Update stats for new writeback behavior.

--HG--
extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14

1 files changed, 64 insertions, 67 deletions

diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
index 7a3645f45..1f2416ce1 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,21 +1,21 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2112807                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 183960                       # Number of bytes of host memory used
-host_seconds                                   704.99                       # Real time elapsed on the host
-host_tick_rate                             2937444703                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 679691                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 179024                       # Number of bytes of host memory used
+host_seconds                                  2191.46                       # Real time elapsed on the host
+host_tick_rate                              944252368                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489514761                       # Number of instructions simulated
-sim_seconds                                  2.070879                       # Number of seconds simulated
-sim_ticks                                2070879278000                       # Number of ticks simulated
+sim_seconds                                  2.069290                       # Number of seconds simulated
+sim_ticks                                2069290262000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          402511688                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 23237.386607                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.386607                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 15023.869951                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13023.869951                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_hits              402318223                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4495621000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency     2906593000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_rate          0.000481                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_misses               193465                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   4108691000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency   2519663000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate     0.000481                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_misses          193465                       # number of ReadReq MSHR misses
 system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
@@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.demand_accesses           569358330                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 24335.366840                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 22335.366840                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 21238.275015                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19238.275015                       # average overall mshr miss latency
 system.cpu.dcache.demand_hits               568845259                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     12485771000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency     10896743000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_rate           0.000901                       # miss rate for demand accesses
 system.cpu.dcache.demand_misses                513071                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  11459629000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency   9870601000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate      0.000901                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_misses           513071                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.overall_accesses          569358330                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 24335.366840                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 22335.366840                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 21238.275015                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19238.275015                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits              568845259                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    12485771000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency    10896743000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.000901                       # miss rate for overall accesses
 system.cpu.dcache.overall_misses               513071                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  11459629000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency   9870601000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate     0.000901                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_misses          513071                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 449114                       # number of replacements
 system.cpu.dcache.sampled_refs                 453210                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.519523                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.519132                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                568906446                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              358652000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              358664000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   316430                       # number of writebacks
 system.cpu.icache.ReadReq_accesses         1489519635                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 24978.142077                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24989.071038                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22989.071038                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_hits             1489518537                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       27426000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency       27438000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 1098                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     25230000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency     25242000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_misses            1098                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs            0                       # n
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.demand_accesses          1489519635                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 24978.142077                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24989.071038                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22989.071038                       # average overall mshr miss latency
 system.cpu.icache.demand_hits              1489518537                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        27426000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency        27438000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  1098                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     25230000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     25242000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_misses             1098                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.overall_accesses         1489519635                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 24978.142077                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24989.071038                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22989.071038                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits             1489518537                       # number of overall hits
-system.cpu.icache.overall_miss_latency       27426000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency       27438000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 1098                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     25230000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     25242000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_misses            1098                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -148,7 +148,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                    115                       # number of replacements
 system.cpu.icache.sampled_refs                   1098                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                891.565977                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                891.583823                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1489518537                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
@@ -165,30 +165,27 @@ system.cpu.l2cache.ReadExReq_mshr_misses       259745                       # nu
 system.cpu.l2cache.ReadReq_accesses            194563                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_avg_miss_latency        22000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        11000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 28419                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    3655168000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.853934                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses              166144                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1827584000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.853934                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses         166144                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits                160837                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency     741972000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.173342                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses               33726                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    370986000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.173342                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses          33726                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_accesses          59901                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency        22000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.265455                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        11000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency   1317822000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency   1317778000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_misses            59901                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency    658911000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_misses        59901                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.Writeback_accesses          316430                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_miss_rate              1                       # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses            316430                       # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate            1                       # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses       316430                       # number of Writeback MSHR misses
+system.cpu.l2cache.Writeback_hits              316430                       # number of Writeback hits
 system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  3.181781                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  3.429642                       # Average number of references to valid blocks.
 system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
@@ -197,14 +194,14 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.demand_accesses             454308                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  28419                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     9369558000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.937446                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses               425889                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits                 160837                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     6456362000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.645974                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               293471                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   4684779000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.937446                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses          425889                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency   3228181000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.645974                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          293471                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
@@ -212,14 +209,14 @@ system.cpu.l2cache.overall_accesses            454308                       # nu
 system.cpu.l2cache.overall_avg_miss_latency        22000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        11000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                 28419                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    9369558000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.937446                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses              425889                       # number of overall misses
+system.cpu.l2cache.overall_hits                160837                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    6456362000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.645974                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              293471                       # number of overall misses
 system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   4684779000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.937446                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses         425889                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency   3228181000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.645974                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         293471                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -231,15 +228,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued            0
 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements                 18200                       # number of replacements
-system.cpu.l2cache.sampled_refs                 19573                       # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements                 82889                       # number of replacements
+system.cpu.l2cache.sampled_refs                 98333                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              8449.130406                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   62277                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             16360.484779                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  337247                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.writebacks                   61877                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4141758556                       # number of cpu cycles simulated
+system.cpu.numCycles                       4138580524                       # number of cpu cycles simulated
 system.cpu.num_insts                       1489514761                       # Number of instructions executed
 system.cpu.num_refs                         569364430                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              19                       # Number of system calls