Stats: Update the stats.

--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8

1 files changed, 22 insertions, 22 deletions

diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
index e732be59f..2a33edee7 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1190065                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 201788                       # Number of bytes of host memory used
-host_seconds                                  1251.63                       # Real time elapsed on the host
-host_tick_rate                             1654548560                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1120793                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 183848                       # Number of bytes of host memory used
+host_seconds                                  1328.98                       # Real time elapsed on the host
+host_tick_rate                             1558243449                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  1489514860                       # Number of instructions simulated
-sim_seconds                                  2.070875                       # Number of seconds simulated
-sim_ticks                                2070875212000                       # Number of ticks simulated
+sim_insts                                  1489514761                       # Number of instructions simulated
+sim_seconds                                  2.070880                       # Number of seconds simulated
+sim_ticks                                2070879986000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          402511688                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149                       # average ReadReq mshr miss latency
@@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                 449136                       # number of replacements
 system.cpu.dcache.sampled_refs                 453232                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.520244                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.519446                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                568906424                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              358125000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              358580000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   316447                       # number of writebacks
-system.cpu.icache.ReadReq_accesses         1489514861                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses         1489519635                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 24978.142077                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1489513763                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits             1489518537                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       27426000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 1098                       # number of ReadReq misses
@@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # ms
 system.cpu.icache.ReadReq_mshr_misses            1098                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               1356569.911658                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               1356574.259563                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1489514861                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses          1489519635                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 24978.142077                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1489513763                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits              1489518537                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        27426000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  1098                       # number of demand (read+write) misses
@@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses             1098                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses         1489514861                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses         1489519635                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 24978.142077                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1489513763                       # number of overall hits
+system.cpu.icache.overall_hits             1489518537                       # number of overall hits
 system.cpu.icache.overall_miss_latency       27426000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 1098                       # number of overall misses
@@ -148,8 +148,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                    115                       # number of replacements
 system.cpu.icache.sampled_refs                   1098                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                891.566276                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1489513763                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                891.566024                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1489518537                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                 18201                       # number of replacements
 system.cpu.l2cache.sampled_refs                 19574                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse              8449.172652                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              8449.165713                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   62289                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                     2070875212000                       # number of cpu cycles simulated
-system.cpu.num_insts                       1489514860                       # Number of instructions executed
-system.cpu.num_refs                         569359656                       # Number of memory references
+system.cpu.numCycles                     2070879986000                       # number of cpu cycles simulated
+system.cpu.num_insts                       1489514761                       # Number of instructions executed
+system.cpu.num_refs                         569364430                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              19                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------