diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-12 19:43:55 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-12 19:43:55 -0400 |
commit | d114e5fae6ffb83a1145208532def7654cc9dd75 (patch) | |
tree | d54b53635428baefbb0ef25715e1059a2bad1185 /tests/long/00.gzip/ref/sparc/linux/simple-timing | |
parent | 02353a60ee6ce831302067aae38bc31b739f14e5 (diff) | |
download | gem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz |
Regression: Update stats for cache changes.
--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux/simple-timing')
3 files changed, 138 insertions, 123 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index ad1db1010..8f0821576 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus workload +children=dcache icache l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false @@ -24,27 +24,28 @@ max_loads_any_thread=0 phase=0 progress_interval=0 system=system +tracer=system.cpu.tracer workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -52,12 +53,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -90,12 +89,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=10000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -128,12 +125,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -151,6 +146,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 @@ -174,7 +172,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index fc8b89b1e..e732be59f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 529254 # Simulator instruction rate (inst/s) -host_mem_usage 154916 # Number of bytes of host memory used -host_seconds 2814.36 # Real time elapsed on the host -host_tick_rate 733354350 # Simulator tick rate (ticks/s) +host_inst_rate 1190065 # Simulator instruction rate (inst/s) +host_mem_usage 201788 # Number of bytes of host memory used +host_seconds 1251.63 # Real time elapsed on the host +host_tick_rate 1654548560 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 2.063927 # Number of seconds simulated -sim_ticks 2063926516000 # Number of ticks simulated +sim_seconds 2.070875 # Number of seconds simulated +sim_ticks 2070875212000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks. @@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses -system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses +system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568905105 # number of overall hits -system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses -system.cpu.dcache.overall_misses 453225 # number of overall misses +system.cpu.dcache.overall_hits 568845227 # number of overall hits +system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses +system.cpu.dcache.overall_misses 513103 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.520244 # Cycle average of tags in use system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 358125000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316447 # number of writebacks system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25230000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25230000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489513763 # number of overall hits -system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25230000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,61 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.566276 # Cycle average of tags in use system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency +system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 743583 # number of overall hits -system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 27194 # number of overall misses +system.cpu.l2cache.overall_hits 28424 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 425906 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -214,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2632 # number of replacements -system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 18201 # number of replacements +system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use -system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8449.172652 # Cycle average of tags in use +system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 2531 # number of writebacks +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2063926516000 # number of cpu cycles simulated +system.cpu.numCycles 2070875212000 # number of cpu cycles simulated system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_refs 569359656 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 3741c6499..6d07eec7c 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 13:36:53 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 12 2007 12:23:15 +M5 started Sun Aug 12 16:24:16 2007 +M5 executing on zeep command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2063926516000 because target called exit() +Exiting @ tick 2070875212000 because target called exit() |