diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 02:20:40 -0500 |
| commit | 8833b4cd44457d50b45a4dfe642cdb5e51c0889d (patch) | |
| tree | 64417a9e2d759dc367848de4b7ee117b3903dc54 /tests/long/00.gzip/ref/sparc/linux | |
| parent | ec1a4cbbc73ecc1d7456d11c571c425e226a7d3b (diff) | |
| download | gem5-8833b4cd44457d50b45a4dfe642cdb5e51c0889d.tar.xz | |
Bus: Update the stats for the recent bus fix.
--HG--
extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux')
8 files changed, 355 insertions, 351 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 502266ba1..857d77efe 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -354,6 +354,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -383,6 +384,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index 3e584c89f..a32e8681e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 185907621 # Number of BTB hits -global.BPredUnit.BTBLookups 211172077 # Number of BTB lookups +global.BPredUnit.BTBHits 181883102 # Number of BTB hits +global.BPredUnit.BTBLookups 205056000 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 84388329 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 259737867 # Number of conditional branches predicted -global.BPredUnit.lookups 259737867 # Number of BP lookups +global.BPredUnit.condIncorrect 84375502 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted +global.BPredUnit.lookups 253548806 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 60132 # Simulator instruction rate (inst/s) -host_mem_usage 181784 # Number of bytes of host memory used -host_seconds 23375.38 # Real time elapsed on the host -host_tick_rate 47481565 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 469164607 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 147914514 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 750060478 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 305538857 # Number of stores inserted to the mem dependence unit. +host_inst_rate 116576 # Simulator instruction rate (inst/s) +host_mem_usage 226608 # Number of bytes of host memory used +host_seconds 12057.44 # Real time elapsed on the host +host_tick_rate 91455071 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 303434180 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405610551 # Number of instructions simulated -sim_seconds 1.109900 # Number of seconds simulated -sim_ticks 1109899556500 # Number of ticks simulated +sim_insts 1405610550 # Number of instructions simulated +sim_seconds 1.102714 # Number of seconds simulated +sim_ticks 1102714100000 # Number of ticks simulated system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8131436 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8144258 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1976139127 +system.cpu.commit.COM:committed_per_cycle.samples 1965947566 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1095749998 5544.90% - 1 581465878 2942.43% - 2 120709498 610.84% - 3 119935544 606.92% - 4 28050272 141.94% - 5 7339488 37.14% - 6 10411639 52.69% - 7 4345374 21.99% - 8 8131436 41.15% + 0 1089819992 5543.48% + 1 575192807 2925.78% + 2 120683737 613.87% + 3 121997081 620.55% + 4 27903521 141.93% + 5 7399306 37.64% + 6 10435277 53.08% + 7 4371587 22.24% + 8 8144258 41.43% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489528974 # Number of instructions committed -system.cpu.commit.COM:loads 402516087 # Number of loads committed +system.cpu.commit.COM:count 1489528973 # Number of instructions committed +system.cpu.commit.COM:loads 402516086 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569373869 # Number of memory references committed +system.cpu.commit.COM:refs 569373868 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84388329 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489528974 # The number of committed instructions +system.cpu.commit.branchMispredicts 84375502 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1415029138 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405610551 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405610551 # Number of Instructions Simulated -system.cpu.cpi 1.579242 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.579242 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 423053343 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15772.083502 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2729.132935 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 422816175 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3740633500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 237168 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 599122 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 647263000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 237168 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 1379622895 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405610550 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated +system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 430903803 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000527 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000527 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 7087.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5087.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 283500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 203500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165053818 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 45542.600793 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.879810 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164707416 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15776048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 346402 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1802638 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2049619000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 346402 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 165064291 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 341979 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1146.620565 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1192.736607 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 588107161 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33443.599740 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency -system.cpu.dcache.demand_hits 587523591 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19516681500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000992 # miss rate for demand accesses -system.cpu.dcache.demand_misses 583570 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2401760 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 2696882000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 583570 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 595968094 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 47263.919107 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency +system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000955 # miss rate for demand accesses +system.cpu.dcache.demand_misses 569002 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000955 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 588107161 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33443.599740 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 595968094 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 47263.919107 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 587523591 # number of overall hits -system.cpu.dcache.overall_miss_latency 19516681500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000992 # miss rate for overall accesses -system.cpu.dcache.overall_misses 583570 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2401760 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 2696882000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 583570 # number of overall MSHR misses +system.cpu.dcache.overall_hits 595399092 # number of overall hits +system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000955 # miss rate for overall accesses +system.cpu.dcache.overall_misses 569002 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000955 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 508363 # number of replacements -system.cpu.dcache.sampled_refs 512459 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 495151 # number of replacements +system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.764839 # Cycle average of tags in use -system.cpu.dcache.total_refs 587596028 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 80528000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 343236 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 411423589 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3483733335 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 768911971 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 792962132 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 243659831 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2841435 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 259737867 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 358807696 # Number of cache lines fetched -system.cpu.fetch.Cycles 1213889868 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 12053122 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3775936768 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 90315783 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.117010 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 358807696 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 185907621 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.701026 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use +system.cpu.dcache.total_refs 595470173 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338813 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3446272352 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 768408181 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 782722330 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239479384 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2858739 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 253548806 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 356679455 # Number of cache lines fetched +system.cpu.fetch.Cycles 1203440686 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10248277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3739797008 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 90313792 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114966 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 356679455 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 181883102 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.695724 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2219798958 +system.cpu.fetch.rateDist.samples 2205426950 system.cpu.fetch.rateDist.min_value 0 - 0 1364716830 6147.93% - 1 258967518 1166.63% - 2 83143428 374.55% - 3 38353275 172.78% - 4 87812104 395.59% - 5 41187584 185.55% - 6 32935987 148.37% - 7 20637545 92.97% - 8 292044687 1315.64% + 0 1358665764 6160.56% + 1 256941668 1165.04% + 2 81115553 367.80% + 3 38329197 173.79% + 4 87812032 398.16% + 5 41184299 186.74% + 6 30948569 140.33% + 7 20663338 93.69% + 8 289766530 1313.88% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 358807628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7480.059084 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5308.714919 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 358806274 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10128000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 356679310 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9956.762749 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 7188000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 264997.248154 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 263620.071693 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 358807628 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7480.059084 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency -system.cpu.icache.demand_hits 358806274 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10128000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 356679310 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9956.762749 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency +system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7188000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 358807628 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7480.059084 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency +system.cpu.icache.overall_accesses 356679310 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9956.762749 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 358806274 # number of overall hits -system.cpu.icache.overall_miss_latency 10128000 # number of overall miss cycles +system.cpu.icache.overall_hits 356677957 # number of overall hits +system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1354 # number of overall misses -system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7188000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1353 # number of overall misses +system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -222,180 +222,180 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 206 # number of replacements -system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks. +system.cpu.icache.replacements 208 # number of replacements +system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1043.219654 # Cycle average of tags in use -system.cpu.icache.total_refs 358806274 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1040.462476 # Cycle average of tags in use +system.cpu.icache.total_refs 356677957 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 127603528 # Number of branches executed -system.cpu.iew.EXEC:nop 356521630 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.852457 # Inst execution rate -system.cpu.iew.EXEC:refs 746062439 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207373942 # Number of stores executed +system.cpu.idleCycles 1251 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 127605912 # Number of branches executed +system.cpu.iew.EXEC:nop 350340512 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.854314 # Inst execution rate +system.cpu.iew.EXEC:refs 751911003 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 205327510 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1493031889 # num instructions consuming a value -system.cpu.iew.WB:count 1859658958 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.962656 # average fanout of values written-back +system.cpu.iew.WB:consumers 1480058841 # num instructions consuming a value +system.cpu.iew.WB:count 1846013592 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.961975 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1437276141 # num instructions producing a value -system.cpu.iew.WB:rate 0.837760 # insts written-back per cycle -system.cpu.iew.WB:sent 1869182188 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 90142069 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 426198 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 750060478 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21374388 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17119395 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 305538857 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2904603510 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 538688497 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 102140333 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1892283108 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 19664 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1423779046 # num instructions producing a value +system.cpu.iew.WB:rate 0.837032 # insts written-back per cycle +system.cpu.iew.WB:sent 1859125771 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 92169328 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 589466 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 741821167 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21373722 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17131490 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 303434180 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2869215575 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 546583493 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 102562223 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1884127631 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 34476 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 4147 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 243659831 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 32077 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6237 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239479384 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64949 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115016780 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 46174 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115050739 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 46193 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6167113 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 347544391 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 138681075 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6167113 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1511945 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 88630124 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.633215 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.633215 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1994423441 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6187227 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 339305081 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 136576398 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6187227 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1512324 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 90657004 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.637341 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.637341 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1986689854 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1187879871 59.56% # Type of FU issued + IntAlu 1179867838 59.39% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2994707 0.15% # Type of FU issued + FloatAdd 3034528 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 575372220 28.85% # Type of FU issued - MemWrite 228176643 11.44% # Type of FU issued + MemRead 573302529 28.86% # Type of FU issued + MemWrite 230484959 11.60% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 4059109 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002035 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3941211 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143359 3.53% # attempts to use FU when none available + IntAlu 143231 3.63% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 223654 5.51% # attempts to use FU when none available + FloatAdd 224126 5.69% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3316143 81.70% # attempts to use FU when none available - MemWrite 375953 9.26% # attempts to use FU when none available + MemRead 3231195 81.98% # attempts to use FU when none available + MemWrite 342659 8.69% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2219798958 +system.cpu.iq.ISSUE:issued_per_cycle.samples 2205426950 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1092127511 4919.94% - 1 592160180 2667.63% - 2 301053468 1356.22% - 3 164170369 739.57% - 4 50664484 228.24% - 5 13356785 60.17% - 6 5787626 26.07% - 7 350679 1.58% - 8 127856 0.58% + 0 1088269781 4934.51% + 1 585554812 2655.06% + 2 294018661 1333.16% + 3 167298864 758.58% + 4 47518780 215.46% + 5 16542191 75.01% + 6 5287334 23.97% + 7 801167 3.63% + 8 135360 0.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.898470 # Inst issue rate -system.cpu.iq.iqInstsAdded 2526420335 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1994423441 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21661545 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1099219582 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 637228 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19418044 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1350410508 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 275291 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4810.268044 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.268044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1324223500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.900818 # Inst issue rate +system.cpu.iq.iqInstsAdded 2497204504 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1986689854 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21670559 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1069656656 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 613177 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19427058 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1294993594 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 272224 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 5810.711032 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.711032 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1581815000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 275291 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 773641500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 272224 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 765143000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 275291 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 238522 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4132.403832 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2132.403832 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 203557 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 144489500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.146590 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34965 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 74559500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146590 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34965 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 71158 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4269.526968 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2269.653447 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 303811000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 272224 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5108.225294 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.225294 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 193435 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 178486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.152998 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34941 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 73663500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.152998 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34941 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 69802 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.366465 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.524054 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 363694000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 71158 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 161504000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 69802 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154299000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 71158 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 343236 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 343236 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 69802 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338813 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338813 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.069566 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.927611 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 513813 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4733.874607 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 203557 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1468713000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.603831 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 310256 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 500600 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5730.801035 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 193435 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1760301500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.613594 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 307165 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 848201000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.603831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 310256 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 838806500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.613594 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 307165 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 513813 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4733.874607 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 500600 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5730.801035 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 203557 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1468713000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.603831 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 310256 # number of overall misses +system.cpu.l2cache.overall_hits 193435 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1760301500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.613594 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 307165 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 848201000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.603831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 310256 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 838806500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.613594 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 307165 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -407,32 +407,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 84454 # number of replacements -system.cpu.l2cache.sampled_refs 99919 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84439 # number of replacements +system.cpu.l2cache.sampled_refs 99904 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16408.026694 # Cycle average of tags in use -system.cpu.l2cache.total_refs 406627 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16410.322643 # Cycle average of tags in use +system.cpu.l2cache.total_refs 392384 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61955 # number of writebacks -system.cpu.numCycles 2219799114 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14139757 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244771059 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 15246 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 833407854 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 22992244 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4967044310 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3128619871 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2442811426 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 727931337 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 243659831 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32162189 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1198040367 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368497990 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 22007928 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 169677376 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21764302 # count of temporary serializing insts renamed -system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 2205428201 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14473307 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 33045 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 831088395 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 23088197 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4934346294 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3102230072 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2427283324 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 719527974 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239479384 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32278343 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1182512267 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 368579547 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 22008768 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 170264872 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21765105 # count of temporary serializing insts renamed +system.cpu.timesIdled 5236 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 19 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index eb1796ead..320065be7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index eacf59013..8ee292d5b 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -31,14 +31,14 @@ Uncompressed data compared correctly Tested 1MB buffer: OK! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 13 2008 00:33:29 -M5 started Wed Feb 13 10:56:54 2008 -M5 executing on zizzer +M5 compiled Feb 24 2008 13:27:50 +M5 started Mon Feb 25 16:16:45 2008 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1109899556500 because target called exit() +Exiting @ tick 1102714100000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 508d9942a..6c34c6dee 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -152,6 +152,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side @@ -181,6 +182,7 @@ type=Bus block_size=64 bus_id=0 clock=1000 +header_cycles=1 responder_set=false width=64 port=system.physmem.port[0] system.cpu.l2cache.mem_side diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 1f2416ce1..49a7103b2 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 679691 # Simulator instruction rate (inst/s) -host_mem_usage 179024 # Number of bytes of host memory used -host_seconds 2191.46 # Real time elapsed on the host -host_tick_rate 944252368 # Simulator tick rate (ticks/s) +host_inst_rate 1554729 # Simulator instruction rate (inst/s) +host_mem_usage 223840 # Number of bytes of host memory used +host_seconds 958.05 # Real time elapsed on the host +host_tick_rate 2160793398 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.069290 # Number of seconds simulated -sim_ticks 2069290262000 # Number of ticks simulated +sim_seconds 2.070158 # Number of seconds simulated +sim_ticks 2070157841000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15023.869951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13023.869951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 16192.525780 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13192.525780 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2906593000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3132687000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2519663000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2552292000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7990150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8629360000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7350938000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7670542000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 21238.275015 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19238.275015 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 22924.794034 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10896743000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 11762047000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9870601000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10222834000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 21238.275015 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19238.275015 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22924.794034 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568845259 # number of overall hits -system.cpu.dcache.overall_miss_latency 10896743000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 11762047000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses system.cpu.dcache.overall_misses 513071 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9870601000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10222834000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449114 # number of replacements system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.519132 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.499108 # Cycle average of tags in use system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 358664000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 373865000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316430 # number of writebacks system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 24989.071038 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22989.071038 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 26988.160291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23988.160291 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 27438000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 29633000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 25242000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26339000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 24989.071038 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22989.071038 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 26988.160291 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 27438000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 29633000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25242000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26339000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 24989.071038 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22989.071038 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 26988.160291 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489518537 # number of overall hits -system.cpu.icache.overall_miss_latency 27438000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 29633000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25242000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26339000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.583823 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.563559 # Cycle average of tags in use system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5714390000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5974135000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 741972000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 775698000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.265455 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232066 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1317778000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1377677000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles @@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6456362000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 6749833000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 160837 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6456362000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 6749833000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses system.cpu.l2cache.overall_misses 293471 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 82889 # number of replacements system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16360.484779 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16360.066474 # Cycle average of tags in use system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61877 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4138580524 # number of cpu cycles simulated +system.cpu.numCycles 4140315682 # number of cpu cycles simulated system.cpu.num_insts 1489514761 # Number of instructions executed system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index eb1796ead..2a6ac4135 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 2a9392257..ce05ca938 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -31,14 +31,14 @@ Uncompressed data compared correctly Tested 1MB buffer: OK! M5 Simulator System -Copyright (c) 2001-2006 +Copyright (c) 2001-2008 The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 13 2008 00:33:29 -M5 started Wed Feb 13 17:45:44 2008 -M5 executing on zizzer +M5 compiled Feb 24 2008 13:27:50 +M5 started Mon Feb 25 16:16:45 2008 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2069290262000 because target called exit() +Exiting @ tick 2070157841000 because target called exit() |