tests: updates for stat name change

2 files changed, 16 insertions, 16 deletions

diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index 9d435e3a3..750396309 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,8 +5,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 19 2011 12:19:46
-M5 started Apr 19 2011 12:20:08
+M5 compiled Apr 21 2011 13:27:10
+M5 started Apr 21 2011 13:30:00
 M5 executing on maize
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 04c8a25b6..9d595253b 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 280029                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206320                       # Number of bytes of host memory used
-host_seconds                                  5019.49                       # Real time elapsed on the host
-host_tick_rate                              116031336                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 154343                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212152                       # Number of bytes of host memory used
+host_seconds                                  9107.03                       # Real time elapsed on the host
+host_tick_rate                               63952564                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1405604152                       # Number of instructions simulated
 sim_seconds                                  0.582418                       # Number of seconds simulated
@@ -243,16 +243,16 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewLSQFullEvents                  8462                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.iewSquashCycles               27885594                       # Number of cycles IEW is squashing
 system.cpu.iew.iewUnblockCycles                128708                       # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked        40205                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads       129748862                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses        35905                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation       460365                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads          237                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads     58644458                       # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores     20174020                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.cacheBlocked         40205                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.forwLoads        129748862                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.ignoredResponses        35905                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.memOrderViolation       460365                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.rescheduledLoads          237                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.squashedLoads     58644458                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedStores     20174020                       # Number of stores squashed
 system.cpu.iew.memOrderViolationEvents         460365                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect       670427                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect        5004860                       # Number of branches that were predicted taken incorrectly