diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-29 00:00:26 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-29 00:00:26 -0800 |
| commit | fa5e3b47c8d541259438c5177ef57232f5317907 (patch) | |
| tree | 55a6a447319c0aacfc3565a82bf622c4f92f959b /tests/long/00.gzip/ref/sparc/linux | |
| parent | 16e99e4677c24147e09ff10d375751a7b114a8d7 (diff) | |
| download | gem5-fa5e3b47c8d541259438c5177ef57232f5317907.tar.xz | |
SPARC: Fix the initial stack to match what the Linux kernel does.
--HG--
extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
Diffstat (limited to 'tests/long/00.gzip/ref/sparc/linux')
9 files changed, 382 insertions, 382 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index 2bc9bd06b..d1cd0392d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 183932235 # Number of BTB hits -global.BPredUnit.BTBLookups 208089812 # Number of BTB lookups +global.BPredUnit.BTBHits 183466846 # Number of BTB hits +global.BPredUnit.BTBLookups 207793260 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 84447535 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted -global.BPredUnit.lookups 256528366 # Number of BP lookups +global.BPredUnit.condIncorrect 83278105 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 256324661 # Number of conditional branches predicted +global.BPredUnit.lookups 256324661 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 135731 # Simulator instruction rate (inst/s) +host_inst_rate 134979 # Simulator instruction rate (inst/s) host_mem_usage 184868 # Number of bytes of host memory used -host_seconds 10355.84 # Real time elapsed on the host -host_tick_rate 105976601 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 302069201 # Number of stores inserted to the mem dependence unit. +host_seconds 10413.54 # Real time elapsed on the host +host_tick_rate 105577175 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 466269652 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 147193104 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 745571091 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 302033091 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405610550 # Number of instructions simulated -sim_seconds 1.097477 # Number of seconds simulated -sim_ticks 1097476890500 # Number of ticks simulated +sim_insts 1405610551 # Number of instructions simulated +sim_seconds 1.099432 # Number of seconds simulated +sim_ticks 1099431876500 # Number of ticks simulated system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 9005633 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8078603 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1955398373 +system.cpu.commit.COM:committed_per_cycle.samples 1959484906 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1080294174 5524.68% - 1 576226777 2946.85% - 2 118746551 607.28% - 3 121516054 621.44% - 4 26673737 136.41% - 5 9328411 47.71% - 6 9370387 47.92% - 7 4236649 21.67% - 8 9005633 46.06% + 0 1081809823 5520.89% + 1 578489124 2952.25% + 2 119799391 611.38% + 3 120342305 614.15% + 4 28015342 142.97% + 5 8264992 42.18% + 6 10398281 53.07% + 7 4287045 21.88% + 8 8078603 41.23% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489528973 # Number of instructions committed -system.cpu.commit.COM:loads 402516086 # Number of loads committed +system.cpu.commit.COM:count 1489528974 # Number of instructions committed +system.cpu.commit.COM:loads 402516087 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569373868 # Number of memory references committed +system.cpu.commit.COM:refs 569373869 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 84447535 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions +system.cpu.commit.branchMispredicts 83278105 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489528974 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1399558822 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405610550 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated -system.cpu.cpi 1.561566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.561566 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 422711094 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 22402.386533 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4523.374198 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 422473888 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5313980500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 237206 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 708416 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1072971500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 237206 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 1400697440 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405610551 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405610551 # Number of Instructions Simulated +system.cpu.cpi 1.564348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.564348 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 419995861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 23168.139352 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4590.459997 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 419768838 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5259700500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000541 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 708214 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1042140000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000541 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 7025 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5025 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 7075 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5075 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 281000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 283000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 201000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 203000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165053813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 45668.908621 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.368381 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164707389 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15820806000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 346424 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1802643 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2049572000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 346424 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 165070864 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 45748.072998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5912.450070 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164728882 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 15645017500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 341982 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1785592 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2021951500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 341982 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1145.843040 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1170.889248 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 587764907 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36212.645854 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency -system.cpu.dcache.demand_hits 587181277 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21134786500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000993 # miss rate for demand accesses -system.cpu.dcache.demand_misses 583630 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2511059 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3122543500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000993 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 583630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 585066725 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36739.076107 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5384.999253 # average overall mshr miss latency +system.cpu.dcache.demand_hits 584497720 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 20904718000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000973 # miss rate for demand accesses +system.cpu.dcache.demand_misses 569005 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2493806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3064091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000973 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 569005 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 587764907 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36212.645854 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 585066725 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36739.076107 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5384.999253 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 587181277 # number of overall hits -system.cpu.dcache.overall_miss_latency 21134786500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000993 # miss rate for overall accesses -system.cpu.dcache.overall_misses 583630 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2511059 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3122543500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000993 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 583630 # number of overall MSHR misses +system.cpu.dcache.overall_hits 584497720 # number of overall hits +system.cpu.dcache.overall_miss_latency 20904718000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000973 # miss rate for overall accesses +system.cpu.dcache.overall_misses 569005 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2493806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3064091500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000973 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 569005 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 508412 # number of replacements -system.cpu.dcache.sampled_refs 512508 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 495156 # number of replacements +system.cpu.dcache.sampled_refs 499252 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.762102 # Cycle average of tags in use -system.cpu.dcache.total_refs 587253725 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 80526000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 343259 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 406688141 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3452580675 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 760521931 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 785512506 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239555254 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2675795 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 256528366 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 355016142 # Number of cache lines fetched -system.cpu.fetch.Cycles 1201036760 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10894008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3738352844 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 89458561 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.116872 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 355016142 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 183932235 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.703158 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.762604 # Cycle average of tags in use +system.cpu.dcache.total_refs 584568799 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 80527000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338816 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 411395405 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3450318732 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 760917725 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 784307506 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239378692 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2864270 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 256324661 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354575767 # Number of cache lines fetched +system.cpu.fetch.Cycles 1200225955 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10817828 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3736159022 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 88285851 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.116571 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354575767 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 183466846 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.699132 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2194953627 +system.cpu.fetch.rateDist.samples 2198863598 system.cpu.fetch.rateDist.min_value 0 - 0 1348933053 6145.61% - 1 256313247 1167.74% - 2 82698191 376.77% - 3 38326183 174.61% - 4 84519360 385.06% - 5 41105906 187.27% - 6 32923583 150.00% - 7 20556634 93.65% - 8 289577470 1319.29% + 0 1353213454 6154.15% + 1 256648572 1167.19% + 2 82308171 374.32% + 3 38352394 174.42% + 4 84338167 383.55% + 5 41018803 186.55% + 6 32950598 149.85% + 7 20580857 93.60% + 8 289452582 1316.37% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 355016079 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7452.363368 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5292.836041 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 355014725 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10090500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 354575701 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7464.153732 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5301.182557 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354574348 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 10099000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 7166500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 7172500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 262196.990399 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 262065.297857 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 355016079 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7452.363368 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency -system.cpu.icache.demand_hits 355014725 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10090500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 354575701 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7464.153732 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5301.182557 # average overall mshr miss latency +system.cpu.icache.demand_hits 354574348 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 10099000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7166500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 7172500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 355016079 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7452.363368 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency +system.cpu.icache.overall_accesses 354575701 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7464.153732 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5301.182557 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 355014725 # number of overall hits -system.cpu.icache.overall_miss_latency 10090500 # number of overall miss cycles +system.cpu.icache.overall_hits 354574348 # number of overall hits +system.cpu.icache.overall_miss_latency 10099000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1354 # number of overall misses -system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7166500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1353 # number of overall misses +system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 7172500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -222,183 +222,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 208 # number of replacements -system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks. +system.cpu.icache.replacements 206 # number of replacements +system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1042.348080 # Cycle average of tags in use -system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1042.511733 # Cycle average of tags in use +system.cpu.icache.total_refs 354574348 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 155 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 128778452 # Number of branches executed -system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate -system.cpu.iew.EXEC:refs 753461994 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 210026063 # Number of stores executed +system.cpu.idleCycles 156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 126703550 # Number of branches executed +system.cpu.iew.EXEC:nop 354855190 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.857840 # Inst execution rate +system.cpu.iew.EXEC:refs 743977888 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207424101 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1497813793 # num instructions consuming a value -system.cpu.iew.WB:count 1867109874 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963032 # average fanout of values written-back +system.cpu.iew.WB:consumers 1489344820 # num instructions consuming a value +system.cpu.iew.WB:count 1853646743 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.962725 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1442442170 # num instructions producing a value -system.cpu.iew.WB:rate 0.850637 # insts written-back per cycle -system.cpu.iew.WB:sent 1877161076 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 745627925 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21367021 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17089542 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 302069201 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2889153048 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 543435931 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 103575555 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1900567912 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 61243 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1433829937 # num instructions producing a value +system.cpu.iew.WB:rate 0.843002 # insts written-back per cycle +system.cpu.iew.WB:sent 1863156113 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 89061580 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 454846 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 745571091 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21380590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17115349 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 302033091 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2890291179 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 536553787 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 102628561 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1886272937 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61790 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9772 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239555254 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 95884 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9769 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239378692 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 96720 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 119997179 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 80650 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 115831794 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 46103 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5250080 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 343111839 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 135211419 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5250080 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1516982 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 89810699 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.640383 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.640383 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2004143467 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 5246415 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 343055004 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 135175309 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5246415 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1515897 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 87545683 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.639244 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639244 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1988901498 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 1186366605 59.20% # Type of FU issued + IntAlu 1181296004 59.39% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3003253 0.15% # Type of FU issued + FloatAdd 3002910 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 584611723 29.17% # Type of FU issued - MemWrite 230161886 11.48% # Type of FU issued + MemRead 577085119 29.02% # Type of FU issued + MemWrite 227517465 11.44% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6010355 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002999 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 5041207 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002535 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 143340 2.38% # attempts to use FU when none available + IntAlu 143450 2.85% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 241345 4.02% # attempts to use FU when none available + FloatAdd 241552 4.79% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5244225 87.25% # attempts to use FU when none available - MemWrite 381445 6.35% # attempts to use FU when none available + MemRead 4269288 84.69% # attempts to use FU when none available + MemWrite 386917 7.68% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2194953627 +system.cpu.iq.ISSUE:issued_per_cycle.samples 2198863598 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1076765226 4905.64% - 1 582878371 2655.54% - 2 298125643 1358.23% - 3 159003575 724.41% - 4 52530250 239.32% - 5 16707223 76.12% - 6 8404252 38.29% - 7 392238 1.79% - 8 146849 0.67% + 0 1077268268 4899.20% + 1 589751497 2682.07% + 2 298052129 1355.48% + 3 161348809 733.78% + 4 50984862 231.87% + 5 14316945 65.11% + 6 6653209 30.26% + 7 347143 1.58% + 8 140736 0.64% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.913069 # Inst issue rate -system.cpu.iq.iqInstsAdded 2513084593 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2004143467 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21683766 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1087893079 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 3817087 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19440265 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1299740082 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 275303 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4888.651776 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2888.651776 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1345860500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.904513 # Inst issue rate +system.cpu.iq.iqInstsAdded 2513738089 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1988901498 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21697900 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1088741621 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1800387 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19454399 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1337770636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 272229 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4890.764761 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2890.764761 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1331408000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 275303 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 795254500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 272229 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 786950000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 275303 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 238559 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4206.099871 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.099871 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 56424 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 766078000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.763480 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 182135 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 401808000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.763480 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 182135 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 71169 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4205.419494 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2205.419494 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 299295500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 272229 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4206.281488 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.281488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 48944 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 754741500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.785687 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 179432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 395877500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.785687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 179432 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 69800 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4203.058739 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2203.058739 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 293373500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 71169 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 156957500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 69800 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 153773500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 71169 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 343259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 69800 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338816 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 343259 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 338816 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 343259 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 338816 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.652891 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.378074 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 513862 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4616.884693 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 56424 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2111938500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.890196 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 457438 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 500605 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4618.839129 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.839129 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 48944 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2086149500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.902230 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 451661 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1197062500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.890196 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 457438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1182827500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.902230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 451661 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 513862 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4616.884693 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 500605 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4618.839129 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.839129 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 56424 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2111938500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.890196 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 457438 # number of overall misses +system.cpu.l2cache.overall_hits 48944 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2086149500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.902230 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 451661 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1197062500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.890196 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 457438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1182827500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.902230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 451661 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -410,31 +410,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 19390 # number of replacements -system.cpu.l2cache.sampled_refs 20786 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 19383 # number of replacements +system.cpu.l2cache.sampled_refs 20779 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8527.413561 # Cycle average of tags in use -system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8526.680719 # Cycle average of tags in use +system.cpu.l2cache.total_refs 90972 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2194953782 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 47407 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 822770114 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 20101500 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4935577703 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3109070263 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2428488542 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 723045080 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239555254 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 28402170 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1183717485 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368180121 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21968418 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 159248004 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21723083 # count of temporary serializing insts renamed +system.cpu.numCycles 2198863754 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14237531 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244771059 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 16 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 47995 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 823614564 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 22929026 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4933879352 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3107597262 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2428032497 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 721097012 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239378692 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 32149684 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1183261438 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 368386115 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 22018362 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 169719231 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21772913 # count of temporary serializing insts renamed system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index 320065be7..bb7dd4e98 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7008 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index e909eac0e..debbd670a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 15:13:45 -M5 started Wed Nov 28 15:13:46 2007 +M5 compiled Nov 28 2007 18:29:37 +M5 started Wed Nov 28 18:29:38 2007 M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1097476890500 because target called exit() +Exiting @ tick 1099431876500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index d7e3d851a..a5fcdb950 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3593860 # Simulator instruction rate (inst/s) +host_inst_rate 3930303 # Simulator instruction rate (inst/s) host_mem_usage 176592 # Number of bytes of host memory used -host_seconds 414.46 # Real time elapsed on the host -host_tick_rate 1796934585 # Simulator tick rate (ticks/s) +host_seconds 378.98 # Real time elapsed on the host +host_tick_rate 1965156849 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated sim_seconds 0.744760 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr index eb1796ead..802ce964e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 +0: system.remote_gdb.listener: listening for remote gdb on port 7007 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index 7dadd1979..5f4ac4eab 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -36,8 +36,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 15:13:45 -M5 started Wed Nov 28 15:13:46 2007 +M5 compiled Nov 28 2007 18:29:37 +M5 started Wed Nov 28 18:29:38 2007 M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 4187ba610..7a3645f45 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2062336 # Simulator instruction rate (inst/s) -host_mem_usage 183952 # Number of bytes of host memory used -host_seconds 722.25 # Real time elapsed on the host -host_tick_rate 2867275090 # Simulator tick rate (ticks/s) +host_inst_rate 2112807 # Simulator instruction rate (inst/s) +host_mem_usage 183960 # Number of bytes of host memory used +host_seconds 704.99 # Real time elapsed on the host +host_tick_rate 2937444703 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated -sim_seconds 2.070880 # Number of seconds simulated -sim_ticks 2070879986000 # Number of ticks simulated +sim_seconds 2.070879 # Number of seconds simulated +sim_ticks 2070879278000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 23237.386607 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.386607 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4495621000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 4108691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency @@ -31,47 +31,47 @@ system.cpu.dcache.SwapReq_mshr_misses 40 # nu system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7990150000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 7350938000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1255.282200 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 24335.366840 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12485771000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 11459629000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 24335.366840 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22335.366840 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568845227 # number of overall hits -system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles +system.cpu.dcache.overall_hits 568845259 # number of overall hits +system.cpu.dcache.overall_miss_latency 12485771000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513103 # number of overall misses +system.cpu.dcache.overall_misses 513071 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 11459629000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -83,13 +83,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 449136 # number of replacements -system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449114 # number of replacements +system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.519446 # Cycle average of tags in use -system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 358580000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316447 # number of writebacks +system.cpu.dcache.tagsinuse 4095.519523 # Cycle average of tags in use +system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 358652000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316430 # number of writebacks system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency @@ -148,78 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.566024 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.565977 # Cycle average of tags in use system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5714390000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 28419 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 3655168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.853934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 166144 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1827584000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 166144 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 1317822000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 59901 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316430 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 316430 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 316430 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.181781 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 28419 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9369558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.937446 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 425889 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4684779000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.937446 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 425889 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 28424 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 425906 # number of overall misses +system.cpu.l2cache.overall_hits 28419 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9369558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.937446 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 425889 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4684779000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.937446 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 425889 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -231,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 18201 # number of replacements -system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 18200 # number of replacements +system.cpu.l2cache.sampled_refs 19573 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8449.165713 # Cycle average of tags in use -system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8449.130406 # Cycle average of tags in use +system.cpu.l2cache.total_refs 62277 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4141759972 # number of cpu cycles simulated +system.cpu.numCycles 4141758556 # number of cpu cycles simulated system.cpu.num_insts 1489514761 # Number of instructions executed system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index 2a6ac4135..f373aba21 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 +0: system.remote_gdb.listener: listening for remote gdb on port 7009 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 1d8d3bb90..c636a4a25 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 28 2007 15:13:45 -M5 started Wed Nov 28 15:13:46 2007 +M5 compiled Nov 28 2007 18:29:37 +M5 started Wed Nov 28 18:29:38 2007 M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2070879986000 because target called exit() +Exiting @ tick 2070879278000 because target called exit() |