CPU: Update stats now that there's no fetch in the middle of macroops.

2 files changed, 24 insertions, 24 deletions

diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index d7c279dee..12ee4624b 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:50:17
-M5 executing on zizzer
+M5 compiled Feb 24 2009 01:30:29
+M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch
+M5 started Feb 24 2009 01:30:33
+M5 executing on tater
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -43,4 +43,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2080416155000 because target called exit()
+Exiting @ tick 2076000961000 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 5a55fc3e0..9a15c39dd 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1502574                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205236                       # Number of bytes of host memory used
-host_seconds                                   991.31                       # Real time elapsed on the host
-host_tick_rate                             2098643273                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 779483                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204800                       # Number of bytes of host memory used
+host_seconds                                  1910.91                       # Real time elapsed on the host
+host_tick_rate                             1086392421                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1489523295                       # Number of instructions simulated
-sim_seconds                                  2.080416                       # Number of seconds simulated
-sim_ticks                                2080416155000                       # Number of ticks simulated
+sim_seconds                                  2.076001                       # Number of seconds simulated
+sim_ticks                                2076000961000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          402512844                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994                       # average ReadReq mshr miss latency
@@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                 449125                       # number of replacements
 system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4095.205833                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.229973                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                568907765                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              596368000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle              567696000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   316420                       # number of writebacks
-system.cpu.icache.ReadReq_accesses         1489528206                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses         1485113012                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 55848.238482                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1489527099                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits             1485111905                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       61824000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                 1107                       # number of ReadReq misses
@@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # ms
 system.cpu.icache.ReadReq_mshr_misses            1107                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               1345552.934959                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               1341564.503162                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1489528206                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses          1485113012                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency 55848.238482                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1489527099                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits              1485111905                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        61824000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                  1107                       # number of demand (read+write) misses
@@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses             1107                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses         1489528206                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1489527099                       # number of overall hits
+system.cpu.icache.overall_hits             1485111905                       # number of overall hits
 system.cpu.icache.overall_miss_latency       61824000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                 1107                       # number of overall misses
@@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                    118                       # number of replacements
 system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                906.330613                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1489527099                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                906.413769                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1485111905                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses            0
 system.cpu.l2cache.replacements                 82905                       # number of replacements
 system.cpu.l2cache.sampled_refs                 98339                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16356.207611                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             16358.028924                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  337181                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   61861                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       4160832310                       # number of cpu cycles simulated
+system.cpu.numCycles                       4152001922                       # number of cpu cycles simulated
 system.cpu.num_insts                       1489523295                       # Number of instructions executed
 system.cpu.num_refs                         569365767                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              49                       # Number of system calls