diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/00.gzip/ref/sparc | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/long/00.gzip/ref/sparc')
9 files changed, 115 insertions, 33 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 02ce84b2d..239140dc5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index df93e233e..44a2a20b1 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 21:17:52 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 21:17:55 -M5 executing on zizzer +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c2bc04472..2fc2b1f97 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 144426 # Simulator instruction rate (inst/s) -host_mem_usage 207996 # Number of bytes of host memory used -host_seconds 9732.45 # Real time elapsed on the host -host_tick_rate 61799305 # Simulator tick rate (ticks/s) +host_inst_rate 165526 # Simulator instruction rate (inst/s) +host_mem_usage 228372 # Number of bytes of host memory used +host_seconds 8491.76 # Real time elapsed on the host +host_tick_rate 70828550 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.601459 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle system.cpu.commit.COM:count 1489523295 # Number of instructions committed +system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569360986 # Number of memory references committed @@ -160,6 +163,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads +system.cpu.fp_regfile_writes 10422320 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency @@ -259,6 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 21427986 # system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1994642284 # number of integer regfile reads +system.cpu.int_regfile_writes 1296237136 # number of integer regfile writes system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -350,6 +357,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate +system.cpu.iq.fp_alu_accesses 9139758 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 17716192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 8503894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9202883 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1476034706 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4152007639 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1463994823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1798910142 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ @@ -430,7 +445,11 @@ system.cpu.memDep0.conflictingLoads 406523724 # Nu system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 596285867 # number of misc regfile reads +system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes system.cpu.numCycles 1202917849 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers @@ -445,10 +464,14 @@ system.cpu.rename.RENAME:RunCycles 329588798 # Nu system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 33734828 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2890766205 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 2859629611 # The number of ROB reads +system.cpu.rob.rob_writes 3448202738 # The number of ROB writes system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 25252561e..0b3b6266f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index c99734c27..4748a164d 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:19:07 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:57 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index d04149323..16c920737 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1748575 # Simulator instruction rate (inst/s) -host_mem_usage 185740 # Number of bytes of host memory used -host_seconds 851.85 # Real time elapsed on the host -host_tick_rate 874289976 # Simulator tick rate (ticks/s) +host_inst_rate 1524596 # Simulator instruction rate (inst/s) +host_mem_usage 219684 # Number of bytes of host memory used +host_seconds 977.00 # Real time elapsed on the host +host_tick_rate 762300416 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 744764119000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1489528239 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234411208 # number of times the integer registers were written +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 9772b8626..9789f7d05 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 78e3d8264..f2b4b3e16 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:28:00 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 04e7c144d..8bc8178fc 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1333935 # Simulator instruction rate (inst/s) -host_mem_usage 197236 # Number of bytes of host memory used -host_seconds 1116.64 # Real time elapsed on the host -host_tick_rate 1848636408 # Simulator tick rate (ticks/s) +host_inst_rate 594721 # Simulator instruction rate (inst/s) +host_mem_usage 227400 # Number of bytes of host memory used +host_seconds 2504.58 # Real time elapsed on the host +host_tick_rate 824195004 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.064259 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 59035 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234411207 # number of times the integer registers were written +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- |