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authorSteve Reinhardt <stever@gmail.com>2010-09-09 14:40:19 -0400
committerSteve Reinhardt <stever@gmail.com>2010-09-09 14:40:19 -0400
commit9e45ada1718b6df9310757fdc7cd78db4695516f (patch)
treec5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/00.gzip/ref/sparc
parent12497284949cb5418e6bc403723c034aee655666 (diff)
downloadgem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/00.gzip/ref/sparc')
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simout14
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt621
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-timing/simout14
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt195
6 files changed, 427 insertions, 423 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index c00f7a514..659cb8ca7 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -353,7 +353,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index ed5277c40..d11cb55dd 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,5 +1,5 @@
-Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr
+Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jun 6 2010 04:01:36
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 04:02:01
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:05:09
M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -45,4 +45,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1088715493000 because target called exit()
+Exiting @ tick 1088441503500 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 57777fec7..8e3cfada7 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,209 +1,209 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 109148 # Simulator instruction rate (inst/s)
-host_mem_usage 208820 # Number of bytes of host memory used
-host_seconds 12878.07 # Real time elapsed on the host
-host_tick_rate 84540245 # Simulator tick rate (ticks/s)
+host_inst_rate 76473 # Simulator instruction rate (inst/s)
+host_mem_usage 212472 # Number of bytes of host memory used
+host_seconds 18380.70 # Real time elapsed on the host
+host_tick_rate 59216546 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618369 # Number of instructions simulated
-sim_seconds 1.088715 # Number of seconds simulated
-sim_ticks 1088715493000 # Number of ticks simulated
+sim_seconds 1.088442 # Number of seconds simulated
+sim_ticks 1088441503500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 173332559 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 194142411 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 173420048 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 194153919 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 81910123 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 251618660 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 251618660 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 81907161 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 251603669 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 251603669 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 8014877 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 8072747 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1942378796 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1941955406 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.767030 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.200667 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 1072972593 55.24% 55.24% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 568760584 29.28% 84.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 118179777 6.08% 90.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 122167717 6.29% 96.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 27965504 1.44% 98.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 8603273 0.44% 98.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 11084471 0.57% 99.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 4630000 0.24% 99.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 1072656731 55.24% 55.24% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 568585470 29.28% 84.51% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 118066725 6.08% 90.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 122346784 6.30% 96.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 28028862 1.44% 98.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8610798 0.44% 98.78% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 11084197 0.57% 99.35% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 4503092 0.23% 99.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 8072747 0.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1942378796 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1941955406 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489537512 # Number of instructions committed
system.cpu.commit.COM:loads 402517247 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569375203 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 81910123 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 81907161 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1349352602 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1348785802 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405618369 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated
-system.cpu.cpi 1.549091 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.549091 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 421562233 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14361.598866 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6977.217093 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 420657692 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12990655000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 904541 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 666380 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1661701000 # number of ReadReq MSHR miss cycles
+system.cpu.cpi 1.548701 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.548701 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 421715823 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14253.643501 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6923.398779 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 420813257 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 12864854000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002140 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 902566 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 664404 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1648890500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 238161 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 238162 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38025 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35025 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 1521000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 1401000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 684500 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 630500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 37779.329951 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36098.948570 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 164660283 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 82976518000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.013163 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2196347 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1851198 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 12459516000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.002069 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 345149 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 164663038 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 80123447685 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.013147 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2193592 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1850133 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 12044158308 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002058 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 343459 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1140.488307 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1140.778331 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 588418863 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30948.287394 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 585317975 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 95967173000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005270 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3100888 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2517578 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 14121217000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000991 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 583310 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 588572453 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30033.448450 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 585476295 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 92988301685 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005260 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3096158 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2514537 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13693048808 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000988 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 581621 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.574437 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 588418863 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30948.287394 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4095.574913 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 588572453 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30033.448450 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 585317975 # number of overall hits
-system.cpu.dcache.overall_miss_latency 95967173000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005270 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3100888 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2517578 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 14121217000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000991 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 583310 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 585476295 # number of overall hits
+system.cpu.dcache.overall_miss_latency 92988301685 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005260 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3096158 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2514537 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13693048808 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000988 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 581621 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 509323 # number of replacements
-system.cpu.dcache.sampled_refs 513419 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 509328 # number of replacements
+system.cpu.dcache.sampled_refs 513424 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.574437 # Cycle average of tags in use
-system.cpu.dcache.total_refs 585548366 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 166128000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 341989 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 421912263 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3394284142 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 753420072 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 764076323 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 233540433 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 2970138 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 251618660 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 350290492 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1175688320 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 10057151 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3685758924 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 87714492 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.115558 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 350290492 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 173332559 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.692710 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 2175919229 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse 4095.574913 # Cycle average of tags in use
+system.cpu.dcache.total_refs 585702974 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 165969000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 343309 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 421597556 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3393767574 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 753336946 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 764050676 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 233579864 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 2970228 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 251603669 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 350205998 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1175621134 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 10022642 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3685217760 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 87763558 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.115580 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 350205998 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 173420048 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.692887 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 2175535270 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.693936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.844478 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1350120177 62.06% 62.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 247723459 11.39% 73.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 78876862 3.63% 77.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 36715633 1.69% 78.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 82505940 3.79% 82.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 39095379 1.80% 84.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30113044 1.38% 85.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 19663449 0.90% 86.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 290721327 13.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 2175919229 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 350290492 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33351.843100 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.230992 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 350288376 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 70572500 # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 2175535270 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 350205998 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33274.163131 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34791.817524 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 350203877 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 70574500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 2116 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 735 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 48060500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 2121 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 740 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 48047500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 253832.156522 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 253770.925362 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 350290492 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33351.843100 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency
-system.cpu.icache.demand_hits 350288376 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 70572500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 350205998 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33274.163131 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
+system.cpu.icache.demand_hits 350203877 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 70574500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
-system.cpu.icache.demand_misses 2116 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 735 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 48060500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 2121 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 740 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 48047500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.517203 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1059.231284 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 350290492 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 33351.843100 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.517204 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1059.233334 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 350205998 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 33274.163131 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 350288376 # number of overall hits
-system.cpu.icache.overall_miss_latency 70572500 # number of overall miss cycles
+system.cpu.icache.overall_hits 350203877 # number of overall hits
+system.cpu.icache.overall_miss_latency 70574500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
-system.cpu.icache.overall_misses 2116 # number of overall misses
-system.cpu.icache.overall_mshr_hits 735 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 48060500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 2121 # number of overall misses
+system.cpu.icache.overall_mshr_hits 740 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 48047500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -211,212 +211,213 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 223 # number of replacements
system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1059.231284 # Cycle average of tags in use
-system.cpu.icache.total_refs 350288376 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1059.233334 # Cycle average of tags in use
+system.cpu.icache.total_refs 350203877 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1511758 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 126596313 # Number of branches executed
-system.cpu.iew.EXEC:nop 341046394 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.865157 # Inst execution rate
-system.cpu.iew.EXEC:refs 745176720 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 207345254 # Number of stores executed
+system.cpu.idleCycles 1347738 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1478969218 # num instructions consuming a value
-system.cpu.iew.WB:count 1850021692 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.963149 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1479878942 # num instructions consuming a value
+system.cpu.iew.WB:count 1850747692 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.963175 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1424467072 # num instructions producing a value
-system.cpu.iew.WB:rate 0.849635 # insts written-back per cycle
-system.cpu.iew.WB:sent 1860023576 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 88314915 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3103548 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 732453281 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21345324 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 16485503 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 296886262 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2838946953 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 537831466 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 95847914 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 1883819308 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 43195 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1425382580 # num instructions producing a value
+system.cpu.iew.WB:rate 0.850182 # insts written-back per cycle
+system.cpu.iew.WB:sent 1860799390 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 88298258 # Number of branch mispredicts detected at execute
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+system.cpu.iew.iewDispLoadInsts 732363888 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21345183 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 16501703 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 296834010 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2838380214 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 537984568 # Number of load instructions executed
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+system.cpu.iew.iewIQFullEvents 42681 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 9926 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 233540433 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 76384 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 10075 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 233579864 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 76418 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 116246750 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 24118 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 3315 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 116246268 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 24120 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 6075012 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 6177679 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 329936034 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 130028306 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 6075012 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 2827686 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 85487229 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.645540 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.645540 # IPC: Total IPC of All Threads
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+system.cpu.iew.predictedNotTakenIncorrect 2822462 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 85475796 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.645702 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.645702 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2996630 0.15% 59.69% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.69% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.69% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.69% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.69% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.69% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 570412087 28.81% 88.50% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 227687410 11.50% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178510091 59.42% 59.42% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.57% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 1979667222 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 5110932 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.002582 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 1983302601 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 6030045 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.003040 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 148685 2.91% 2.91% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.91% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.91% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 233686 4.57% 7.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.48% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 4411963 86.32% 93.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 316598 6.19% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 148667 2.47% 2.47% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 233339 3.87% 6.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 5333431 88.45% 94.78% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 314608 5.22% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 2175535270 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.911639 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.163576 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 1068255963 49.09% 49.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 579314637 26.62% 75.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 292421261 13.44% 89.16% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 161809686 7.44% 96.59% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 50369072 2.31% 98.91% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 14937591 0.69% 99.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 7897011 0.36% 99.96% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 777368 0.04% 99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 1067990413 49.09% 49.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 580044793 26.66% 75.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 292279315 13.43% 89.19% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 158370905 7.28% 96.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 51349615 2.36% 98.83% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 15864540 0.73% 99.56% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 8721161 0.40% 99.96% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 777887 0.04% 99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 136641 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 2175919229 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.909176 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2476265906 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 1979667222 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21634653 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1050976502 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1545941 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 19390982 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 1261656908 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 275258 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34298.440009 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.934352 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 9440920000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 275258 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 8578397500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 275258 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 239542 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34105.753589 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.482948 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 204503 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1195031500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.146275 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 35039 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1086296000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146275 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 35039 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 69939 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34214.100859 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.876206 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2392900000 # number of UpgradeReq miss cycles
+system.cpu.iq.ISSUE:issued_per_cycle::total 2175535270 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.911075 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2475761446 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 1983302601 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21636209 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1050320205 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 3387342 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 19392538 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1256970263 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 275262 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34309.417551 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31170.249101 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 11754 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 9040806000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.957299 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 263508 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 8213610000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.957299 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 263508 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 239543 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 204890 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1181858000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.144663 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 34653 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1074330000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144663 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 34653 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 68215 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2333844500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 69939 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2169639000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 68215 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2116155000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 69939 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 341989 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 341989 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 68215 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 343309 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 343309 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.064673 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.105608 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 514800 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34276.681695 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 204503 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10635951500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.602753 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 310297 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 514805 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34285.718119 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 216644 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 10222664000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.579173 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 298161 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9664693500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.602753 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 310297 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 9287940000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.579173 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 298161 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.056082 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.444448 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1837.702550 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14563.687199 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 514800 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34276.681695 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.057090 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.444973 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1870.709103 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14580.888860 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 514805 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34285.718119 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 204503 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10635951500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.602753 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 310297 # number of overall misses
+system.cpu.l2cache.overall_hits 216644 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 10222664000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.579173 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 298161 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9664693500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.602753 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 310297 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 9287940000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.579173 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 298161 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 84514 # number of replacements
-system.cpu.l2cache.sampled_refs 99965 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 83969 # number of replacements
+system.cpu.l2cache.sampled_refs 99434 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16401.389748 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 406325 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16451.597962 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 408237 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61949 # number of writebacks
-system.cpu.memDep0.conflictingLoads 446168372 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144446189 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 732453281 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 296886262 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 2177430987 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 18705831 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 61561 # number of writebacks
+system.cpu.memDep0.conflictingLoads 445088392 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 142143895 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 732363888 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 296834010 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 2176883008 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 18665128 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed
-system.cpu.rename.RENAME:FullRegisterEvents 818 # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents 29460 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 816810065 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 24399902 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 4857699412 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3052479029 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2393152182 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 700108886 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 233540433 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 34052536 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1148372924 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 372701478 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 21719371 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 176909620 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21553732 # count of temporary serializing insts renamed
-system.cpu.timesIdled 44523 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:FullRegisterEvents 724 # Number of times there has been no free registers
+system.cpu.rename.RENAME:IQFullEvents 28925 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 816745640 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 24395596 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 4856285750 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3051371057 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2392375919 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 700064958 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 233579864 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 34053219 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1147596661 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 372426461 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 21718962 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 176891245 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21553313 # count of temporary serializing insts renamed
+system.cpu.timesIdled 41709 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 44b6cba58..9514e3ea7 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -152,12 +152,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index be22dcc27..833f1cfc2 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:27:10
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:04:04
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -43,4 +45,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2076000877000 because target called exit()
+Exiting @ tick 2075400743000 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 89a25e955..736d779d0 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 933241 # Simulator instruction rate (inst/s)
-host_mem_usage 193388 # Number of bytes of host memory used
-host_seconds 1596.08 # Real time elapsed on the host
-host_tick_rate 1300690172 # Simulator tick rate (ticks/s)
+host_inst_rate 1385286 # Simulator instruction rate (inst/s)
+host_mem_usage 211532 # Number of bytes of host memory used
+host_seconds 1075.25 # Real time elapsed on the host
+host_tick_rate 1930162951 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
-sim_seconds 2.076001 # Number of seconds simulated
-sim_ticks 2076000877000 # Number of ticks simulated
+sim_seconds 2.075401 # Number of seconds simulated
+sim_ticks 2075400743000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
@@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 #
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.229973 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 568846579 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 513081 # number of overall misses
+system.cpu.dcache.overall_hits 568847975 # number of overall hits
+system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000899 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 511685 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000899 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 316424 # number of writebacks
+system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 316439 # number of writebacks
system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
@@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.442585 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 906.413760 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
@@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
@@ -142,36 +142,37 @@ system.cpu.idle_fraction 0 # Pe
system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 12877124000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.953422 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.448937 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 160849 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses
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+system.cpu.l2cache.demand_miss_rate 0.618599 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 281047 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11739160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.645963 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 82908 # number of replacements
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61864 # number of writebacks
+system.cpu.l2cache.writebacks 61551 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4152001754 # number of cpu cycles simulated
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system.cpu.num_insts 1489523295 # Number of instructions executed
system.cpu.num_refs 569365767 # Number of memory references
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls