stats: update stats for the changes I pushed re: shared cache occupancy

6 files changed, 29 insertions, 18 deletions

diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 8edc68d8c..8ce850818 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 4a4332de9..dd9141c9e 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  8 2009 12:09:45
-M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch
-M5 started Aug  8 2009 12:09:46
-M5 executing on tater
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:41:09
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index f1a9425ca..eeabe51c0 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1432576                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 198272                       # Number of bytes of host memory used
-host_seconds                                  1130.39                       # Real time elapsed on the host
-host_tick_rate                              851856908                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1572419                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 188984                       # Number of bytes of host memory used
+host_seconds                                  1029.86                       # Real time elapsed on the host
+host_tick_rate                              935012313                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619366736                       # Number of instructions simulated
 sim_seconds                                  0.962929                       # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 0c81e9129..c67ff9af1 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -45,6 +45,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -79,6 +80,7 @@ hash_delay=1
 latency=1000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=10000
@@ -113,6 +115,7 @@ hash_delay=1
 latency=10000
 max_miss_count=0
 mshrs=10
+num_cpus=1
 prefetch_data_accesses_only=false
 prefetch_degree=1
 prefetch_latency=100000
@@ -154,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 8936a6094..68f564509 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Nov  8 2009 16:16:58
-M5 revision 5d58e4833e79 6726 default qtip tip x86_tests.diff
-M5 started Nov  8 2009 16:32:22
-M5 executing on maize
+M5 compiled Feb 25 2010 03:41:05
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:47:37
+M5 executing on SC2B0619
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 60806dc72..59d079222 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1181561                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 194380                       # Number of bytes of host memory used
-host_seconds                                  1370.53                       # Real time elapsed on the host
-host_tick_rate                             1324103876                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 992380                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 196544                       # Number of bytes of host memory used
+host_seconds                                  1631.80                       # Real time elapsed on the host
+host_tick_rate                             1112100106                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619366736                       # Number of instructions simulated
 sim_seconds                                  1.814727                       # Number of seconds simulated
@@ -50,6 +50,8 @@ system.cpu.dcache.demand_mshr_misses           506760                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999732                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0           4094.901154                       # Average occupied blocks per context
 system.cpu.dcache.overall_accesses          607228174                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency 42325.964954                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954                       # average overall mshr miss latency
@@ -103,6 +105,8 @@ system.cpu.icache.demand_mshr_misses              722                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.322346                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            660.164909                       # Average occupied blocks per context
 system.cpu.icache.overall_accesses         1186516703                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
@@ -177,6 +181,10 @@ system.cpu.l2cache.demand_mshr_misses          277801                       # nu
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.052737                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1                  0.452189                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0          1728.087970                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1         14817.313734                       # Average occupied blocks per context
 system.cpu.l2cache.overall_accesses            442788                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency