diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/00.gzip/ref/x86/linux | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/00.gzip/ref/x86/linux')
3 files changed, 91 insertions, 102 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 1bbdb5a19..da2490100 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 5c6b0de63..d309b71a7 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:20:12 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:33:02 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:29:10 +M5 executing on phenom command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -46,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1814105620000 because target called exit() +Exiting @ tick 1803258587000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index f79a1a362..f28dbcde3 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1308474 # Simulator instruction rate (inst/s) -host_mem_usage 210192 # Number of bytes of host memory used -host_seconds 1237.60 # Real time elapsed on the host -host_tick_rate 1465826235 # Simulator tick rate (ticks/s) +host_inst_rate 1292356 # Simulator instruction rate (inst/s) +host_mem_usage 195556 # Number of bytes of host memory used +host_seconds 1253.03 # Real time elapsed on the host +host_tick_rate 1439113315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366787 # Number of instructions simulated -sim_seconds 1.814106 # Number of seconds simulated -sim_ticks 1814105620000 # Number of ticks simulated +sim_seconds 1.803259 # Number of seconds simulated +sim_ticks 1803258587000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 20826246000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses -system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses +system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606722925 # number of overall hits -system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses -system.cpu.dcache.overall_misses 505257 # number of overall misses +system.cpu.dcache.overall_hits 606786134 # number of overall hits +system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses +system.cpu.dcache.overall_misses 442048 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 306200 # number of writebacks +system.cpu.dcache.writebacks 396372 # number of writebacks system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -132,37 +132,28 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -171,44 +162,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 177813 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 264957 # number of overall misses +system.cpu.l2cache.overall_hits 353302 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 89468 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 81078 # number of replacements -system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 71208 # number of replacements +system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use -system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61253 # number of writebacks +system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3628211240 # number of cpu cycles simulated +system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.num_insts 1619366787 # Number of instructions executed system.cpu.num_refs 607228182 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |