diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/00.gzip/ref/x86 | |
parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz |
Stats: Re update stats.
Diffstat (limited to 'tests/long/00.gzip/ref/x86')
9 files changed, 103 insertions, 29 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index f7f0c46d4..503c61f1c 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f9fa6a62e..3dbb4b0b4 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 6441cfabc..05b37528b 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136188 # Simulator instruction rate (inst/s) -host_mem_usage 231788 # Number of bytes of host memory used -host_seconds 11906.26 # Real time elapsed on the host -host_tick_rate 64872637 # Simulator tick rate (ticks/s) +host_inst_rate 168346 # Simulator instruction rate (inst/s) +host_mem_usage 232444 # Number of bytes of host memory used +host_seconds 9631.89 # Real time elapsed on the host +host_tick_rate 80190939 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.772390 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.COM:loads 419042125 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed @@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency @@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 22026294 # system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads +system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued @@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ @@ -420,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 289036318 # Nu system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads system.cpu.numCycles 1544781000 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full @@ -434,10 +451,14 @@ system.cpu.rename.RENAME:RunCycles 968560202 # Nu system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3357159543 # The number of ROB reads +system.cpu.rob.rob_writes 3732197477 # The number of ROB writes system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 5a8f812f4..6c9d60230 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 2cf82dff0..1dd3bb0d2 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:38:48 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index c7162281a..ce8635d17 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1409865 # Simulator instruction rate (inst/s) -host_mem_usage 219780 # Number of bytes of host memory used -host_seconds 1150.11 # Real time elapsed on the host -host_tick_rate 838177430 # Simulator tick rate (ticks/s) +host_inst_rate 1066510 # Simulator instruction rate (inst/s) +host_mem_usage 223440 # Number of bytes of host memory used +host_seconds 1520.37 # Real time elapsed on the host +host_tick_rate 634049597 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 963992704000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1927985409 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_refs 607228182 # Number of memory references +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 56899b979..967d3d328 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index c71548d66..889c6868b 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:35 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 8adfcec1a..46400c920 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1099985 # Simulator instruction rate (inst/s) -host_mem_usage 227480 # Number of bytes of host memory used -host_seconds 1474.11 # Real time elapsed on the host -host_tick_rate 1223290364 # Simulator tick rate (ticks/s) +host_inst_rate 685934 # Simulator instruction rate (inst/s) +host_mem_usage 231240 # Number of bytes of host memory used +host_seconds 2363.92 # Real time elapsed on the host +host_tick_rate 762824620 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_refs 607228182 # Number of memory references +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- |