X86: Update stats for in place TLB miss handling.

4 files changed, 38 insertions, 38 deletions

diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 5eb2ed956..1d076eebd 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:19:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 01:00:03
-M5 executing on zizzer
+M5 compiled Feb 23 2009 23:45:19
+M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
+M5 started Feb 23 2009 23:48:10
+M5 executing on tater
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -44,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 962935342000 because target called exit()
+Exiting @ tick 962928676500 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index cf444d872..fd612c556 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,18 +1,18 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1622364                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197488                       # Number of bytes of host memory used
-host_seconds                                   998.15                       # Real time elapsed on the host
-host_tick_rate                              964717823                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 977325                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 197144                       # Number of bytes of host memory used
+host_seconds                                  1656.94                       # Real time elapsed on the host
+host_tick_rate                              581149945                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619365942                       # Number of instructions simulated
-sim_seconds                                  0.962935                       # Number of seconds simulated
-sim_ticks                                962935342000                       # Number of ticks simulated
+sim_seconds                                  0.962929                       # Number of seconds simulated
+sim_ticks                                962928676500                       # Number of ticks simulated
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       1925870685                       # number of cpu cycles simulated
+system.cpu.numCycles                       1925857354                       # number of cpu cycles simulated
 system.cpu.num_insts                       1619365942                       # Number of instructions executed
-system.cpu.num_refs                         607160031                       # Number of memory references
+system.cpu.num_refs                         607148814                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 547d12c0b..f6eeaa6d1 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb 16 2009 00:19:15
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 01:02:02
-M5 executing on zizzer
+M5 compiled Feb 23 2009 23:45:19
+M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch
+M5 started Feb 23 2009 23:48:10
+M5 executing on tater
 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -44,4 +44,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2554098117000 because target called exit()
+Exiting @ tick 2554084828000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 3681e4f0c..f6f018cc6 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1065301                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204932                       # Number of bytes of host memory used
-host_seconds                                  1520.10                       # Real time elapsed on the host
-host_tick_rate                             1680214432                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 751612                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204588                       # Number of bytes of host memory used
+host_seconds                                  2154.53                       # Real time elapsed on the host
+host_tick_rate                             1185451424                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                  1619365942                       # Number of instructions simulated
-sim_seconds                                  2.554098                       # Number of seconds simulated
-sim_ticks                                2554098117000                       # Number of ticks simulated
+sim_seconds                                  2.554085                       # Number of seconds simulated
+sim_ticks                                2554084828000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses          418962758                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697                       # average ReadReq mshr miss latency
@@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses            0
 system.cpu.dcache.replacements                 439707                       # number of replacements
 system.cpu.dcache.sampled_refs                 443803                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4094.609383                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.610676                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                606705011                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1593417000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle             1592465000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                   308507                       # number of writebacks
-system.cpu.icache.ReadReq_accesses         1925870644                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses         1925857355                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             1925869923                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits             1925856634                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       40376000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  721                       # number of ReadReq misses
@@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # ms
 system.cpu.icache.ReadReq_mshr_misses             721                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               2671109.463245                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               2671091.031900                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          1925870644                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses          1925857355                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              1925869923                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits              1925856634                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        40376000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   721                       # number of demand (read+write) misses
@@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses              721                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses         1925870644                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses         1925857355                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             1925869923                       # number of overall hits
+system.cpu.icache.overall_hits             1925856634                       # number of overall hits
 system.cpu.icache.overall_miss_latency       40376000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  721                       # number of overall misses
@@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses            0
 system.cpu.icache.replacements                      4                       # number of replacements
 system.cpu.icache.sampled_refs                    721                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                658.724449                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1925869923                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                658.724808                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1925856634                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
@@ -194,14 +194,14 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses            0
 system.cpu.l2cache.replacements                 82097                       # number of replacements
 system.cpu.l2cache.sampled_refs                 97587                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             16428.000401                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             16428.009263                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  332264                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                   61702                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       5108196234                       # number of cpu cycles simulated
+system.cpu.numCycles                       5108169656                       # number of cpu cycles simulated
 system.cpu.num_insts                       1619365942                       # Number of instructions executed
-system.cpu.num_refs                         607160031                       # Number of memory references
+system.cpu.num_refs                         607148814                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              48                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------