diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/long/00.gzip/ref/x86 | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/long/00.gzip/ref/x86')
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini | 3 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 724 |
3 files changed, 369 insertions, 366 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 503c61f1c..2af9a6819 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index e2d377ea1..f0ec00748 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 16 2011 15:39:14 -M5 started Mar 16 2011 15:39:15 -M5 executing on burrito +M5 compiled Mar 18 2011 20:12:06 +M5 started Mar 18 2011 20:12:27 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1066,4 +1066,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 766217705000 because target called exit() +Exiting @ tick 751079230500 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 7b745cca5..3726448fa 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 213906 # Simulator instruction rate (inst/s) -host_mem_usage 226116 # Number of bytes of host memory used -host_seconds 7580.41 # Real time elapsed on the host -host_tick_rate 101078599 # Simulator tick rate (ticks/s) +host_inst_rate 151077 # Simulator instruction rate (inst/s) +host_mem_usage 216016 # Number of bytes of host memory used +host_seconds 10732.89 # Real time elapsed on the host +host_tick_rate 69979188 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.766218 # Number of seconds simulated -sim_ticks 766217705000 # Number of ticks simulated +sim_seconds 0.751079 # Number of seconds simulated +sim_ticks 751079230500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 168460210 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 169652659 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 8971423 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 11445860 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1402522347 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.156127 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1402522347 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses +system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926404 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 325401931 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10107.251018 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7152.951878 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 325183672 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2205998500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 218259 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3345 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1537269500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 214914 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 19574.534314 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10012.304968 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 186952974 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 24137025496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006552 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1233083 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 982981 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2504097497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 250102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15974.978853 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1101.331236 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 472140500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency -system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 513587988 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18150.803874 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency +system.cpu.dcache.demand_hits 512136646 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26343023996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002826 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1451342 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 986326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4041366997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 465016 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999792 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 517710070 # number of overall hits -system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1455125 # number of overall misses -system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses +system.cpu.dcache.overall_hits 512136646 # number of overall hits +system.cpu.dcache.overall_miss_latency 26343023996 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002826 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1451342 # number of overall misses +system.cpu.dcache.overall_mshr_hits 986326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4041366997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 465016 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 460779 # number of replacements -system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 460920 # number of replacements +system.cpu.dcache.sampled_refs 465016 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use -system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 411288 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched -system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.146726 # Cycle average of tags in use +system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 411408 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 587921420 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2472731706 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 429893143 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 331529130 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 99378480 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 53178654 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched +system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 625222 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1408639601 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 15384200 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.119823 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 170058043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 168460210 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.937744 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1501900827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.699260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.059388 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1104715792 73.55% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26107791 1.74% 75.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14369087 0.96% 76.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13756932 0.92% 77.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30207594 2.01% 79.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20132707 1.34% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34410865 2.29% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37556252 2.50% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220643807 14.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1501900827 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 170058043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35240.756303 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.058688 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 170056853 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 41936500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 321 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 30694000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 869 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 195692.581128 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency -system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 170058043 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35240.756303 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency +system.cpu.icache.demand_hits 170056853 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 41936500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 30694000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 869 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context -system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.387535 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context +system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 168862206 # number of overall hits -system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles +system.cpu.icache.overall_hits 170056853 # number of overall hits +system.cpu.icache.overall_miss_latency 41936500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1223 # number of overall misses -system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1190 # number of overall misses +system.cpu.icache.overall_mshr_hits 321 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 30694000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 869 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 11 # number of replacements -system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 869 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use -system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 793.670730 # Cycle average of tags in use +system.cpu.icache.total_refs 170056853 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 111314295 # Number of branches executed +system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 111429178 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate -system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 191312994 # Number of stores executed +system.cpu.iew.EXEC:rate 1.227514 # Inst execution rate +system.cpu.iew.EXEC:refs 636597814 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 191695864 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2089450314 # num instructions consuming a value -system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back +system.cpu.iew.WB:consumers 2082700302 # num instructions consuming a value +system.cpu.iew.WB:count 1838995466 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.683970 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1430463260 # num instructions producing a value -system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle -system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1424504384 # num instructions producing a value +system.cpu.iew.WB:rate 1.224235 # insts written-back per cycle +system.cpu.iew.WB:sent 1842743630 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 312936 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 250798855 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2343198083 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 444901950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13067063 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1843921293 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 56293 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 119484333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads -system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes -system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6399400 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 47 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 196809249 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 62612798 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads +system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes +system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1856988356 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4273878 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1501900827 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.236425 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate -system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads +system.cpu.iq.ISSUE:issued_per_cycle::total 1501900827 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.236213 # Inst issue rate +system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2351086127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1543114167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3071160852 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2343198002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1856988356 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 721564206 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 191287 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2024064500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235198 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58826 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235198 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 215772 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34136.783762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.222249 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 182665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1130166500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.153435 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33107 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026523000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153435 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33107 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 411408 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 411408 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 5.099879 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 465885 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34310.106273 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 373952 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3154231000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.197330 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91933 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2859290000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.197330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91933 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.058491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491164 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 373812 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91930 # number of overall misses +system.cpu.l2cache.overall_hits 373952 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3154231000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.197330 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91933 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2859290000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.197330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91933 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 73661 # number of replacements -system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 73660 # number of replacements +system.cpu.l2cache.sampled_refs 89268 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use -system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18011.074755 # Cycle average of tags in use +system.cpu.l2cache.total_refs 455256 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58542 # number of writebacks -system.cpu.memDep0.conflictingLoads 537232403 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads -system.cpu.numCycles 1532435411 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58532 # number of writebacks +system.cpu.memDep0.conflictingLoads 528261825 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 206728085 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 615851374 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250798855 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 931071836 # number of misc regfile reads +system.cpu.numCycles 1502158462 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 169288978 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3775835718 # The number of ROB reads -system.cpu.rob.rob_writes 4802062478 # The number of ROB writes -system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 298516669 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 493321936 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5808956116 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2397077126 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2395694665 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 310095488 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 99378480 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 429812969 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 777700015 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 64 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5808956052 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 2976 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 89 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 706930007 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 89 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3734283918 # The number of ROB reads +system.cpu.rob.rob_writes 4785794667 # The number of ROB writes +system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- |