summaryrefslogtreecommitdiff
path: root/tests/long/00.gzip/ref
diff options
context:
space:
mode:
authorKorey Sewell <ksewell@umich.edu>2006-10-12 15:04:14 -0400
committerKorey Sewell <ksewell@umich.edu>2006-10-12 15:04:14 -0400
commit790e746bd961510b93f9276296cb86fc70768cd3 (patch)
tree160e67c96ba6ab2063b0f577de834c9446ffdb8d /tests/long/00.gzip/ref
parent1ebe4b0dec40fd3d58aa55c38a0fcbf212ebda85 (diff)
downloadgem5-790e746bd961510b93f9276296cb86fc70768cd3.tar.xz
config file updates
--HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
Diffstat (limited to 'tests/long/00.gzip/ref')
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini417
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out403
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt1974
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr3
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout13
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini417
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out403
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt1974
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr3
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout13
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini417
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out403
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt1974
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr3
-rw-r--r--tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout13
15 files changed, 8430 insertions, 0 deletions
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini
new file mode 100644
index 000000000..c3a59fbce
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini
@@ -0,0 +1,417 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.dcache
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+env=
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+system=system
+
+[system.membus]
+type=Bus
+bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out
new file mode 100644
index 000000000..f491a3081
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out
@@ -0,0 +1,403 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+env=
+system=system
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.cpu.workload
+mem=system.cpu.dcache
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt
new file mode 100644
index 000000000..5d4f9235a
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt
@@ -0,0 +1,1974 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 542 # Number of BTB hits
+global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
+global.BPredUnit.lookups 2256 # Number of BP lookups
+global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
+host_inst_rate 41797 # Simulator instruction rate (inst/s)
+host_mem_usage 160344 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 50948 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5623 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 6870 # Number of ticks simulated
+system.cpu.commit.COM:branches 862 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 3908 6389.80%
+ 1 1064 1739.70%
+ 2 389 636.04%
+ 3 210 343.36%
+ 4 153 250.16%
+ 5 93 152.06%
+ 6 76 124.26%
+ 7 149 243.62%
+ 8 74 120.99%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 5640 # Number of instructions committed
+system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5623 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
+system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2048 # number of overall hits
+system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 311 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.min_value 0
+ 0 4549 6620.58%
+ 1 174 253.24%
+ 2 186 270.70%
+ 3 157 228.50%
+ 4 211 307.09%
+ 5 153 222.68%
+ 6 171 248.87%
+ 7 105 152.82%
+ 8 1165 1695.53%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
+system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1255 # number of overall hits
+system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
+system.cpu.icache.overall_misses 327 # number of overall misses
+system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
+system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.iew.EXEC:branches 1206 # Number of branches executed
+system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
+system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 37 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
+system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
+system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 4049 # num instructions producing a value
+system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
+system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:(null).samples 0
+system.cpu.iq.IQ:residence:(null).min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:(null).max_value 0
+system.cpu.iq.IQ:residence:(null).end_dist
+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntAlu.samples 0
+system.cpu.iq.IQ:residence:IntAlu.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntAlu.max_value 0
+system.cpu.iq.IQ:residence:IntAlu.end_dist
+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntMult.samples 0
+system.cpu.iq.IQ:residence:IntMult.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntMult.max_value 0
+system.cpu.iq.IQ:residence:IntMult.end_dist
+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntDiv.samples 0
+system.cpu.iq.IQ:residence:IntDiv.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntDiv.max_value 0
+system.cpu.iq.IQ:residence:IntDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatAdd.samples 0
+system.cpu.iq.IQ:residence:FloatAdd.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatAdd.max_value 0
+system.cpu.iq.IQ:residence:FloatAdd.end_dist
+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCmp.samples 0
+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatCmp.max_value 0
+system.cpu.iq.IQ:residence:FloatCmp.end_dist
+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCvt.samples 0
+system.cpu.iq.IQ:residence:FloatCvt.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatCvt.max_value 0
+system.cpu.iq.IQ:residence:FloatCvt.end_dist
+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatMult.samples 0
+system.cpu.iq.IQ:residence:FloatMult.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatMult.max_value 0
+system.cpu.iq.IQ:residence:FloatMult.end_dist
+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatDiv.samples 0
+system.cpu.iq.IQ:residence:FloatDiv.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatDiv.max_value 0
+system.cpu.iq.IQ:residence:FloatDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatSqrt.samples 0
+system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemRead.samples 0
+system.cpu.iq.IQ:residence:MemRead.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:MemRead.max_value 0
+system.cpu.iq.IQ:residence:MemRead.end_dist
+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemWrite.samples 0
+system.cpu.iq.IQ:residence:MemWrite.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:MemWrite.max_value 0
+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IprAccess.samples 0
+system.cpu.iq.IQ:residence:IprAccess.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IprAccess.max_value 0
+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:InstPrefetch.samples 0
+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
+system.cpu.iq.IQ:residence:InstPrefetch.end_dist
+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:(null)_delay.samples 0
+system.cpu.iq.ISSUE:(null)_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:(null)_delay.max_value 0
+system.cpu.iq.ISSUE:(null)_delay.end_dist
+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
+system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
+system.cpu.iq.ISSUE:IntMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
+system.cpu.iq.ISSUE:IntMult_delay.end_dist
+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
+system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
+system.cpu.iq.ISSUE:IntDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
+system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
+system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
+system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 2 0.02% # Type of FU issued
+ IntAlu 5594 66.69% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 1757 20.95% # Type of FU issued
+ MemWrite 1032 12.30% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 1 0.87% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 76 66.09% # attempts to use FU when none available
+ MemWrite 38 33.04% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 3753 5462.09%
+ 1 894 1301.12%
+ 2 723 1052.25%
+ 3 614 893.61%
+ 4 451 656.38%
+ 5 279 406.05%
+ 6 104 151.36%
+ 7 41 59.67%
+ 8 12 17.46%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 6871 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr
new file mode 100644
index 000000000..8893caac8
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr
@@ -0,0 +1,3 @@
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout
new file mode 100644
index 000000000..fbb329a2f
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout
@@ -0,0 +1,13 @@
+Hello world!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:12 2006
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
+Exiting @ tick 6870 because target called exit()
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..c3a59fbce
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini
@@ -0,0 +1,417 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.dcache
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+env=
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+system=system
+
+[system.membus]
+type=Bus
+bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out
new file mode 100644
index 000000000..f491a3081
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out
@@ -0,0 +1,403 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+env=
+system=system
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.cpu.workload
+mem=system.cpu.dcache
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt
new file mode 100644
index 000000000..5d4f9235a
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -0,0 +1,1974 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 542 # Number of BTB hits
+global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
+global.BPredUnit.lookups 2256 # Number of BP lookups
+global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
+host_inst_rate 41797 # Simulator instruction rate (inst/s)
+host_mem_usage 160344 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 50948 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5623 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 6870 # Number of ticks simulated
+system.cpu.commit.COM:branches 862 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 3908 6389.80%
+ 1 1064 1739.70%
+ 2 389 636.04%
+ 3 210 343.36%
+ 4 153 250.16%
+ 5 93 152.06%
+ 6 76 124.26%
+ 7 149 243.62%
+ 8 74 120.99%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 5640 # Number of instructions committed
+system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5623 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
+system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2048 # number of overall hits
+system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 311 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.min_value 0
+ 0 4549 6620.58%
+ 1 174 253.24%
+ 2 186 270.70%
+ 3 157 228.50%
+ 4 211 307.09%
+ 5 153 222.68%
+ 6 171 248.87%
+ 7 105 152.82%
+ 8 1165 1695.53%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
+system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1255 # number of overall hits
+system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
+system.cpu.icache.overall_misses 327 # number of overall misses
+system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
+system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.iew.EXEC:branches 1206 # Number of branches executed
+system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
+system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 37 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
+system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
+system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 4049 # num instructions producing a value
+system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
+system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:(null).samples 0
+system.cpu.iq.IQ:residence:(null).min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:(null).max_value 0
+system.cpu.iq.IQ:residence:(null).end_dist
+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntAlu.samples 0
+system.cpu.iq.IQ:residence:IntAlu.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntAlu.max_value 0
+system.cpu.iq.IQ:residence:IntAlu.end_dist
+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntMult.samples 0
+system.cpu.iq.IQ:residence:IntMult.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntMult.max_value 0
+system.cpu.iq.IQ:residence:IntMult.end_dist
+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntDiv.samples 0
+system.cpu.iq.IQ:residence:IntDiv.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntDiv.max_value 0
+system.cpu.iq.IQ:residence:IntDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatAdd.samples 0
+system.cpu.iq.IQ:residence:FloatAdd.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatAdd.max_value 0
+system.cpu.iq.IQ:residence:FloatAdd.end_dist
+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCmp.samples 0
+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatCmp.max_value 0
+system.cpu.iq.IQ:residence:FloatCmp.end_dist
+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCvt.samples 0
+system.cpu.iq.IQ:residence:FloatCvt.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatCvt.max_value 0
+system.cpu.iq.IQ:residence:FloatCvt.end_dist
+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatMult.samples 0
+system.cpu.iq.IQ:residence:FloatMult.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatMult.max_value 0
+system.cpu.iq.IQ:residence:FloatMult.end_dist
+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatDiv.samples 0
+system.cpu.iq.IQ:residence:FloatDiv.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatDiv.max_value 0
+system.cpu.iq.IQ:residence:FloatDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatSqrt.samples 0
+system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemRead.samples 0
+system.cpu.iq.IQ:residence:MemRead.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:MemRead.max_value 0
+system.cpu.iq.IQ:residence:MemRead.end_dist
+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemWrite.samples 0
+system.cpu.iq.IQ:residence:MemWrite.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:MemWrite.max_value 0
+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IprAccess.samples 0
+system.cpu.iq.IQ:residence:IprAccess.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IprAccess.max_value 0
+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:InstPrefetch.samples 0
+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
+system.cpu.iq.IQ:residence:InstPrefetch.end_dist
+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:(null)_delay.samples 0
+system.cpu.iq.ISSUE:(null)_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:(null)_delay.max_value 0
+system.cpu.iq.ISSUE:(null)_delay.end_dist
+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
+system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
+system.cpu.iq.ISSUE:IntMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
+system.cpu.iq.ISSUE:IntMult_delay.end_dist
+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
+system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
+system.cpu.iq.ISSUE:IntDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
+system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
+system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
+system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 2 0.02% # Type of FU issued
+ IntAlu 5594 66.69% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 1757 20.95% # Type of FU issued
+ MemWrite 1032 12.30% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 1 0.87% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 76 66.09% # attempts to use FU when none available
+ MemWrite 38 33.04% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 3753 5462.09%
+ 1 894 1301.12%
+ 2 723 1052.25%
+ 3 614 893.61%
+ 4 451 656.38%
+ 5 279 406.05%
+ 6 104 151.36%
+ 7 41 59.67%
+ 8 12 17.46%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 6871 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr
new file mode 100644
index 000000000..8893caac8
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr
@@ -0,0 +1,3 @@
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout
new file mode 100644
index 000000000..fbb329a2f
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout
@@ -0,0 +1,13 @@
+Hello world!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:12 2006
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
+Exiting @ tick 6870 because target called exit()
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini
new file mode 100644
index 000000000..c3a59fbce
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini
@@ -0,0 +1,417 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.dcache
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+env=
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+system=system
+
+[system.membus]
+type=Bus
+bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out
new file mode 100644
index 000000000..f491a3081
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out
@@ -0,0 +1,403 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+env=
+system=system
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.cpu.workload
+mem=system.cpu.dcache
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt
new file mode 100644
index 000000000..5d4f9235a
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt
@@ -0,0 +1,1974 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 542 # Number of BTB hits
+global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
+global.BPredUnit.lookups 2256 # Number of BP lookups
+global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
+host_inst_rate 41797 # Simulator instruction rate (inst/s)
+host_mem_usage 160344 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 50948 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5623 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 6870 # Number of ticks simulated
+system.cpu.commit.COM:branches 862 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 3908 6389.80%
+ 1 1064 1739.70%
+ 2 389 636.04%
+ 3 210 343.36%
+ 4 153 250.16%
+ 5 93 152.06%
+ 6 76 124.26%
+ 7 149 243.62%
+ 8 74 120.99%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 5640 # Number of instructions committed
+system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5623 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
+system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2048 # number of overall hits
+system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 311 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.min_value 0
+ 0 4549 6620.58%
+ 1 174 253.24%
+ 2 186 270.70%
+ 3 157 228.50%
+ 4 211 307.09%
+ 5 153 222.68%
+ 6 171 248.87%
+ 7 105 152.82%
+ 8 1165 1695.53%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
+system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1255 # number of overall hits
+system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
+system.cpu.icache.overall_misses 327 # number of overall misses
+system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
+system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.iew.EXEC:branches 1206 # Number of branches executed
+system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
+system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 37 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
+system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
+system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 4049 # num instructions producing a value
+system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
+system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:(null).samples 0
+system.cpu.iq.IQ:residence:(null).min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:(null).max_value 0
+system.cpu.iq.IQ:residence:(null).end_dist
+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntAlu.samples 0
+system.cpu.iq.IQ:residence:IntAlu.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntAlu.max_value 0
+system.cpu.iq.IQ:residence:IntAlu.end_dist
+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntMult.samples 0
+system.cpu.iq.IQ:residence:IntMult.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntMult.max_value 0
+system.cpu.iq.IQ:residence:IntMult.end_dist
+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntDiv.samples 0
+system.cpu.iq.IQ:residence:IntDiv.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IntDiv.max_value 0
+system.cpu.iq.IQ:residence:IntDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatAdd.samples 0
+system.cpu.iq.IQ:residence:FloatAdd.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatAdd.max_value 0
+system.cpu.iq.IQ:residence:FloatAdd.end_dist
+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCmp.samples 0
+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatCmp.max_value 0
+system.cpu.iq.IQ:residence:FloatCmp.end_dist
+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatCvt.samples 0
+system.cpu.iq.IQ:residence:FloatCvt.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatCvt.max_value 0
+system.cpu.iq.IQ:residence:FloatCvt.end_dist
+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatMult.samples 0
+system.cpu.iq.IQ:residence:FloatMult.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatMult.max_value 0
+system.cpu.iq.IQ:residence:FloatMult.end_dist
+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatDiv.samples 0
+system.cpu.iq.IQ:residence:FloatDiv.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatDiv.max_value 0
+system.cpu.iq.IQ:residence:FloatDiv.end_dist
+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:FloatSqrt.samples 0
+system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemRead.samples 0
+system.cpu.iq.IQ:residence:MemRead.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:MemRead.max_value 0
+system.cpu.iq.IQ:residence:MemRead.end_dist
+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:MemWrite.samples 0
+system.cpu.iq.IQ:residence:MemWrite.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:MemWrite.max_value 0
+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IprAccess.samples 0
+system.cpu.iq.IQ:residence:IprAccess.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:IprAccess.max_value 0
+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:InstPrefetch.samples 0
+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
+system.cpu.iq.IQ:residence:InstPrefetch.end_dist
+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:(null)_delay.samples 0
+system.cpu.iq.ISSUE:(null)_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:(null)_delay.max_value 0
+system.cpu.iq.ISSUE:(null)_delay.end_dist
+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
+system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
+system.cpu.iq.ISSUE:IntMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
+system.cpu.iq.ISSUE:IntMult_delay.end_dist
+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
+system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
+system.cpu.iq.ISSUE:IntDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
+system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
+system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
+system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
+ 26 0
+ 28 0
+ 30 0
+ 32 0
+ 34 0
+ 36 0
+ 38 0
+ 40 0
+ 42 0
+ 44 0
+ 46 0
+ 48 0
+ 50 0
+ 52 0
+ 54 0
+ 56 0
+ 58 0
+ 60 0
+ 62 0
+ 64 0
+ 66 0
+ 68 0
+ 70 0
+ 72 0
+ 74 0
+ 76 0
+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 2 0.02% # Type of FU issued
+ IntAlu 5594 66.69% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 1757 20.95% # Type of FU issued
+ MemWrite 1032 12.30% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 1 0.87% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 76 66.09% # attempts to use FU when none available
+ MemWrite 38 33.04% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 3753 5462.09%
+ 1 894 1301.12%
+ 2 723 1052.25%
+ 3 614 893.61%
+ 4 451 656.38%
+ 5 279 406.05%
+ 6 104 151.36%
+ 7 41 59.67%
+ 8 12 17.46%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 6871 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr
new file mode 100644
index 000000000..8893caac8
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr
@@ -0,0 +1,3 @@
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout
new file mode 100644
index 000000000..fbb329a2f
--- /dev/null
+++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout
@@ -0,0 +1,13 @@
+Hello world!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:12 2006
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
+Exiting @ tick 6870 because target called exit()