diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
| commit | 999cd8aef5dfa3c22b02b55420608fbb8d7e7822 (patch) | |
| tree | 98f11453678ed2be66b2ae3239b0ee42ad6f4e05 /tests/long/00.gzip/ref | |
| parent | b94f84196924d60d4d4677929ddb6f677e3d96d9 (diff) | |
| download | gem5-999cd8aef5dfa3c22b02b55420608fbb8d7e7822.tar.xz | |
StoreSet: Update stats for store-set clearing
Diffstat (limited to 'tests/long/00.gzip/ref')
12 files changed, 1542 insertions, 1519 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 55c96d241..cdf647d08 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 5c5a7a6e9..81484db61 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 17:43:54 -gem5 started Jul 15 2011 18:05:21 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 14:47:20 +gem5 started Aug 17 2011 14:50:17 +gem5 executing on nadc-0388 command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -39,4 +41,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145175788500 because target called exit() +Exiting @ tick 145301847500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 4f3a6d8f3..5c2b0fbb8 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145176 # Number of seconds simulated -sim_ticks 145175788500 # Number of ticks simulated +sim_seconds 0.145302 # Number of seconds simulated +sim_ticks 145301847500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116167 # Simulator instruction rate (inst/s) -host_tick_rate 29819633 # Simulator tick rate (ticks/s) -host_mem_usage 246468 # Number of bytes of host memory used -host_seconds 4868.46 # Real time elapsed on the host +host_inst_rate 168398 # Simulator instruction rate (inst/s) +host_tick_rate 43264868 # Simulator tick rate (ticks/s) +host_mem_usage 252140 # Number of bytes of host memory used +host_seconds 3358.43 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125726238 # DTB read hits -system.cpu.dtb.read_misses 26702 # DTB read misses +system.cpu.dtb.read_hits 125931819 # DTB read hits +system.cpu.dtb.read_misses 26714 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125752940 # DTB read accesses -system.cpu.dtb.write_hits 41507366 # DTB write hits -system.cpu.dtb.write_misses 32028 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 41539394 # DTB write accesses -system.cpu.dtb.data_hits 167233604 # DTB hits -system.cpu.dtb.data_misses 58730 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 167292334 # DTB accesses -system.cpu.itb.fetch_hits 71588816 # ITB hits +system.cpu.dtb.read_accesses 125958533 # DTB read accesses +system.cpu.dtb.write_hits 41424543 # DTB write hits +system.cpu.dtb.write_misses 32276 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 41456819 # DTB write accesses +system.cpu.dtb.data_hits 167356362 # DTB hits +system.cpu.dtb.data_misses 58990 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 167415352 # DTB accesses +system.cpu.itb.fetch_hits 71387266 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71588856 # ITB accesses +system.cpu.itb.fetch_accesses 71387306 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290351578 # number of cpu cycles simulated +system.cpu.numCycles 290603696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 82068439 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75472139 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4139210 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 77758293 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69764860 # Number of BTB hits +system.cpu.BPredUnit.lookups 81919814 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75390266 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4129357 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77614173 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69618230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1965418 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74381248 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 740847057 # Number of instructions fetch has processed -system.cpu.fetch.Branches 82068439 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71730278 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139388095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17359106 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 63481916 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1955958 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74192269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 739424750 # Number of instructions fetch has processed +system.cpu.fetch.Branches 81919814 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71574188 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139080989 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17172234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 64410456 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71588816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1228525 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290282404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.552160 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199400 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 71387266 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1210642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290534603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.545049 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.198246 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 150894309 51.98% 51.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11757724 4.05% 56.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15902063 5.48% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15874475 5.47% 66.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13293221 4.58% 71.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15622251 5.38% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6768599 2.33% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3592047 1.24% 80.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56577715 19.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151453614 52.13% 52.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11687885 4.02% 56.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15898742 5.47% 61.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15854935 5.46% 67.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13240035 4.56% 71.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15603650 5.37% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6697784 2.31% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3574182 1.23% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56523776 19.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290282404 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.282652 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.551552 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90540829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 49762589 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 127167334 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9782311 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13029341 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4494723 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 873 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 729210837 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3260 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 13029341 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 98854754 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12652695 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 558 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123369042 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42376014 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 715226972 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32893526 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4012041 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 545137745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 939207717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 939205613 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2104 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290534603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281895 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.544444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90310656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 50731551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 126219695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10423604 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12849097 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4446391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 727740839 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3152 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12849097 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98621596 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12675857 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123066068 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43321346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 713725381 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 266 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 34127954 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3740820 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 543893835 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 937350842 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 937348775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2067 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 81282856 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 82693608 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131825687 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43890067 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17591169 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7047053 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 644543109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621562613 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 380292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77712656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42125820 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290282404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.141234 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.879500 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 80038946 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 85210895 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131427932 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43788464 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14719547 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6869694 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 643138163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 621184561 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 428348 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 76303449 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41228761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 290534603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.138074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876724 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 70571105 24.31% 24.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 58751148 20.24% 44.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 55824387 19.23% 63.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31456534 10.84% 74.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33062190 11.39% 86.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 24005083 8.27% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12272709 4.23% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3831324 1.32% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 507924 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 70371393 24.22% 24.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 59001774 20.31% 44.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 56407615 19.42% 63.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31734464 10.92% 74.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32252552 11.10% 85.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24569230 8.46% 94.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11680867 4.02% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3911059 1.35% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 605649 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290282404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290534603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4555010 86.10% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 57 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 523123 9.89% 95.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 212105 4.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4149748 79.41% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 46 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 644138 12.33% 91.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 431804 8.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451240060 72.60% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7852 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 128169032 20.62% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42145620 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 450716451 72.56% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7786 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 128329931 20.66% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42130345 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 621562613 # Type of FU issued -system.cpu.iq.rate 2.140724 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5290295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008511 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1539074805 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 722600568 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 609952454 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3412 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1900 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1604 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 626851187 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1721 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11465807 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 621184561 # Type of FU issued +system.cpu.iq.rate 2.137566 # Inst issue rate +system.cpu.iq.fu_busy_cnt 5225736 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008413 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1538554428 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 719791910 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 609163875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3381 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1606 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 626408589 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1708 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11777609 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17311645 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67694 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 365195 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4438746 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 16913890 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 148570 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 370604 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4337143 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5929 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50756 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5917 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50743 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13029341 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1515549 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101263 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 690142973 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2399318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 131825687 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43890067 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41006 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13792 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 365195 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4054325 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 604453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4658778 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 614025387 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125753017 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7537226 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12849097 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1534890 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101054 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 688747962 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2386448 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 131427932 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43788464 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 40995 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13802 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 370604 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4041048 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 603771 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4644819 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613556554 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125958678 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7628007 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45599835 # number of nop insts executed -system.cpu.iew.exec_refs 167311882 # number of memory reference insts executed -system.cpu.iew.exec_branches 68605174 # Number of branches executed -system.cpu.iew.exec_stores 41558865 # Number of stores executed -system.cpu.iew.exec_rate 2.114765 # Inst execution rate -system.cpu.iew.wb_sent 611451889 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 609954058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 420339317 # num instructions producing a value -system.cpu.iew.wb_consumers 532241742 # num instructions consuming a value +system.cpu.iew.exec_nop 45609769 # number of nop insts executed +system.cpu.iew.exec_refs 167435052 # number of memory reference insts executed +system.cpu.iew.exec_branches 68567792 # Number of branches executed +system.cpu.iew.exec_stores 41476374 # Number of stores executed +system.cpu.iew.exec_rate 2.111317 # Inst execution rate +system.cpu.iew.wb_sent 610651273 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 609165481 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420066604 # num instructions producing a value +system.cpu.iew.wb_consumers 531633628 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.100743 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789753 # average fanout of values written-back +system.cpu.iew.wb_rate 2.096207 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 88132303 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 86736991 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4138394 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 277253063 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.170786 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.607112 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4128553 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 277685506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.167405 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.598933 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91432186 32.98% 32.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75471271 27.22% 60.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31359713 11.31% 71.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9812345 3.54% 75.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10073105 3.63% 78.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21591836 7.79% 86.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5927353 2.14% 88.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2268519 0.82% 89.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29316735 10.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91049633 32.79% 32.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 76164348 27.43% 60.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31609265 11.38% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9610599 3.46% 75.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10212120 3.68% 78.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21618987 7.79% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6091791 2.19% 88.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2481977 0.89% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 28846786 10.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 277253063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 277685506 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29316735 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 28846786 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 937861205 # The number of ROB reads -system.cpu.rob.rob_writes 1393014626 # The number of ROB writes -system.cpu.timesIdled 2237 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 69174 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 937368285 # The number of ROB reads +system.cpu.rob.rob_writes 1390043178 # The number of ROB writes +system.cpu.timesIdled 2213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69093 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.513395 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.513395 # CPI: Total CPI of All Threads -system.cpu.ipc 1.947819 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.947819 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 864633877 # number of integer regfile reads -system.cpu.int_regfile_writes 501928899 # number of integer regfile writes -system.cpu.fp_regfile_reads 273 # number of floating regfile reads -system.cpu.fp_regfile_writes 57 # number of floating regfile writes +system.cpu.cpi 0.513840 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.513840 # CPI: Total CPI of All Threads +system.cpu.ipc 1.946130 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.946130 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 864034550 # number of integer regfile reads +system.cpu.int_regfile_writes 501250515 # number of integer regfile writes +system.cpu.fp_regfile_reads 281 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 799.817467 # Cycle average of tags in use -system.cpu.icache.total_refs 71587538 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 76076.023379 # Average number of references to valid blocks. +system.cpu.icache.replacements 34 # number of replacements +system.cpu.icache.tagsinuse 800.952347 # Cycle average of tags in use +system.cpu.icache.total_refs 71385990 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 75700.943796 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 799.817467 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.390536 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 71587538 # number of ReadReq hits -system.cpu.icache.demand_hits 71587538 # number of demand (read+write) hits -system.cpu.icache.overall_hits 71587538 # number of overall hits -system.cpu.icache.ReadReq_misses 1278 # number of ReadReq misses -system.cpu.icache.demand_misses 1278 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1278 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 45985500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 45985500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 45985500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 71588816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 71588816 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 71588816 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 800.952347 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.391090 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 71385990 # number of ReadReq hits +system.cpu.icache.demand_hits 71385990 # number of demand (read+write) hits +system.cpu.icache.overall_hits 71385990 # number of overall hits +system.cpu.icache.ReadReq_misses 1276 # number of ReadReq misses +system.cpu.icache.demand_misses 1276 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1276 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46038500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46038500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46038500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 71387266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 71387266 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 71387266 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35982.394366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35982.394366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35982.394366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36080.329154 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36080.329154 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36080.329154 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -343,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33582500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33582500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33582500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33661000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33661000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33661000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35688.097768 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35688.097768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35688.097768 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35695.652174 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35695.652174 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470793 # number of replacements -system.cpu.dcache.tagsinuse 4093.950327 # Cycle average of tags in use -system.cpu.dcache.total_refs 151670470 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474889 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 319.380887 # Average number of references to valid blocks. +system.cpu.dcache.replacements 470870 # number of replacements +system.cpu.dcache.tagsinuse 4093.952106 # Cycle average of tags in use +system.cpu.dcache.total_refs 151563529 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474966 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 319.103955 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.950327 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4093.952106 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113522942 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147524 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits 113415940 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147585 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151670466 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151670466 # number of overall hits -system.cpu.dcache.ReadReq_misses 730602 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303797 # number of WriteReq misses -system.cpu.dcache.demand_misses 2034399 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2034399 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11799452000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19635094216 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31434546216 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31434546216 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114253544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 151563525 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151563525 # number of overall hits +system.cpu.dcache.ReadReq_misses 731363 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303736 # number of WriteReq misses +system.cpu.dcache.demand_misses 2035099 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2035099 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11802867000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19634898764 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31437765764 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31437765764 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 114147303 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153704865 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153704865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006395 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033048 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013236 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013236 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16150.314398 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15059.932042 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15451.514780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15451.514780 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 884996 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 153598624 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153598624 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006407 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033047 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013249 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013249 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16138.178989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15060.486758 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15447.782031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15447.782031 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 886996 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7629.275862 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7646.517241 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423112 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 511747 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047763 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1559510 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1559510 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218855 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256034 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474889 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474889 # number of overall MSHR misses +system.cpu.dcache.writebacks 423193 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 512453 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047680 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1560133 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1560133 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218910 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256056 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474966 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474966 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640196500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3028456494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4668652994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4668652994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640097000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3028332494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4668429494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4668429494 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001918 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7494.443810 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11828.337229 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9831.040504 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9831.040504 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.003092 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003092 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7492.106345 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11826.836684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9828.976167 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74461 # number of replacements -system.cpu.l2cache.tagsinuse 17667.693378 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478022 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90361 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.290136 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74473 # number of replacements +system.cpu.l2cache.tagsinuse 17668.898791 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478122 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90370 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.290716 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1746.744701 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15920.948677 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053306 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485869 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186848 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423112 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196221 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383069 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383069 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32948 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59813 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92761 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92761 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133336500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2066482500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3199819000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3199819000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219796 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423112 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475830 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475830 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.149903 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233614 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194946 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194946 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.732791 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.052881 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34495.305139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34495.305139 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 460000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1750.296576 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15918.602215 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053415 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485797 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186900 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423193 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196240 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 383140 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 383140 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32953 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59816 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92769 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92769 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133504500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2066596000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3200100500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3200100500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219853 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423193 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256056 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475909 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475909 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.149887 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233605 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194930 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194930 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.611750 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.217601 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34495.364831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34495.364831 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 453500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 71 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 76 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6478.873239 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5967.105263 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59333 # number of writebacks +system.cpu.l2cache.writebacks 59331 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32948 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59813 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92761 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92761 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32953 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59816 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92769 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022013500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878097000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2900110500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2900110500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022169500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878238500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2900408000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2900408000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149903 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233614 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194946 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194946 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.984460 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31399.478374 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.329837 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.329837 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149887 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233605 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194930 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194930 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.011926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31400.269159 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.840626 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 485873d05..fea8ea4a1 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index eb566e6f8..a9117199d 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:02:03 -gem5 started Jul 16 2011 00:35:36 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 19:27:45 +gem5 started Aug 17 2011 20:12:24 +gem5 executing on nadc-0388 command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 181676511500 because target called exit() +Exiting @ tick 181028108500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 212b723af..701011da6 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.181677 # Number of seconds simulated -sim_ticks 181676511500 # Number of ticks simulated +sim_seconds 0.181028 # Number of seconds simulated +sim_ticks 181028108500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82416 # Simulator instruction rate (inst/s) -host_tick_rate 24857445 # Simulator tick rate (ticks/s) -host_mem_usage 257796 # Number of bytes of host memory used -host_seconds 7308.74 # Real time elapsed on the host -sim_insts 602359820 # Number of instructions simulated +host_inst_rate 110603 # Simulator instruction rate (inst/s) +host_tick_rate 33239774 # Simulator tick rate (ticks/s) +host_mem_usage 263548 # Number of bytes of host memory used +host_seconds 5446.13 # Real time elapsed on the host +sim_insts 602359805 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 363353024 # number of cpu cycles simulated +system.cpu.numCycles 362056218 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 93642406 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86055517 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3937297 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 88612742 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 82226729 # Number of BTB hits +system.cpu.BPredUnit.lookups 93448154 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 85911629 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3923569 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 88397798 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81789381 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1811116 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1799 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 80077128 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 720176236 # Number of instructions fetch has processed -system.cpu.fetch.Branches 93642406 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84037845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163199656 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20933611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102893232 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 623 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 77424762 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1579270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 362477887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126441 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.976296 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1790445 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1821 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 79878814 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 718366767 # Number of instructions fetch has processed +system.cpu.fetch.Branches 93448154 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83579826 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162526152 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20714981 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102669649 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 673 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 77174070 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1530906 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 361172763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.127936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.978152 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199278398 54.98% 54.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25830413 7.13% 62.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 19932307 5.50% 67.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25118126 6.93% 74.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12539166 3.46% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13666852 3.77% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4829528 1.33% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7994396 2.21% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53288701 14.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198646777 55.00% 55.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25571456 7.08% 62.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19827264 5.49% 67.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25093348 6.95% 74.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12488036 3.46% 77.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13650153 3.78% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4767489 1.32% 83.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7787203 2.16% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53341037 14.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 362477887 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257717 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.982029 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 102756406 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83077250 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 141158544 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19181042 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16304645 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6938686 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2613 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 758024516 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7262 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 16304645 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 116075491 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10185612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 146924183 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72878598 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 743558817 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 188 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 58921601 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10117687 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 591 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 767454765 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3458233737 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3458233609 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 361172763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258104 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.984130 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 102343616 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83020024 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 140521738 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19192459 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16094926 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6886310 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2563 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 756045465 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7091 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 16094926 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 115645953 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9675212 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 105916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 146342748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73308008 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 741744489 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59347402 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10155907 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 308 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 765934734 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3449682594 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3449682466 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417418 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 140037342 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6399 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6398 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 130096693 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 183828757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85345746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 25811031 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37497456 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 715547655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7366 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 667339389 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 840250 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 112563133 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 285197370 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1065 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 362477887 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.841049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.675765 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 138517335 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6417 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6420 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 130475053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 183427028 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85118109 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 19617047 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24959505 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 714042486 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 668482439 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 813187 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 110903932 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 272103092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1046 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 361172763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.850866 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.720469 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89414922 24.67% 24.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90190265 24.88% 49.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 79396670 21.90% 71.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 45359007 12.51% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28036434 7.73% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16328709 4.50% 96.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8232346 2.27% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5060866 1.40% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 458668 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89609578 24.81% 24.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 92103808 25.50% 50.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76957239 21.31% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 43677932 12.09% 83.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26190048 7.25% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17902760 4.96% 95.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7158113 1.98% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6378593 1.77% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1194692 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 362477887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 361172763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 175813 5.16% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2586346 75.94% 81.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 643459 18.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 174743 4.36% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2924154 73.03% 77.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 905037 22.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 414934483 62.18% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6549 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 174108289 26.09% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 78290065 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 414572332 62.02% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6557 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174888345 26.16% 88.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79015202 11.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 667339389 # Type of FU issued -system.cpu.iq.rate 1.836614 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3405618 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005103 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1701402497 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 828782976 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 653330026 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 668482439 # Type of FU issued +system.cpu.iq.rate 1.846350 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4003934 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005990 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1702954726 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 825626408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 654174988 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 670744987 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 672486353 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 28288943 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28890587 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34876158 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 159827 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 665311 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 15124729 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34474432 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 677004 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 14897095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15440 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12578 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12604 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16304645 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 784511 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 50454 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 715624477 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2065189 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 183828757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85345746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6034 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13250 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5066 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 665311 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4094363 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 486296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4580659 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659689382 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 170637671 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7650007 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16094926 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 778321 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 50892 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 714119394 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2033981 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 183427028 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85118109 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6015 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12993 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 677004 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4081658 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 498372 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4580030 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 660769173 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171345747 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7713266 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69456 # number of nop insts executed -system.cpu.iew.exec_refs 247330517 # number of memory reference insts executed -system.cpu.iew.exec_branches 76920251 # Number of branches executed -system.cpu.iew.exec_stores 76692846 # Number of stores executed -system.cpu.iew.exec_rate 1.815560 # Inst execution rate -system.cpu.iew.wb_sent 655349780 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 653330042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 425170180 # num instructions producing a value -system.cpu.iew.wb_consumers 661395893 # num instructions consuming a value +system.cpu.iew.exec_nop 69564 # number of nop insts executed +system.cpu.iew.exec_refs 248875630 # number of memory reference insts executed +system.cpu.iew.exec_branches 76892303 # Number of branches executed +system.cpu.iew.exec_stores 77529883 # Number of stores executed +system.cpu.iew.exec_rate 1.825046 # Inst execution rate +system.cpu.iew.wb_sent 656292597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 654175004 # cumulative count of insts written-back +system.cpu.iew.wb_producers 424501609 # num instructions producing a value +system.cpu.iew.wb_consumers 659455960 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.798059 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642838 # average fanout of values written-back +system.cpu.iew.wb_rate 1.806833 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643715 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359871 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 113270616 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6301 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3996549 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 346173243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.740053 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.116155 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 111769419 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6298 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3982936 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345077838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.745577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.124891 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 112054418 32.37% 32.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 109168598 31.54% 63.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49782434 14.38% 78.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10491888 3.03% 81.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23443534 6.77% 88.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14637280 4.23% 92.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8029663 2.32% 94.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1511197 0.44% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17054231 4.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 111837000 32.41% 32.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 108539519 31.45% 63.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49573446 14.37% 78.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10197254 2.96% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23493632 6.81% 87.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14599312 4.23% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8154465 2.36% 94.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1281875 0.37% 94.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17401335 5.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 346173243 # Number of insts commited each cycle -system.cpu.commit.count 602359871 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 345077838 # Number of insts commited each cycle +system.cpu.commit.count 602359856 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173615 # Number of memory references committed -system.cpu.commit.loads 148952598 # Number of loads committed +system.cpu.commit.refs 219173609 # Number of memory references committed +system.cpu.commit.loads 148952595 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828605 # Number of branches committed +system.cpu.commit.branches 70828602 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522655 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522643 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 17054231 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 17401335 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1044748887 # The number of ROB reads -system.cpu.rob.rob_writes 1447602374 # The number of ROB writes -system.cpu.timesIdled 36933 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 875137 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359820 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359820 # Number of Instructions Simulated -system.cpu.cpi 0.603216 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.603216 # CPI: Total CPI of All Threads -system.cpu.ipc 1.657781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.657781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3292742614 # number of integer regfile reads -system.cpu.int_regfile_writes 679039343 # number of integer regfile writes +system.cpu.rob.rob_reads 1041805166 # The number of ROB reads +system.cpu.rob.rob_writes 1444392656 # The number of ROB writes +system.cpu.timesIdled 37065 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 883455 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359805 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated +system.cpu.cpi 0.601063 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.601063 # CPI: Total CPI of All Threads +system.cpu.ipc 1.663719 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.663719 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3299876653 # number of integer regfile reads +system.cpu.int_regfile_writes 679084326 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 961073357 # number of misc regfile reads -system.cpu.misc_regfile_writes 2664 # number of misc regfile writes -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 658.859257 # Cycle average of tags in use -system.cpu.icache.total_refs 77423742 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 99644.455598 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 960654614 # number of misc regfile reads +system.cpu.misc_regfile_writes 2658 # number of misc regfile writes +system.cpu.icache.replacements 39 # number of replacements +system.cpu.icache.tagsinuse 659.213464 # Cycle average of tags in use +system.cpu.icache.total_refs 77173072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 101410.081472 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 658.859257 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.321709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 77423742 # number of ReadReq hits -system.cpu.icache.demand_hits 77423742 # number of demand (read+write) hits -system.cpu.icache.overall_hits 77423742 # number of overall hits -system.cpu.icache.ReadReq_misses 1020 # number of ReadReq misses -system.cpu.icache.demand_misses 1020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35800500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35800500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 77424762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 77424762 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 77424762 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 659.213464 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.321882 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 77173072 # number of ReadReq hits +system.cpu.icache.demand_hits 77173072 # number of demand (read+write) hits +system.cpu.icache.overall_hits 77173072 # number of overall hits +system.cpu.icache.ReadReq_misses 998 # number of ReadReq misses +system.cpu.icache.demand_misses 998 # number of demand (read+write) misses +system.cpu.icache.overall_misses 998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 34962500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 34962500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 34962500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 77174070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 77174070 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 77174070 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35098.529412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35098.529412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35098.529412 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35032.565130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35032.565130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35032.565130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 243 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 243 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 243 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 777 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 777 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 777 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 762 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 762 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 762 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26636000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26035000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26035000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26035000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34280.566281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34166.666667 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440951 # number of replacements -system.cpu.dcache.tagsinuse 4094.785016 # Cycle average of tags in use -system.cpu.dcache.total_refs 208890975 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445047 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 469.368348 # Average number of references to valid blocks. +system.cpu.dcache.replacements 441073 # number of replacements +system.cpu.dcache.tagsinuse 4094.780664 # Cycle average of tags in use +system.cpu.dcache.total_refs 208769486 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445169 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 468.966810 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.785016 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999703 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 140815101 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 68073201 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1331 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 208888302 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 208888302 # number of overall hits -system.cpu.dcache.ReadReq_misses 248858 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1344330 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 4094.780664 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999702 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 140903051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67863771 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1333 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 208766822 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 208766822 # number of overall hits +system.cpu.dcache.ReadReq_misses 249137 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1553760 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1593188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1593188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3280375500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26109782527 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 29390158027 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 29390158027 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 141063959 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1802897 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1802897 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3284237500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 27026235527 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30310473027 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30310473027 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 141152188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1351 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1331 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 210481490 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 210481490 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.019366 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.006662 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.007569 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.007569 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13181.716079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19422.152691 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 21555.555556 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18447.388524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18447.388524 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1342 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 210569719 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 210569719 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001765 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.022383 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.006706 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008562 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008562 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13182.455838 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17394.086298 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 22166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16812.093551 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16812.093551 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -422,70 +422,72 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395037 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51168 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1096973 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 395116 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51340 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1306387 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1148141 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1148141 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197690 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247357 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445047 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445047 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1357727 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1357727 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197797 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247373 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445170 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445170 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1624799500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2561111027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4185910527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4185910527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1624472000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2544428527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4168900527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4168900527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8218.926096 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.905598 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8212.824259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.797266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9364.738251 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72983 # number of replacements -system.cpu.l2cache.tagsinuse 17823.829612 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421659 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88508 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.764078 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72968 # number of replacements +system.cpu.l2cache.tagsinuse 17823.256167 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421257 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88492 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.760396 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1903.131187 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15920.698425 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058079 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485861 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165659 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395037 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 188979 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354638 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354638 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32805 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58381 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91186 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91186 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126836000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2004580000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3131416000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3131416000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198464 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395037 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247360 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445824 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445824 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.236016 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204534 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204534 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.519890 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.171015 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34340.973395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34340.973395 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1903.843188 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15919.412978 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058101 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485822 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165755 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395116 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 189016 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354771 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354771 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32799 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58360 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91159 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91159 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2004231000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130969500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130969500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198554 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395116 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247376 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445930 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445930 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235916 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204424 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204424 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34352.830879 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34342.546265 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34346.246668 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34346.246668 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -494,28 +496,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58139 # number of writebacks +system.cpu.l2cache.writebacks 58122 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32796 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58381 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91177 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91177 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58360 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020208500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822855000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2843063500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2843063500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1020255000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822537500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2842792500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2842792500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165249 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236016 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204513 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.711306 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31223.428855 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165144 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235916 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204404 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204404 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.821592 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31229.223783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.069117 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index d391b02a1..69d6d5791 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index a3848a023..f40ea4f95 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 18 2011 18:04:45 -gem5 started Jul 18 2011 18:04:49 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 17 2011 16:58:37 +gem5 started Aug 17 2011 16:59:36 +gem5 executing on nadc-0388 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -38,4 +40,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 568878317500 because target called exit() +Exiting @ tick 424846003000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index cb1a626e1..386994981 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,251 +1,252 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.568878 # Number of seconds simulated -sim_ticks 568878317500 # Number of ticks simulated +sim_seconds 0.424846 # Number of seconds simulated +sim_ticks 424846003000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127390 # Simulator instruction rate (inst/s) -host_tick_rate 51557660 # Simulator tick rate (ticks/s) -host_mem_usage 254284 # Number of bytes of host memory used -host_seconds 11033.83 # Real time elapsed on the host +host_inst_rate 130905 # Simulator instruction rate (inst/s) +host_tick_rate 39566335 # Simulator tick rate (ticks/s) +host_mem_usage 260032 # Number of bytes of host memory used +host_seconds 10737.56 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1137756636 # number of cpu cycles simulated +system.cpu.numCycles 849692007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 106888514 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 95381218 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5420176 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 103841112 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 102522993 # Number of BTB hits +system.cpu.BPredUnit.lookups 103951242 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 92817618 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5441892 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 101027131 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 99845588 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180638334 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1773593568 # Number of instructions fetch has processed -system.cpu.fetch.Branches 106888514 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 102524223 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 381465937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37837382 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 543268181 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1639 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 176102907 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 948661 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1137451065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.563275 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.753191 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1240 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 176461208 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1731297968 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103951242 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99846828 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 372380430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 32542357 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 273950532 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1598 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 171982366 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1072419 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 849334249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.043796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 755985128 66.46% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 84858619 7.46% 73.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 46317326 4.07% 78.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24386522 2.14% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 34286806 3.01% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34702861 3.05% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 15288834 1.34% 87.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7898837 0.69% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 133726132 11.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 476953819 56.16% 56.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82874443 9.76% 65.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45104012 5.31% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23823207 2.80% 74.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 33449263 3.94% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 34018296 4.01% 81.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14934889 1.76% 83.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7594649 0.89% 84.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 130581671 15.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1137451065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093947 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.558851 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 242051252 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 485212822 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 328784553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49325481 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 32076957 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1761674668 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 32076957 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 305517434 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 121834770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66846353 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 312365178 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 298810373 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1743986914 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 179337186 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 63010596 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 40441846 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1455333902 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2943882462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2909924571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33957891 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 849334249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122340 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.037559 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 228750775 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 225010682 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 340329593 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 28702732 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 26540467 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1719853048 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 26540467 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 263479088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 41404306 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55665718 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333164025 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 129080645 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1702621917 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 27946870 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 65424391 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 16478266 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1420563184 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2876973295 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2842990293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33983002 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 210563450 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3348344 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3348760 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 542381303 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 470273369 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 190181130 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 405202372 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 165490113 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1617272450 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3218242 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1489328778 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 214120992 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 291680058 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 974571 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1137451065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.140672 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 175792732 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3237844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3287220 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 297721307 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 456905033 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 186186881 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 277685429 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 94682535 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1573041480 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3078086 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1493571680 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 168879 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 169173312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193746620 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 834415 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 849334249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.758520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.350284 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 308893636 27.16% 27.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 389103497 34.21% 61.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 284410316 25.00% 86.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 106768220 9.39% 95.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33533421 2.95% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12093348 1.06% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2169743 0.19% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 349965 0.03% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128919 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 177901650 20.95% 20.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 206358445 24.30% 45.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 226462970 26.66% 71.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 151667203 17.86% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 64968416 7.65% 97.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14273144 1.68% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6071046 0.71% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1430974 0.17% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 200401 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1137451065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 849334249 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 267660 8.55% 8.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 151678 4.84% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2460340 78.58% 91.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 251345 8.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 106837 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 176348 8.29% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1497549 70.41% 83.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 346224 16.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 892252171 59.91% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2624686 0.18% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 423006461 28.40% 88.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171445460 11.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 886788388 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2623578 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 430759220 28.84% 88.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173400494 11.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1489328778 # Type of FU issued -system.cpu.iq.rate 1.309005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3131023 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002102 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4101702594 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1825725243 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1471768719 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17605097 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9240911 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8506597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1483444207 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9015594 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 136711373 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1493571680 # Type of FU issued +system.cpu.iq.rate 1.757780 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2126958 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001424 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3820899737 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1736825318 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1473365597 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17873709 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9212850 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8524107 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1486479437 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9219201 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 209970408 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 67760525 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20730 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 356316 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 23332988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 54392189 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 142413 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 763229 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 19338739 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 46765 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 609 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 45345 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 32076957 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2310683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98308 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1723301655 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4186060 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 470273369 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 190181130 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3115724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 51873 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4910 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 356316 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5266619 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 459051 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5725670 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1483096593 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 420520679 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6232185 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 26540467 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2525220 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 145175 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1675654819 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4255922 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 456905033 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 186186881 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2976415 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59600 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9064 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 763229 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5291175 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 468114 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5759289 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1486215446 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 427697474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7356234 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 102810963 # number of nop insts executed -system.cpu.iew.exec_refs 590732580 # number of memory reference insts executed -system.cpu.iew.exec_branches 90117242 # Number of branches executed -system.cpu.iew.exec_stores 170211901 # Number of stores executed -system.cpu.iew.exec_rate 1.303527 # Inst execution rate -system.cpu.iew.wb_sent 1481375672 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1480275316 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1168908244 # num instructions producing a value -system.cpu.iew.wb_consumers 1211941530 # num instructions consuming a value +system.cpu.iew.exec_nop 99535253 # number of nop insts executed +system.cpu.iew.exec_refs 599761085 # number of memory reference insts executed +system.cpu.iew.exec_branches 90544158 # Number of branches executed +system.cpu.iew.exec_stores 172063611 # Number of stores executed +system.cpu.iew.exec_rate 1.749123 # Inst execution rate +system.cpu.iew.wb_sent 1483627085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1481889704 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1175309728 # num instructions producing a value +system.cpu.iew.wb_consumers 1225337993 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.301047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.964492 # average fanout of values written-back +system.cpu.iew.wb_rate 1.744032 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.959172 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 233686324 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 186029259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5420176 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1105374719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.347528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786900 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5441892 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 822794393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.810323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.360899 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 387659384 35.07% 35.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 461508986 41.75% 76.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51139183 4.63% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 98630108 8.92% 90.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 32299027 2.92% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8730687 0.79% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 27864776 2.52% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10533124 0.95% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 27009444 2.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 271095175 32.95% 32.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 302645797 36.78% 69.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 45322356 5.51% 75.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 68686908 8.35% 83.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 22732084 2.76% 86.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9729610 1.18% 87.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 29628308 3.60% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10807412 1.31% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 62146743 7.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1105374719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 822794393 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -255,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 27009444 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 62146743 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2801510024 # The number of ROB reads -system.cpu.rob.rob_writes 3478548339 # The number of ROB writes -system.cpu.timesIdled 10892 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 305571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2436135334 # The number of ROB reads +system.cpu.rob.rob_writes 3377694632 # The number of ROB writes +system.cpu.timesIdled 11301 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 357758 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.809443 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809443 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2001717837 # number of integer regfile reads -system.cpu.int_regfile_writes 1303407681 # number of integer regfile writes -system.cpu.fp_regfile_reads 16935756 # number of floating regfile reads -system.cpu.fp_regfile_writes 10440358 # number of floating regfile writes -system.cpu.misc_regfile_reads 596613763 # number of misc regfile reads +system.cpu.cpi 0.604503 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.604503 # CPI: Total CPI of All Threads +system.cpu.ipc 1.654251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.654251 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2015965671 # number of integer regfile reads +system.cpu.int_regfile_writes 1304123959 # number of integer regfile writes +system.cpu.fp_regfile_reads 16988422 # number of floating regfile reads +system.cpu.fp_regfile_writes 10452078 # number of floating regfile writes +system.cpu.misc_regfile_reads 605607850 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.icache.replacements 165 # number of replacements -system.cpu.icache.tagsinuse 1040.317886 # Cycle average of tags in use -system.cpu.icache.total_refs 176101137 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1300 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 135462.413077 # Average number of references to valid blocks. +system.cpu.icache.replacements 166 # number of replacements +system.cpu.icache.tagsinuse 1030.164560 # Cycle average of tags in use +system.cpu.icache.total_refs 171980565 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 132598.739399 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1040.317886 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.507968 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 176101137 # number of ReadReq hits -system.cpu.icache.demand_hits 176101137 # number of demand (read+write) hits -system.cpu.icache.overall_hits 176101137 # number of overall hits -system.cpu.icache.ReadReq_misses 1770 # number of ReadReq misses -system.cpu.icache.demand_misses 1770 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1770 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 61911500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 61911500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 61911500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 176102907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 176102907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 176102907 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1030.164560 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.503010 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 171980565 # number of ReadReq hits +system.cpu.icache.demand_hits 171980565 # number of demand (read+write) hits +system.cpu.icache.overall_hits 171980565 # number of overall hits +system.cpu.icache.ReadReq_misses 1801 # number of ReadReq misses +system.cpu.icache.demand_misses 1801 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1801 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62794000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62794000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62794000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 171982366 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 171982366 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 171982366 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34978.248588 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34978.248588 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34978.248588 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34866.185453 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34866.185453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34866.185453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 469 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 469 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 469 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1301 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1301 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1301 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 503 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 503 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 503 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45277500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45277500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45277500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45168500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45168500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45168500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34802.075327 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34802.075327 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34802.075327 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.536210 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34798.536210 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475458 # number of replacements -system.cpu.dcache.tagsinuse 4095.400143 # Cycle average of tags in use -system.cpu.dcache.total_refs 447983825 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479554 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 934.167633 # Average number of references to valid blocks. +system.cpu.dcache.replacements 475459 # number of replacements +system.cpu.dcache.tagsinuse 4095.196777 # Cycle average of tags in use +system.cpu.dcache.total_refs 381789765 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479555 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 796.133426 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.400143 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999854 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 282962670 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 165019836 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 4095.196777 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 216852847 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 164935599 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 447982506 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 447982506 # number of overall hits -system.cpu.dcache.ReadReq_misses 815560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1826980 # number of WriteReq misses +system.cpu.dcache.demand_hits 381788446 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 381788446 # number of overall hits +system.cpu.dcache.ReadReq_misses 816608 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1911217 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2642540 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2642540 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10724956500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26607670410 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 37332626910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 37332626910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 283778230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 2727825 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2727825 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11966798000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 30001558232 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 268000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency 41968356232 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 41968356232 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 217669455 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 450625046 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 450625046 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002874 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010950 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 384516271 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 384516271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011455 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.005864 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005864 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13150.419957 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14563.744765 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14127.554137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14127.554137 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.007094 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.007094 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14654.274756 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15697.620015 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15385.281766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15385.281766 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2375 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2071.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 603466 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1559527 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2162993 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2162993 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212094 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267453 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426734 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 604334 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1643943 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2248277 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2248277 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212274 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267274 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479547 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479547 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479548 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1622799000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3442234519 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5065033519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5065033519 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1589212000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3626989841 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 247000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5216201841 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5216201841 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000747 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001602 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001064 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001064 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7651.319698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12870.427772 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10562.121166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10562.121166 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001247 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001247 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7486.606933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13570.305533 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10877.329988 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75848 # number of replacements -system.cpu.l2cache.tagsinuse 17699.311990 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464479 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.084108 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75834 # number of replacements +system.cpu.l2cache.tagsinuse 17835.857801 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464745 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.087186 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1967.262312 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15732.049678 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.480104 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179745 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426814 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 207036 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386781 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386781 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33650 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60424 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94074 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94074 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1149817000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2071878000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3221695000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3221695000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 213395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 426814 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 267460 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 480855 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 480855 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157689 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.225918 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195639 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195639 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34169.895988 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.991129 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34246.391139 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34246.391139 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2067.900619 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15767.957182 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.063107 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.481200 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179917 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426734 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 206874 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386791 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386791 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33655 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60407 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94062 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94062 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1145507000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2078924500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3224431500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3224431500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213572 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426734 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267281 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480853 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480853 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157582 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.226006 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195615 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195615 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.755311 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34415.291274 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34279.852650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34279.852650 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59264 # number of writebacks +system.cpu.l2cache.writebacks 59251 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60424 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94074 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94074 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33655 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60407 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044115000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1884920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2929035000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2929035000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1043470000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892046500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2935516500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2935516500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157689 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225918 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195639 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195639 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31028.677563 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31194.889448 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.435933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.435933 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195615 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195615 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.902689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31321.643187 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.314729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 29b391479..244f95975 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/gzip +executable=/arm/scratch/sysexplr/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index a4b9477d1..03608f531 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 15 2011 18:01:24 -gem5 started Jul 15 2011 20:50:21 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 18 2011 15:15:16 +gem5 started Aug 18 2011 15:56:00 +gem5 executing on nadc-0330 command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1062,4 +1064,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 749294021000 because target called exit() +Exiting @ tick 631043541000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 06ad1be7c..e79e605fc 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.749294 # Number of seconds simulated -sim_ticks 749294021000 # Number of ticks simulated +sim_seconds 0.631044 # Number of seconds simulated +sim_ticks 631043541000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60097 # Simulator instruction rate (inst/s) -host_tick_rate 27771108 # Simulator tick rate (ticks/s) -host_mem_usage 253640 # Number of bytes of host memory used -host_seconds 26981.06 # Real time elapsed on the host +host_inst_rate 115557 # Simulator instruction rate (inst/s) +host_tick_rate 44971725 # Simulator tick rate (ticks/s) +host_mem_usage 259448 # Number of bytes of host memory used +host_seconds 14032.01 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1498588043 # number of cpu cycles simulated +system.cpu.numCycles 1262087083 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 174353147 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 174353147 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 8954437 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 165220115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 164182726 # Number of BTB hits +system.cpu.BPredUnit.lookups 172291796 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 172291796 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7138140 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 165694672 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 164669298 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 197081055 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1427085390 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174353147 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 164182726 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 405643185 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 122961003 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 787624963 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 296 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 184521623 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1125658 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1498287760 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.715646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.067557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187457062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1372690648 # Number of instructions fetch has processed +system.cpu.fetch.Branches 172291796 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 164669298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 395189805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 112734719 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 580214048 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 390 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 176517375 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1196842 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1261930799 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.983622 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.216635 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1095772488 73.13% 73.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26898081 1.80% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18204566 1.22% 76.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17325497 1.16% 77.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23844032 1.59% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 17164690 1.15% 80.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40138916 2.68% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38301790 2.56% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220637700 14.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 869789775 68.93% 68.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26036678 2.06% 70.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17623388 1.40% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17507853 1.39% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23833900 1.89% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16948501 1.34% 77.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37076715 2.94% 79.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38063595 3.02% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215050394 17.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1498287760 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116345 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.952287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 300082946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 691709075 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 302993844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 95563685 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 107938210 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2548886917 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 107938210 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 357219052 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 188499779 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 326836039 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 517791392 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2482037348 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3801 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 365556322 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 131873603 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2483397127 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6018409804 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6018402452 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7352 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1261930799 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136513 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.087635 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 280972137 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 498778976 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 296140618 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 86969632 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 99069436 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2448347491 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 99069436 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 329963846 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 111715541 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3471 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 317046121 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 404132384 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2409604498 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5352 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 248907784 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 129341699 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2413708682 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5838625893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5838622529 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3364 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 865402477 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 169 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 866525950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 641640659 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 260570368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 562700768 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 217406187 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2410485981 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 96 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1860645622 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 297905 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 788955121 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1689446934 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1498287760 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.241848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.192555 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 795714032 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 96 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 96 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 735209031 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 621902213 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 256079721 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 462456843 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 162376544 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2335230964 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1868917555 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 372085 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 713469187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1453396284 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1261930799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.480998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.347284 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 431380009 28.79% 28.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 604501817 40.35% 69.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252266719 16.84% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 123988851 8.28% 94.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 58817201 3.93% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20817096 1.39% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5535754 0.37% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 767498 0.05% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 212815 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 328585186 26.04% 26.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 421239585 33.38% 59.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 248611798 19.70% 79.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 160686589 12.73% 91.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 61778588 4.90% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 27094790 2.15% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12009524 0.95% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1648751 0.13% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 275988 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1498287760 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1261930799 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 150800 3.27% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3625649 78.65% 81.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 833140 18.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 173659 2.51% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6577211 95.02% 97.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 171078 2.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28076414 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1193303219 64.13% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 446918343 24.02% 89.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192347646 10.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26325646 1.41% 1.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1180659411 63.17% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 467364876 25.01% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194567622 10.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1860645622 # Type of FU issued -system.cpu.iq.rate 1.241599 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4609589 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5224486461 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3205506305 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1835062624 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 37 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2036 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1837178777 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 118533940 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1868917555 # Type of FU issued +system.cpu.iq.rate 1.480815 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6921948 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003704 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5007059820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3055406588 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1845403489 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1849513807 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 50 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 191278132 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 222598534 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4428 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6067505 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 72384311 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 202860088 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 64357 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6719705 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 67893664 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30883 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 674 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36961 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 107938210 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267962 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121894 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2410486077 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 630348 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 641640659 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 260570368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 96 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66625 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6067505 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4521579 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4614873 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 9136452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1840276566 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 443019520 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 20369056 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 99069436 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1201433 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 112801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2335231055 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 659652 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 621902213 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 256079721 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 57218 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6719705 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4534206 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2790969 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7325175 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1852764474 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 461769012 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16153081 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 634826939 # number of memory reference insts executed -system.cpu.iew.exec_branches 111934330 # Number of branches executed -system.cpu.iew.exec_stores 191807419 # Number of stores executed -system.cpu.iew.exec_rate 1.228007 # Inst execution rate -system.cpu.iew.wb_sent 1838313315 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1835062636 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1427807499 # num instructions producing a value -system.cpu.iew.wb_consumers 2086812885 # num instructions consuming a value +system.cpu.iew.exec_refs 655479520 # number of memory reference insts executed +system.cpu.iew.exec_branches 112349751 # Number of branches executed +system.cpu.iew.exec_stores 193710508 # Number of stores executed +system.cpu.iew.exec_rate 1.468016 # Inst execution rate +system.cpu.iew.wb_sent 1850700108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1845403509 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1443346270 # num instructions producing a value +system.cpu.iew.wb_consumers 2115960944 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.224528 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.684205 # average fanout of values written-back +system.cpu.iew.wb_rate 1.462184 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682123 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 789002361 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 713749948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8954478 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1390349550 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.166249 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.425241 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7138191 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1162861363 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.394400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.690304 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 517686759 37.23% 37.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 532094045 38.27% 75.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 126340876 9.09% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122997225 8.85% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 42691092 3.07% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23602651 1.70% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988906 0.36% 98.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10568517 0.76% 99.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 9379479 0.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 395572650 34.02% 34.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 431612406 37.12% 71.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 98230430 8.45% 79.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 129131818 11.10% 90.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30975376 2.66% 93.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25883779 2.23% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22467188 1.93% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 13999993 1.20% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14987723 1.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1390349550 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1162861363 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 9379479 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14987723 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791466414 # The number of ROB reads -system.cpu.rob.rob_writes 4929477020 # The number of ROB writes -system.cpu.timesIdled 44919 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 300283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3483117570 # The number of ROB reads +system.cpu.rob.rob_writes 4770120987 # The number of ROB writes +system.cpu.timesIdled 44517 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 156284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.924202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.924202 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082014 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082014 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3236351438 # number of integer regfile reads -system.cpu.int_regfile_writes 1827281055 # number of integer regfile writes -system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 926454727 # number of misc regfile reads -system.cpu.icache.replacements 14 # number of replacements -system.cpu.icache.tagsinuse 821.249711 # Cycle average of tags in use -system.cpu.icache.total_refs 184520340 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 203664.834437 # Average number of references to valid blocks. +system.cpu.cpi 0.778348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.778348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.284772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.284772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289423155 # number of integer regfile reads +system.cpu.int_regfile_writes 1840387955 # number of integer regfile writes +system.cpu.fp_regfile_reads 20 # number of floating regfile reads +system.cpu.misc_regfile_reads 943704220 # number of misc regfile reads +system.cpu.icache.replacements 12 # number of replacements +system.cpu.icache.tagsinuse 813.354682 # Cycle average of tags in use +system.cpu.icache.total_refs 176516095 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 197445.296421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 821.249711 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.401001 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 184520379 # number of ReadReq hits -system.cpu.icache.demand_hits 184520379 # number of demand (read+write) hits -system.cpu.icache.overall_hits 184520379 # number of overall hits -system.cpu.icache.ReadReq_misses 1244 # number of ReadReq misses -system.cpu.icache.demand_misses 1244 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43837000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43837000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43837000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 184521623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 184521623 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 184521623 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 813.354682 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.397146 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 176516138 # number of ReadReq hits +system.cpu.icache.demand_hits 176516138 # number of demand (read+write) hits +system.cpu.icache.overall_hits 176516138 # number of overall hits +system.cpu.icache.ReadReq_misses 1237 # number of ReadReq misses +system.cpu.icache.demand_misses 1237 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1237 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43406000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43406000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43406000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 176517375 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 176517375 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 176517375 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35238.745981 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35238.745981 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35238.745981 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35089.733226 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35089.733226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35089.733226 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,159 +306,167 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 898 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 898 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 898 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32023000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32023000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32023000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31587000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31587000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31587000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35267.621145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35267.621145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35267.621145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35174.832962 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35174.832962 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459267 # number of replacements -system.cpu.dcache.tagsinuse 4095.145013 # Cycle average of tags in use -system.cpu.dcache.total_refs 511187603 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463363 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1103.211959 # Average number of references to valid blocks. +system.cpu.dcache.replacements 459230 # number of replacements +system.cpu.dcache.tagsinuse 4094.984798 # Cycle average of tags in use +system.cpu.dcache.total_refs 457142531 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463326 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 986.654172 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 317737000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.145013 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 324252389 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186935214 # number of WriteReq hits -system.cpu.dcache.demand_hits 511187603 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 511187603 # number of overall hits -system.cpu.dcache.ReadReq_misses 216893 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1250843 # number of WriteReq misses -system.cpu.dcache.demand_misses 1467736 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1467736 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2202140000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24456528497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 26658668497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 26658668497 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 324469282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 4094.984798 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999752 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 270249416 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186893112 # number of WriteReq hits +system.cpu.dcache.demand_hits 457142528 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 457142528 # number of overall hits +system.cpu.dcache.ReadReq_misses 217407 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1292945 # number of WriteReq misses +system.cpu.dcache.demand_misses 1510352 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1510352 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2208510500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25332209498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 27540719998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 27540719998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 270466823 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 512655339 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 512655339 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000668 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006647 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002863 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002863 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10153.116975 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19552.036904 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18163.122317 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18163.122317 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1683000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 471232500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 455 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29502 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3698.901099 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15972.900142 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses 458652880 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 458652880 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006871 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.003293 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003293 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10158.414862 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19592.642764 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18234.636693 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18234.636693 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1882500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 494592500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 34873 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3905.601660 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14182.677143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 410236 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3187 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1001186 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1004373 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1004373 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213706 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249657 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463363 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463363 # number of overall MSHR misses +system.cpu.dcache.writebacks 410188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1043440 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1047022 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1047022 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213825 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249505 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463330 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463330 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1537618500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2504912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4042530500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4042530500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1535603000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2500577500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4036180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4036180500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7195.017922 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10033.413844 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8724.327363 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8724.327363 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000791 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.001010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7181.587747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10022.153865 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8711.243606 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73626 # number of replacements -system.cpu.l2cache.tagsinuse 18020.121122 # Cycle average of tags in use -system.cpu.l2cache.total_refs 453087 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89234 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.077515 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73611 # number of replacements +system.cpu.l2cache.tagsinuse 18032.065292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 453266 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89232 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.079635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1915.061823 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16105.059300 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058443 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491487 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181487 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410236 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190884 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372371 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372371 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33119 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58779 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91898 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91898 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130363000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2022275000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3152638000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3152638000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214606 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410236 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249663 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464269 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464269 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154325 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235433 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197941 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197941 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34130.348139 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.719373 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.839082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.839082 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 116500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1960.203068 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16071.862223 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.059821 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.490474 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181561 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410188 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 190780 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372341 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372341 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33157 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 58724 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91881 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91881 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130411500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2017247500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3147659000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3147659000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214718 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410188 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249504 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464222 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464222 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154421 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235363 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197925 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197925 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34092.695358 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34351.329950 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34257.996757 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34257.996757 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 204000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 95 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1226.315789 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1685.950413 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58523 # number of writebacks +system.cpu.l2cache.writebacks 58498 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33119 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58779 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91898 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91898 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33157 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58724 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91881 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1830910000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2857815500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2857815500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028041500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829105500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2857147000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2857147000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154325 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235433 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197941 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197941 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.537033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.049831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31097.689830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31097.689830 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235363 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197925 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197925 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.262840 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31147.495062 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.167869 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |