diff options
| author | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2010-09-09 14:40:19 -0400 |
| commit | 9e45ada1718b6df9310757fdc7cd78db4695516f (patch) | |
| tree | c5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/long/00.gzip/ref | |
| parent | 12497284949cb5418e6bc403723c034aee655666 (diff) | |
| download | gem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz | |
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/long/00.gzip/ref')
20 files changed, 1071 insertions, 1049 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 787ff8db0..850b52f90 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -353,7 +353,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 8cfa09dc6..9bd144353 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:24:00 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -46,3 +46,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 169506496500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index eda9ea869..29244fba0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 217525 # Simulator instruction rate (inst/s) -host_mem_usage 207124 # Number of bytes of host memory used -host_seconds 2599.94 # Real time elapsed on the host -host_tick_rate 64460403 # Simulator tick rate (ticks/s) +host_inst_rate 178555 # Simulator instruction rate (inst/s) +host_mem_usage 207544 # Number of bytes of host memory used +host_seconds 3167.39 # Real time elapsed on the host +host_tick_rate 53516139 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.167593 # Number of seconds simulated -sim_ticks 167593085500 # Number of ticks simulated +sim_seconds 0.169506 # Number of seconds simulated +sim_ticks 169506496500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 63922842 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 71487962 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 180 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4121924 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70504427 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76440051 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1674270 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 64068954 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71556079 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4120910 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70589657 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76519042 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1672225 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 18448626 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 19702213 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 323575021 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 327417755 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.838193 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.277454 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 107931872 33.36% 33.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 101513205 31.37% 64.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 37265964 11.52% 76.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 10166735 3.14% 79.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 11290718 3.49% 82.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21721468 6.71% 89.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 12702626 3.93% 93.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2533807 0.78% 94.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 105871733 32.34% 32.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 108541066 33.15% 65.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 36996526 11.30% 76.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 11988281 3.66% 80.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 10398233 3.18% 83.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21777635 6.65% 90.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 9735285 2.97% 93.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2406783 0.74% 93.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 19702213 6.02% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 323575021 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 327417755 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4121096 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4120073 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61591802 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 63088611 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.592670 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.592670 # CPI: Total CPI of All Threads +system.cpu.cpi 0.599437 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.599437 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113443216 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112634831 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 15560393000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 808385 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 590181 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 218204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 116877204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7693.277195 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 116024078 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16646128000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 853126 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 634854 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1679227000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001868 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218272 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37116231 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76584863381 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.059189 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2335090 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1996724 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 338366 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37146976 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 73589663391 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.058410 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2304345 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1968193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 11570226999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 336152 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7088.486726 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 316.462124 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.avg_refs 323.627554 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 802995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 800999 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152894537 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29313.182507 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149751062 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 92145256381 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020560 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3143475 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2586905 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13749247995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003640 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 556570 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 156328525 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 28578.502032 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153171054 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 90235791391 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020198 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3157471 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2603047 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13249453999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 554424 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999563 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.208277 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 152894537 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29313.182507 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999568 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.232018 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 156328525 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 28578.502032 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149751062 # number of overall hits -system.cpu.dcache.overall_miss_latency 92145256381 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020560 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3143475 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2586905 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13749247995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003640 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 556570 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153171054 # number of overall hits +system.cpu.dcache.overall_miss_latency 90235791391 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020198 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3157471 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2603047 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13249453999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 554424 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 470982 # number of replacements -system.cpu.dcache.sampled_refs 475078 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 471007 # number of replacements +system.cpu.dcache.sampled_refs 475103 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.208277 # Cycle average of tags in use -system.cpu.dcache.total_refs 150344193 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126612000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 335213 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 51119249 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 861 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4177292 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689843810 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144051375 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122990983 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9853353 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3386 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5413414 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163070578 # DTB accesses +system.cpu.dcache.tagsinuse 4094.232018 # Cycle average of tags in use +system.cpu.dcache.total_refs 153756422 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126427000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 336082 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 53096224 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 870 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4174977 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 691367918 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 145684312 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123209609 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 10007520 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3007 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5427610 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163170180 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163012019 # DTB hits -system.cpu.dtb.data_misses 58559 # DTB misses +system.cpu.dtb.data_hits 163108618 # DTB hits +system.cpu.dtb.data_misses 61562 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122259759 # DTB read accesses +system.cpu.dtb.read_accesses 122378622 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122237048 # DTB read hits -system.cpu.dtb.read_misses 22711 # DTB read misses -system.cpu.dtb.write_accesses 40810819 # DTB write accesses +system.cpu.dtb.read_hits 122354151 # DTB read hits +system.cpu.dtb.read_misses 24471 # DTB read misses +system.cpu.dtb.write_accesses 40791558 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40774971 # DTB write hits -system.cpu.dtb.write_misses 35848 # DTB write misses -system.cpu.fetch.Branches 76440051 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65631744 # Number of cache lines fetched -system.cpu.fetch.Cycles 195845469 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1315609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 699070033 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4181068 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.228053 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65631744 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 65597112 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.085617 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 333428374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.096612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.077342 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 40754467 # DTB write hits +system.cpu.dtb.write_misses 37091 # DTB write misses +system.cpu.fetch.Branches 76519042 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65743933 # Number of cache lines fetched +system.cpu.fetch.Cycles 196171036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1323544 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 700543147 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4180854 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.225711 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65743933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 65741179 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.066420 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 337425275 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.076143 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.069329 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54714617 16.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 206998212 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10205574 3.02% 64.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 16013127 4.75% 69.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13976667 4.14% 73.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12062274 3.57% 76.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13987466 4.15% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5886424 1.74% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3487900 1.03% 83.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 54807631 16.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 333428374 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 65631744 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36217.817562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35518.743109 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65630571 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42483500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 337425275 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 65743933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36198.392555 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35509.868421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65742751 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42786500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1173 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32215500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1182 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32385000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 912 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 72360.056229 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 72086.349781 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65631744 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36217.817562 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency -system.cpu.icache.demand_hits 65630571 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42483500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65743933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36198.392555 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency +system.cpu.icache.demand_hits 65742751 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42786500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1173 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 266 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32215500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1182 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32385000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 912 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.378038 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 774.221896 # Average occupied blocks per context -system.cpu.icache.overall_accesses 65631744 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36217.817562 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.379446 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 777.105869 # Average occupied blocks per context +system.cpu.icache.overall_accesses 65743933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36198.392555 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65630571 # number of overall hits -system.cpu.icache.overall_miss_latency 42483500 # number of overall miss cycles +system.cpu.icache.overall_hits 65742751 # number of overall hits +system.cpu.icache.overall_miss_latency 42786500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1173 # number of overall misses -system.cpu.icache.overall_mshr_hits 266 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32215500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1182 # number of overall misses +system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32385000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 912 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 35 # number of replacements -system.cpu.icache.sampled_refs 907 # Sample count of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.sampled_refs 912 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 774.221896 # Cycle average of tags in use -system.cpu.icache.total_refs 65630571 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 777.105869 # Cycle average of tags in use +system.cpu.icache.total_refs 65742751 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1757798 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67441684 # Number of branches executed -system.cpu.iew.EXEC:nop 43298534 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.787674 # Inst execution rate -system.cpu.iew.EXEC:refs 164010690 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41206389 # Number of stores executed +system.cpu.idleCycles 1587719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67446690 # Number of branches executed +system.cpu.iew.EXEC:nop 43287555 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.768234 # Inst execution rate +system.cpu.iew.EXEC:refs 164109637 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41186586 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 488922033 # num instructions consuming a value -system.cpu.iew.WB:count 596002683 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.810520 # average fanout of values written-back +system.cpu.iew.WB:consumers 494218268 # num instructions consuming a value +system.cpu.iew.WB:count 596241723 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.805354 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 396281024 # num instructions producing a value -system.cpu.iew.WB:rate 1.778124 # insts written-back per cycle -system.cpu.iew.WB:sent 597106328 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4603784 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2069078 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126900612 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3145838 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43054897 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663551547 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122804301 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6319339 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599203767 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 4454 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 398020536 # num instructions producing a value +system.cpu.iew.WB:rate 1.758758 # insts written-back per cycle +system.cpu.iew.WB:sent 597367655 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4601660 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2251946 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 127252956 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3156398 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43259984 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 665052109 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122923051 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6371334 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599454333 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2449 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 32589 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9853353 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 86305 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 33854 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 10007520 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 83713 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 194 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8787843 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 12289 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 175 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 5470953 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10609 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 89737 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5921 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11851102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3242374 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 89737 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 943709 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3660075 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.687279 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.687279 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 93535 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5935 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 12203446 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3447461 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 93535 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 944573 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3657087 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.668232 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.668232 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 438810493 72.47% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6669 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.47% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124770612 20.61% 93.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 41935289 6.93% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 438988101 72.46% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6710 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124874272 20.61% 93.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956540 6.93% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605523106 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7132172 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 605825667 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 6927509 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011435 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5335622 74.81% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 49 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1469402 20.60% 95.41% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 327099 4.59% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5320205 76.80% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 51 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1245764 17.98% 94.78% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 361489 5.22% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 333428374 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.816052 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.661323 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 337425275 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.795437 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.663310 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 91844434 27.55% 27.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 66796624 20.03% 47.58% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 82026036 24.60% 72.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 37142853 11.14% 83.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 29318508 8.79% 92.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 13804488 4.14% 96.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 11015283 3.30% 99.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 983503 0.29% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 496645 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 95395357 28.27% 28.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 68329461 20.25% 48.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 80056631 23.73% 72.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 36910615 10.94% 83.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 31840128 9.44% 92.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 12299933 3.65% 96.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 10951663 3.25% 99.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1050952 0.31% 99.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 590535 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 333428374 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.806528 # Inst issue rate -system.cpu.iq.iqInstsAdded 620252984 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605523106 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53278148 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 39411 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29138505 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 337425275 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.787028 # Inst issue rate +system.cpu.iq.iqInstsAdded 621764526 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605825667 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 54809333 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 18475 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 31050369 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 65631783 # ITB accesses +system.cpu.itb.fetch_accesses 65743973 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 65631744 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.itb.fetch_hits 65743933 # ITB hits +system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,107 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 256875 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.188321 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.765450 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 8801356500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256875 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7998513500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256875 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 219110 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34284.038279 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31037.107304 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 183268 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1228808500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.163580 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35842 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1112432000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.163580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35842 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 81505 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34131.924422 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31025.814367 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2781922500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 256831 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.808951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.097625 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 12642 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 8367822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.950777 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 244189 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7606267000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950777 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 244189 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 219184 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34300.593807 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31016.018663 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 183819 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1213040500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.161348 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35365 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1096881500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.161348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35365 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 79334 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34139.271939 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31029.539668 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2708405000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 81505 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528759000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 79334 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2461697500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 81505 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 335213 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 335213 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5455.882353 # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 79334 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 336082 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 336082 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5312.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.750936 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 68 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 3.798768 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 371000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 382500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 475985 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.741313 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 183268 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10030165000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.614971 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292717 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 476015 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34271.956402 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 196461 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9580862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.587280 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 279554 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9110945500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.614971 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292717 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 8703148500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.587280 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 279554 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.051123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447698 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1675.210024 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14670.153699 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 475985 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.741313 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.052597 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.448200 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1723.488326 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14686.601231 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 476015 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34271.956402 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 183268 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10030165000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.614971 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292717 # number of overall misses +system.cpu.l2cache.overall_hits 196461 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9580862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.587280 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 279554 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9110945500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.614971 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292717 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 8703148500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.587280 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 279554 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 85307 # number of replacements -system.cpu.l2cache.sampled_refs 100934 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84626 # number of replacements +system.cpu.l2cache.sampled_refs 100342 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16345.363723 # Cycle average of tags in use -system.cpu.l2cache.total_refs 378597 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16410.089557 # Cycle average of tags in use +system.cpu.l2cache.total_refs 381176 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63240 # number of writebacks -system.cpu.memDep0.conflictingLoads 18950859 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15231969 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 126900612 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43054897 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 335186172 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14808263 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 62683 # number of writebacks +system.cpu.memDep0.conflictingLoads 23861424 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18454491 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 127252956 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43259984 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 339012994 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14846495 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 34154270 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151775927 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2034435 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 895748431 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680023810 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 518612424 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115460168 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9853353 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 41529646 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54757535 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 1017 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 36228613 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 153406470 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1884931 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 97 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 897942713 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 681539497 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 519842559 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115704820 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 10007520 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 43459223 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 55987670 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 747 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 80752072 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 87364721 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.timesIdled 42487 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 36935 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index fdd3515e5..850a6530b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -152,12 +152,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr index b2d79346c..67f69f09d 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index c1023446a..d9a9a6b92 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:27:06 -M5 executing on SC2B0619 -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:59:22 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -44,3 +46,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 777351681000 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 53f0d7951..c92f137ce 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1555765 # Simulator instruction rate (inst/s) -host_mem_usage 191800 # Number of bytes of host memory used -host_seconds 386.86 # Real time elapsed on the host -host_tick_rate 2011092592 # Simulator tick rate (ticks/s) +host_inst_rate 1386497 # Simulator instruction rate (inst/s) +host_mem_usage 206712 # Number of bytes of host memory used +host_seconds 434.08 # Real time elapsed on the host +host_tick_rate 1790782589 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.778004 # Number of seconds simulated -sim_ticks 778003833000 # Number of ticks simulated +sim_seconds 0.777352 # Number of seconds simulated +sim_ticks 777351681000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4227398000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3623702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39124493 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17781358000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008284 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 326828 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16800874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008284 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 326828 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses -system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 41678.513805 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153437303 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 22008756000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003430 # miss rate for demand accesses +system.cpu.dcache.demand_misses 528060 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 20424576000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003430 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 528060 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999559 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.195523 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999560 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.197079 # Average occupied blocks per context system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 41678.513805 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153435240 # number of overall hits -system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses -system.cpu.dcache.overall_misses 530123 # number of overall misses +system.cpu.dcache.overall_hits 153437303 # number of overall hits +system.cpu.dcache.overall_miss_latency 22008756000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003430 # miss rate for overall accesses +system.cpu.dcache.overall_misses 528060 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 20424576000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003430 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 528060 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.197079 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 325723 # number of writebacks +system.cpu.dcache.warmup_cycle 578599000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 325740 # number of writebacks system.cpu.dtb.data_accesses 153970296 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 153965363 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.328723 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 673.225223 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.328737 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 673.252668 # Average occupied blocks per context system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.252668 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,36 +164,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12405 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 12571416000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.951193 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 241758 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9670320000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.951193 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 241758 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 167657 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1787240000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.170126 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34370 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1374800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34370 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 72665 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3778580000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 72665 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2906600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 72665 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 325740 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325740 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.553777 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -202,44 +203,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 180062 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14358656000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.605292 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 276128 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11045120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.605292 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 276128 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050771 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447994 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1663.663316 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14679.879055 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.052155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.448358 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1709.012624 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14691.802112 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 167236 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 288954 # number of overall misses +system.cpu.l2cache.overall_hits 180062 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14358656000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.605292 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 276128 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11045120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.605292 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 276128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84513 # number of replacements -system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 83906 # number of replacements +system.cpu.l2cache.sampled_refs 99616 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use -system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16400.814735 # Cycle average of tags in use +system.cpu.l2cache.total_refs 354013 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63194 # number of writebacks +system.cpu.l2cache.writebacks 62672 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1556007666 # number of cpu cycles simulated +system.cpu.numCycles 1554703362 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index 86b7d82fa..4bef17201 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index b8e1d7eb2..b26d693cf 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2010 15:34:40 -M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase -M5 started Aug 24 2010 15:44:30 +M5 compiled Aug 26 2010 13:52:30 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:54:54 M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -43,4 +45,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 808121048000 because target called exit() +Exiting @ tick 807517408000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index bd7d26f79..4b4cf244a 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1674821 # Simulator instruction rate (inst/s) -host_mem_usage 210020 # Number of bytes of host memory used -host_seconds 357.42 # Real time elapsed on the host -host_tick_rate 2260963263 # Simulator tick rate (ticks/s) +host_inst_rate 1492183 # Simulator instruction rate (inst/s) +host_mem_usage 211112 # Number of bytes of host memory used +host_seconds 401.17 # Real time elapsed on the host +host_tick_rate 2012902303 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated -sim_seconds 0.808121 # Number of seconds simulated -sim_ticks 808121048000 # Number of ticks simulated +sim_seconds 0.807517 # Number of seconds simulated +sim_ticks 807517408000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21168.913260 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18168.913260 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4018770000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3449241000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 69110224 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17283504000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004446 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 308634 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16357602000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004446 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 308634 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42734.717951 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency -system.cpu.dcache.demand_hits 216713991 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21302274000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002295 # miss rate for demand accesses -system.cpu.dcache.demand_misses 498477 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency +system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses +system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19806843000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002295 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 498477 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999571 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.243213 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42734.717951 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 216713991 # number of overall hits -system.cpu.dcache.overall_miss_latency 21302274000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002295 # miss rate for overall accesses -system.cpu.dcache.overall_misses 498477 # number of overall misses +system.cpu.dcache.overall_hits 216715375 # number of overall hits +system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses +system.cpu.dcache.overall_misses 497093 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19806843000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002295 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 498477 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 433495 # number of replacements system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.243213 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 537993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 305427 # number of writebacks +system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 305501 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.282040 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 577.617873 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 577.617873 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,36 +150,37 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12882896000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247748 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9909920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247748 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 157466 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1717040000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173346 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33020 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1320800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173346 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33020 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 60886 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3166072000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 60886 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2435440000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 60886 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 305427 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 305427 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.359132 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -188,44 +189,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 157466 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14599936000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.640681 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 280768 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11230720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.640681 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 280768 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.049205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.452726 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1612.352730 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14834.915268 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 157466 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14599936000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.640681 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 280768 # number of overall misses +system.cpu.l2cache.overall_hits 170026 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 268208 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11230720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.640681 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 280768 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 81265 # number of replacements -system.cpu.l2cache.sampled_refs 96683 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 80841 # number of replacements +system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16447.267999 # Cycle average of tags in use -system.cpu.l2cache.total_refs 324771 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use +system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61092 # number of writebacks +system.cpu.l2cache.writebacks 60805 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1616242096 # number of cpu cycles simulated +system.cpu.numCycles 1615034816 # number of cpu cycles simulated system.cpu.num_insts 598619824 # Number of instructions executed system.cpu.num_refs 219174038 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index c00f7a514..659cb8ca7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -353,7 +353,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing +cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index ed5277c40..d11cb55dd 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,5 +1,5 @@ -Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr +Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jun 6 2010 04:01:36 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 04:02:01 +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:05:09 M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -45,4 +45,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1088715493000 because target called exit() +Exiting @ tick 1088441503500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 57777fec7..8e3cfada7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,209 +1,209 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109148 # Simulator instruction rate (inst/s) -host_mem_usage 208820 # Number of bytes of host memory used -host_seconds 12878.07 # Real time elapsed on the host -host_tick_rate 84540245 # Simulator tick rate (ticks/s) +host_inst_rate 76473 # Simulator instruction rate (inst/s) +host_mem_usage 212472 # Number of bytes of host memory used +host_seconds 18380.70 # Real time elapsed on the host +host_tick_rate 59216546 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618369 # Number of instructions simulated -sim_seconds 1.088715 # Number of seconds simulated -sim_ticks 1088715493000 # Number of ticks simulated +sim_seconds 1.088442 # Number of seconds simulated +sim_ticks 1088441503500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 173332559 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 194142411 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 173420048 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 194153919 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 81910123 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 251618660 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 251618660 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 81907161 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 251603669 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 251603669 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8014877 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8072747 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1942378796 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1941955406 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.767030 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.200667 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 1072972593 55.24% 55.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 568760584 29.28% 84.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 118179777 6.08% 90.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 122167717 6.29% 96.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 27965504 1.44% 98.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 8603273 0.44% 98.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11084471 0.57% 99.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 4630000 0.24% 99.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 1072656731 55.24% 55.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 568585470 29.28% 84.51% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 118066725 6.08% 90.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 122346784 6.30% 96.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 28028862 1.44% 98.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8610798 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 11084197 0.57% 99.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 4503092 0.23% 99.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 8072747 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1942378796 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1941955406 # Number of insts commited each cycle system.cpu.commit.COM:count 1489537512 # Number of instructions committed system.cpu.commit.COM:loads 402517247 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569375203 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 81910123 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 81907161 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1349352602 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1348785802 # The number of squashed insts skipped by commit system.cpu.committedInsts 1405618369 # Number of Instructions Simulated system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated -system.cpu.cpi 1.549091 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.549091 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 421562233 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14361.598866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6977.217093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 420657692 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12990655000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 904541 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 666380 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1661701000 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.548701 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.548701 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 421715823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14253.643501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6923.398779 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 420813257 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12864854000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002140 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 902566 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 664404 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1648890500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 238161 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 238162 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38025 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35025 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1521000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 1401000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 684500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 630500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37779.329951 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36098.948570 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164660283 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 82976518000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013163 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2196347 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1851198 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12459516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002069 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 345149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164663038 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 80123447685 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013147 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2193592 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1850133 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12044158308 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002058 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 343459 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1140.488307 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1140.778331 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 588418863 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30948.287394 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency -system.cpu.dcache.demand_hits 585317975 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 95967173000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005270 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3100888 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2517578 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14121217000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 583310 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 588572453 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30033.448450 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency +system.cpu.dcache.demand_hits 585476295 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 92988301685 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005260 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3096158 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2514537 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13693048808 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000988 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 581621 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.574437 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 588418863 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30948.287394 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4095.574913 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 588572453 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30033.448450 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 585317975 # number of overall hits -system.cpu.dcache.overall_miss_latency 95967173000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005270 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3100888 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2517578 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14121217000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 583310 # number of overall MSHR misses +system.cpu.dcache.overall_hits 585476295 # number of overall hits +system.cpu.dcache.overall_miss_latency 92988301685 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005260 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3096158 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2514537 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13693048808 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000988 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 581621 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 509323 # number of replacements -system.cpu.dcache.sampled_refs 513419 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 509328 # number of replacements +system.cpu.dcache.sampled_refs 513424 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.574437 # Cycle average of tags in use -system.cpu.dcache.total_refs 585548366 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 166128000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 341989 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 421912263 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3394284142 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 753420072 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 764076323 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 233540433 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2970138 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 251618660 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 350290492 # Number of cache lines fetched -system.cpu.fetch.Cycles 1175688320 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10057151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3685758924 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 87714492 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115558 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 350290492 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 173332559 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.692710 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 2175919229 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.574913 # Cycle average of tags in use +system.cpu.dcache.total_refs 585702974 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 165969000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 343309 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 421597556 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3393767574 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 753336946 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 764050676 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 233579864 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2970228 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 251603669 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 350205998 # Number of cache lines fetched +system.cpu.fetch.Cycles 1175621134 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10022642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3685217760 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 87763558 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115580 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 350205998 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 173420048 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692887 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 2175535270 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.844478 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1350120177 62.06% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 247723459 11.39% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 78876862 3.63% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36715633 1.69% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82505940 3.79% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 39095379 1.80% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30113044 1.38% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19663449 0.90% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 290721327 13.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2175919229 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 350290492 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33351.843100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.230992 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 350288376 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70572500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 2175535270 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 350205998 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33274.163131 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34791.817524 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 350203877 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70574500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2116 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 735 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 48060500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 2121 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 740 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 48047500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 253832.156522 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 253770.925362 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 350290492 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33351.843100 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency -system.cpu.icache.demand_hits 350288376 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70572500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 350205998 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33274.163131 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency +system.cpu.icache.demand_hits 350203877 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70574500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2116 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 735 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 48060500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 2121 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 740 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 48047500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.517203 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1059.231284 # Average occupied blocks per context -system.cpu.icache.overall_accesses 350290492 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33351.843100 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.517204 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1059.233334 # Average occupied blocks per context +system.cpu.icache.overall_accesses 350205998 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33274.163131 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 350288376 # number of overall hits -system.cpu.icache.overall_miss_latency 70572500 # number of overall miss cycles +system.cpu.icache.overall_hits 350203877 # number of overall hits +system.cpu.icache.overall_miss_latency 70574500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2116 # number of overall misses -system.cpu.icache.overall_mshr_hits 735 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 48060500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 2121 # number of overall misses +system.cpu.icache.overall_mshr_hits 740 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 48047500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -211,212 +211,213 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 223 # number of replacements system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1059.231284 # Cycle average of tags in use -system.cpu.icache.total_refs 350288376 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1059.233334 # Cycle average of tags in use +system.cpu.icache.total_refs 350203877 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1511758 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 126596313 # Number of branches executed -system.cpu.iew.EXEC:nop 341046394 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.865157 # Inst execution rate -system.cpu.iew.EXEC:refs 745176720 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207345254 # Number of stores executed +system.cpu.idleCycles 1347738 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 126526916 # Number of branches executed +system.cpu.iew.EXEC:nop 340982559 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.865733 # Inst execution rate +system.cpu.iew.EXEC:refs 746184493 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 208199925 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1478969218 # num instructions consuming a value -system.cpu.iew.WB:count 1850021692 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963149 # average fanout of values written-back +system.cpu.iew.WB:consumers 1479878942 # num instructions consuming a value +system.cpu.iew.WB:count 1850747692 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963175 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1424467072 # num instructions producing a value -system.cpu.iew.WB:rate 0.849635 # insts written-back per cycle -system.cpu.iew.WB:sent 1860023576 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 88314915 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3103548 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 732453281 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21345324 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 16485503 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 296886262 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2838946953 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 537831466 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 95847914 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1883819308 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 43195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1425382580 # num instructions producing a value +system.cpu.iew.WB:rate 0.850182 # insts written-back per cycle +system.cpu.iew.WB:sent 1860799390 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 88298258 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3065589 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 732363888 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21345183 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 16501703 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 296834010 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2838380214 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 537984568 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 98702938 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1884599663 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42681 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9926 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 233540433 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 76384 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 10075 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 233579864 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 76418 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 116246750 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 24118 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 3315 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 116246268 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24120 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6075012 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 6177679 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 329936034 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 130028306 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6075012 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2827686 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 85487229 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.645540 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.645540 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 329846641 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 129976054 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6177679 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2822462 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 85475796 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.645702 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.645702 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178571095 59.53% 59.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2996630 0.15% 59.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.69% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 570412087 28.81% 88.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 227687410 11.50% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178510091 59.42% 59.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2995561 0.15% 59.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 574193114 28.95% 88.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 227603835 11.48% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1979667222 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 5110932 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002582 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1983302601 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 6030045 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.003040 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 148685 2.91% 2.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 233686 4.57% 7.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4411963 86.32% 93.81% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 316598 6.19% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 148667 2.47% 2.47% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 233339 3.87% 6.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5333431 88.45% 94.78% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 314608 5.22% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 2175535270 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.911639 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.163576 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 1068255963 49.09% 49.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 579314637 26.62% 75.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 292421261 13.44% 89.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 161809686 7.44% 96.59% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 50369072 2.31% 98.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 14937591 0.69% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 7897011 0.36% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 777368 0.04% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 1067990413 49.09% 49.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 580044793 26.66% 75.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 292279315 13.43% 89.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 158370905 7.28% 96.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 51349615 2.36% 98.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 15864540 0.73% 99.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 8721161 0.40% 99.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 777887 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 136641 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 2175919229 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.909176 # Inst issue rate -system.cpu.iq.iqInstsAdded 2476265906 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1979667222 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21634653 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1050976502 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1545941 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19390982 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1261656908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 275258 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34298.440009 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.934352 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9440920000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 275258 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8578397500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 275258 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 239542 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34105.753589 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.482948 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 204503 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1195031500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.146275 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35039 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1086296000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35039 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 69939 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34214.100859 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.876206 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2392900000 # number of UpgradeReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::total 2175535270 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.911075 # Inst issue rate +system.cpu.iq.iqInstsAdded 2475761446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1983302601 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21636209 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1050320205 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 3387342 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19392538 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1256970263 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 275262 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34309.417551 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31170.249101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 11754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 9040806000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.957299 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 263508 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8213610000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.957299 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 263508 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 239543 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 204890 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1181858000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.144663 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34653 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1074330000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144663 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34653 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 68215 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2333844500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 69939 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2169639000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 68215 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2116155000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 69939 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 341989 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 341989 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 68215 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 343309 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 343309 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.064673 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.105608 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 514800 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34276.681695 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 204503 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10635951500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.602753 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 310297 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 514805 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34285.718119 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 216644 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10222664000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.579173 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 298161 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9664693500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.602753 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 310297 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9287940000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.579173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 298161 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.056082 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.444448 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1837.702550 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14563.687199 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 514800 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34276.681695 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.057090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.444973 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1870.709103 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14580.888860 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 514805 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34285.718119 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 204503 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10635951500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.602753 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 310297 # number of overall misses +system.cpu.l2cache.overall_hits 216644 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10222664000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.579173 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 298161 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9664693500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.602753 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 310297 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9287940000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.579173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 298161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84514 # number of replacements -system.cpu.l2cache.sampled_refs 99965 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 83969 # number of replacements +system.cpu.l2cache.sampled_refs 99434 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16401.389748 # Cycle average of tags in use -system.cpu.l2cache.total_refs 406325 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16451.597962 # Cycle average of tags in use +system.cpu.l2cache.total_refs 408237 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61949 # number of writebacks -system.cpu.memDep0.conflictingLoads 446168372 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144446189 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 732453281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 296886262 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 2177430987 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 18705831 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 61561 # number of writebacks +system.cpu.memDep0.conflictingLoads 445088392 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 142143895 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 732363888 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 296834010 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2176883008 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 18665128 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 818 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 29460 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 816810065 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 24399902 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4857699412 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3052479029 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2393152182 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 700108886 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 233540433 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 34052536 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1148372924 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 372701478 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21719371 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 176909620 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21553732 # count of temporary serializing insts renamed -system.cpu.timesIdled 44523 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:FullRegisterEvents 724 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 28925 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 816745640 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 24395596 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4856285750 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3051371057 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2392375919 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 700064958 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 233579864 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 34053219 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1147596661 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372426461 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21718962 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 176891245 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21553313 # count of temporary serializing insts renamed +system.cpu.timesIdled 41709 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 44b6cba58..9514e3ea7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -152,12 +152,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index be22dcc27..833f1cfc2 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:27:10 -M5 executing on SC2B0619 -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing +M5 compiled Aug 26 2010 13:03:41 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:04:04 +M5 executing on zizzer +command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -43,4 +45,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2076000877000 because target called exit() +Exiting @ tick 2075400743000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 89a25e955..736d779d0 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 933241 # Simulator instruction rate (inst/s) -host_mem_usage 193388 # Number of bytes of host memory used -host_seconds 1596.08 # Real time elapsed on the host -host_tick_rate 1300690172 # Simulator tick rate (ticks/s) +host_inst_rate 1385286 # Simulator instruction rate (inst/s) +host_mem_usage 211532 # Number of bytes of host memory used +host_seconds 1075.25 # Real time elapsed on the host +host_tick_rate 1930162951 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.076001 # Number of seconds simulated -sim_ticks 2076000877000 # Number of ticks simulated +sim_seconds 2.075401 # Number of seconds simulated +sim_ticks 2075400743000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. @@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses -system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses +system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.229973 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568846579 # number of overall hits -system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses -system.cpu.dcache.overall_misses 513081 # number of overall misses +system.cpu.dcache.overall_hits 568847975 # number of overall hits +system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000899 # miss rate for overall accesses +system.cpu.dcache.overall_misses 511685 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000899 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316424 # number of writebacks +system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 316439 # number of writebacks system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.442585 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 906.413760 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency @@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -142,36 +142,37 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 12877124000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.953422 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1737320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.448937 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -180,44 +181,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 160849 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 173281 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 14614444000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.618599 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 281047 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11739160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.645963 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 11241880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.618599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 281047 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052187 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447022 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1710.054315 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14648.032371 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.052996 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.447533 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1736.572582 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14664.762880 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 160849 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 293479 # number of overall misses +system.cpu.l2cache.overall_hits 173281 # number of overall hits +system.cpu.l2cache.overall_miss_latency 14614444000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.618599 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 281047 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11739160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.645963 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 293479 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 11241880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.618599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 281047 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82908 # number of replacements -system.cpu.l2cache.sampled_refs 98342 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 82461 # number of replacements +system.cpu.l2cache.sampled_refs 97909 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16358.086686 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16401.335462 # Cycle average of tags in use +system.cpu.l2cache.total_refs 337682 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61864 # number of writebacks +system.cpu.l2cache.writebacks 61551 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4152001754 # number of cpu cycles simulated +system.cpu.numCycles 4150801486 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 78cac28fc..1bbdb5a19 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -152,7 +152,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 0c109578a..5c6b0de63 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout +Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 2 2010 23:23:01 -M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch -M5 started May 2 2010 23:23:02 -M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing +M5 compiled Aug 26 2010 13:20:12 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 13:33:02 +M5 executing on zizzer +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +46,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1814725999000 because target called exit() +Exiting @ tick 1814105620000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index a907a8948..f79a1a362 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1830893 # Simulator instruction rate (inst/s) -host_mem_usage 225176 # Number of bytes of host memory used -host_seconds 884.47 # Real time elapsed on the host -host_tick_rate 2051770366 # Simulator tick rate (ticks/s) +host_inst_rate 1308474 # Simulator instruction rate (inst/s) +host_mem_usage 210192 # Number of bytes of host memory used +host_seconds 1237.60 # Real time elapsed on the host +host_tick_rate 1465826235 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366787 # Number of instructions simulated -sim_seconds 1.814726 # Number of seconds simulated -sim_ticks 1814725999000 # Number of ticks simulated +sim_seconds 1.814106 # Number of seconds simulated +sim_ticks 1814105620000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20886.624165 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17886.624165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4121474000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3529496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187876653 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17326624000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 309404 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16398412000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 309404 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 42326.481558 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606721452 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21448098000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses -system.cpu.dcache.demand_misses 506730 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 20826246000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses +system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19927908000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 506730 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.901606 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 42326.481558 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606721452 # number of overall hits -system.cpu.dcache.overall_miss_latency 21448098000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses -system.cpu.dcache.overall_misses 506730 # number of overall misses +system.cpu.dcache.overall_hits 606722925 # number of overall hits +system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses +system.cpu.dcache.overall_misses 505257 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19927908000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 506730 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.901606 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 779585000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 306191 # number of writebacks +system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 306200 # number of writebacks system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 660.164839 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 660.164839 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -132,36 +132,37 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 12725544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 244722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9788880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 244722 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 164971 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1720004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.167015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33077 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1323080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.167015 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33077 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 64682 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3363464000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 64682 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587280000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 64682 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 306191 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 306191 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.428492 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -170,44 +171,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 164971 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14445548000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.627412 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 277799 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11111960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.627412 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 277799 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052754 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.452175 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1728.633036 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14816.859075 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 164971 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14445548000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.627412 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 277799 # number of overall misses +system.cpu.l2cache.overall_hits 177813 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 264957 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11111960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.627412 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 277799 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 81557 # number of replacements -system.cpu.l2cache.sampled_refs 97073 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 81078 # number of replacements +system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16545.492111 # Cycle average of tags in use -system.cpu.l2cache.total_refs 332814 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use +system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61569 # number of writebacks +system.cpu.l2cache.writebacks 61253 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3629451998 # number of cpu cycles simulated +system.cpu.numCycles 3628211240 # number of cpu cycles simulated system.cpu.num_insts 1619366787 # Number of instructions executed system.cpu.num_refs 607228182 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |