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authorNilay Vaish <nilay@cs.wisc.edu>2012-01-28 19:09:17 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-01-28 19:09:17 -0600
commitf19b3f30b4fdbf464334f6a8c5b86210d675c9ec (patch)
treea39c3a31170866533531a00ecbe5624eb09fb786 /tests/long/00.gzip/ref
parent5c2fc35e029d8cd8e69e983e1baef6b86e47d64d (diff)
downloadgem5-f19b3f30b4fdbf464334f6a8c5b86210d675c9ec.tar.xz
X86 Regressions: Update stats due to introduction of TSO
Diffstat (limited to 'tests/long/00.gzip/ref')
-rw-r--r--tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini3
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/o3-timing/simout1036
-rw-r--r--tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt696
3 files changed, 358 insertions, 1377 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
index 42f7aa66f..6e971ebcf 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -80,6 +80,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=true
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -502,7 +503,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index 48ae315a0..bff73f5f1 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,1037 +1,15 @@
+Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:28:24
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 12:11:40
+gem5 started Jan 28 2012 12:12:43
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
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Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
@@ -1039,9 +17,11 @@ Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
+info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
+info: Increasing stack size by one page.
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -1062,4 +42,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 586294224000 because target called exit()
+Exiting @ tick 588785308000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 802bd6f5d..f7c59f027 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,155 +1,155 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.586294 # Number of seconds simulated
-sim_ticks 586294224000 # Number of ticks simulated
-final_tick 586294224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.588785 # Number of seconds simulated
+sim_ticks 588785308000 # Number of ticks simulated
+final_tick 588785308000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 145094 # Simulator instruction rate (inst/s)
-host_tick_rate 52462700 # Simulator tick rate (ticks/s)
-host_mem_usage 215548 # Number of bytes of host memory used
-host_seconds 11175.48 # Real time elapsed on the host
+host_inst_rate 112730 # Simulator instruction rate (inst/s)
+host_tick_rate 40933847 # Simulator tick rate (ticks/s)
+host_mem_usage 244824 # Number of bytes of host memory used
+host_seconds 14383.83 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated
-system.physmem.bytes_read 5880640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 56960 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 3744192 # Number of bytes written to this memory
-system.physmem.num_reads 91885 # Number of read requests responded to by this memory
-system.physmem.num_writes 58503 # Number of write requests responded to by this memory
+system.physmem.bytes_read 5878272 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 57216 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3742528 # Number of bytes written to this memory
+system.physmem.num_reads 91848 # Number of read requests responded to by this memory
+system.physmem.num_writes 58477 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 10030186 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 97153 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 6386200 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 16416386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 9983727 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 97176 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 6356354 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 16340082 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1172588449 # number of cpu cycles simulated
+system.cpu.numCycles 1177570617 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 142448982 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 142448982 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 134509888 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits
+system.cpu.BPredUnit.lookups 141882222 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 141882222 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 7459322 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 135523268 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 134664780 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1143761054 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 142448982 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 649541012 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 331 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 137027209 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 996742 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1172439660 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.784546 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.109877 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 141519405 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1135188232 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 141882222 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 134664780 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 328423216 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 56273795 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 658902879 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 302 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 135738609 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 998788 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1177479353 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.766783 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.096310 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 845244296 72.09% 72.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 17110181 1.46% 73.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 18043141 1.54% 75.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 16408368 1.40% 76.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 23340182 1.99% 78.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 16629602 1.42% 79.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 21855680 1.86% 81.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28257046 2.41% 84.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 185551164 15.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 852058955 72.36% 72.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 15948065 1.35% 73.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 17931063 1.52% 75.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 17495755 1.49% 76.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 23352779 1.98% 78.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 16626553 1.41% 80.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 22402886 1.90% 82.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28214099 2.40% 84.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 183449198 15.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1172439660 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.121483 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.975416 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 240695556 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 558473143 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 228947071 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 94774294 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 49549596 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2070409567 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 49549596 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 290323713 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 132525789 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 3175 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 256725592 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 443311795 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2043122328 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2031527322 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 4954653611 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4954649391 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1177479353 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.120487 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.964009 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 241266448 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 565597424 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 225300633 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 96681345 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 48633503 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2058834896 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 48633503 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 289994325 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 136667782 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 3607 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 255841310 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 446338826 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2031094400 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 199 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 278357951 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 133112570 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2019296537 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 4928551600 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 4928548640 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2960 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 413532672 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 91 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 148937436 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1986583516 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 218 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1781630004 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 670712329 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 168 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 401301887 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 93 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 797995614 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 517349896 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 226176362 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 355062669 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 148977960 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1979799927 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1779311117 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 175082 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 358154503 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 654941515 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 165 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1177479353 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.511119 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.319645 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 271921709 23.19% 23.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 416937499 35.56% 58.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 21203892 1.81% 98.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 14378982 1.23% 99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1804798 0.15% 99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 305352 0.03% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 271443176 23.05% 23.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 420511572 35.71% 58.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 239784716 20.36% 79.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 159545639 13.55% 92.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 48751983 4.14% 96.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 21481111 1.82% 98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 13897994 1.18% 99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1713551 0.15% 99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 349611 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1172439660 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1177479353 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 179772 6.92% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2269895 87.35% 94.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 183781 6.86% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2344413 87.49% 94.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 151333 5.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1102052869 61.86% 63.37% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 26390474 1.48% 1.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1101178190 61.89% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued
@@ -178,85 +178,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 457060255 25.69% 89.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 194682198 10.94% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1781630004 # Type of FU issued
-system.cpu.iq.rate 1.519399 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4738479063 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1760053765 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 1779311117 # Type of FU issued
+system.cpu.iq.rate 1.511002 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2679527 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001506 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4738956161 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2338163322 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1758678242 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 458 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1757334381 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 1755600151 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 207757708 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 100048507 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 60622 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 216417 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 38622350 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 98307771 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 75876 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 215687 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 37990305 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 849 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 34395 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1126 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 49549596 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1308890 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 133908 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1986583734 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 659432 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 519090632 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 226808407 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 64911 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 216417 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1768232808 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 48633503 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1923683 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 157688 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1979800142 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 665872 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 517349896 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 226176362 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 85 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 70768 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 44 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 215687 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4604749 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3040457 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7645206 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1766024784 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 346724877 30.88% 30.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 438665808 39.07% 69.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 94902960 8.45% 78.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 133728922 11.91% 90.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 36854784 3.28% 93.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 26115374 2.33% 95.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 22565758 2.01% 97.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8207714 0.73% 98.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 15123867 1.35% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 347283519 30.76% 30.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 441725058 39.13% 69.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 99623372 8.83% 78.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 136537223 12.10% 90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 31770740 2.81% 93.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 26056867 2.31% 95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 22501724 1.99% 97.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 8245904 0.73% 98.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 15101443 1.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1122890064 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1128845850 # Number of insts commited each cycle
system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed
@@ -266,48 +266,48 @@ system.cpu.commit.branches 107161579 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 15123867 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 15101443 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3094363491 # The number of ROB reads
-system.cpu.rob.rob_writes 4022764791 # The number of ROB writes
-system.cpu.timesIdled 43542 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 148789 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3093547157 # The number of ROB reads
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+system.cpu.timesIdled 21053 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 91264 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
-system.cpu.cpi 0.723153 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.723153 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads
-system.cpu.int_regfile_writes 1756091292 # number of integer regfile writes
+system.cpu.cpi 0.726226 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.726226 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.376982 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.376982 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3270153545 # number of integer regfile reads
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system.cpu.fp_regfile_reads 12 # number of floating regfile reads
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+system.cpu.misc_regfile_reads 907833056 # number of misc regfile reads
system.cpu.icache.replacements 12 # number of replacements
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-system.cpu.icache.avg_refs 153444.543113 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.ReadReq_misses 1232 # number of ReadReq misses
-system.cpu.icache.demand_misses 1232 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 1232 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 43328500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35169.237013 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35169.237013 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35169.237013 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency 35293.300654 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -317,159 +317,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 73618 # number of replacements
-system.cpu.l2cache.tagsinuse 17964.500601 # Cycle average of tags in use
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1976.098849 # Average occupied blocks per context
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions