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authorSteve Reinhardt <stever@gmail.com>2008-03-17 23:07:22 -0400
committerSteve Reinhardt <stever@gmail.com>2008-03-17 23:07:22 -0400
commit3de8a78a04b1d1c5e901f3613b6247da9cf00a9c (patch)
tree8a45228bb814642fe4c6070e19202df4fd16a4f9 /tests/long/00.gzip/ref
parentb051ae6acc5a4e98ba60478f42ba2a2b92cb5ff1 (diff)
downloadgem5-3de8a78a04b1d1c5e901f3613b6247da9cf00a9c.tar.xz
Update long regression stats for semi-recent cache changes.
--HG-- extra : convert_revision : 7fef1e4f684ced37479ed363ebbb3a7485bc0d52
Diffstat (limited to 'tests/long/00.gzip/ref')
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini1
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt76
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr2
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini1
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt70
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout6
6 files changed, 79 insertions, 77 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 60a97b97b..595b91bdc 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
output=cout
pid=100
ppid=99
+simpoint=0
system=system
uid=100
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
index 04959f23f..ca33458cb 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4205990 # Nu
global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted
global.BPredUnit.lookups 76112488 # Number of BP lookups
global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target.
-host_inst_rate 185893 # Simulator instruction rate (inst/s)
-host_mem_usage 223968 # Number of bytes of host memory used
-host_seconds 3042.35 # Real time elapsed on the host
-host_tick_rate 54375513 # Simulator tick rate (ticks/s)
+host_inst_rate 131337 # Simulator instruction rate (inst/s)
+host_mem_usage 179084 # Number of bytes of host memory used
+host_seconds 4306.11 # Real time elapsed on the host
+host_tick_rate 38417331 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit.
@@ -53,61 +53,61 @@ system.cpu.cpi 0.585019 # CP
system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 114321557 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 26993.890628 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses 115038352 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 6257.587595 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001892 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 216307 # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate 0.008111 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 933102 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001892 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001880 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 37579282 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 48790.597140 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 7448.640662 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.008975 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 337288 # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate 0.056001 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2209327 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.008975 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 320.196392 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 321.245700 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 151900839 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 40273.937496 # average overall miss latency
+system.cpu.dcache.demand_accesses 154489673 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 7094.973483 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003644 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 553595 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate 0.020341 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3142429 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003644 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.003583 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 151900839 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 40273.937496 # average overall miss latency
+system.cpu.dcache.overall_accesses 154489673 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 7094.973483 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 151347244 # number of overall hits
system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003644 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 553595 # number of overall misses
+system.cpu.dcache.overall_miss_rate 0.020341 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3142429 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003644 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.003583 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -124,7 +124,7 @@ system.cpu.dcache.replacements 468826 # nu
system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use
-system.cpu.dcache.total_refs 151427918 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 151924159 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 334126 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked
@@ -173,13 +173,13 @@ system.cpu.fetch.rateDist.min_value 0
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 66025546 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 10641.352550 # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses 66025670 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 9355.263158 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses
+system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1026 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
@@ -192,13 +192,13 @@ system.cpu.icache.blocked_no_targets 0 # nu
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 66025546 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 10641.352550 # average overall miss latency
+system.cpu.icache.demand_accesses 66025670 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 9355.263158 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
-system.cpu.icache.demand_misses 902 # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1026 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
@@ -206,14 +206,14 @@ system.cpu.icache.demand_mshr_misses 902 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 66025546 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 10641.352550 # average overall miss latency
+system.cpu.icache.overall_accesses 66025670 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 9355.263158 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 66024644 # number of overall hits
system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
-system.cpu.icache.overall_misses 902 # number of overall misses
+system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1026 # number of overall misses
system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
index 598fc86c0..8053728f7 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr
@@ -1,3 +1,3 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7006
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 857d77efe..4e87924ca 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -376,6 +376,7 @@ max_stack_size=67108864
output=cout
pid=100
ppid=99
+simpoint=0
system=system
uid=100
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
index a32e8681e..623095a72 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
@@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 84375502 # Nu
global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted
global.BPredUnit.lookups 253548806 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 116576 # Simulator instruction rate (inst/s)
-host_mem_usage 226608 # Number of bytes of host memory used
-host_seconds 12057.44 # Real time elapsed on the host
-host_tick_rate 91455071 # Simulator tick rate (ticks/s)
+host_inst_rate 60603 # Simulator instruction rate (inst/s)
+host_mem_usage 181372 # Number of bytes of host memory used
+host_seconds 23193.76 # Real time elapsed on the host
+host_tick_rate 47543564 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit.
@@ -51,16 +51,16 @@ system.cpu.committedInsts 1405610550 # Nu
system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 430903803 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_accesses 431513840 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5832.966573 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000527 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses
+system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 837060 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000527 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency
@@ -72,50 +72,50 @@ system.cpu.dcache.SwapReq_misses 40 # nu
system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 165064291 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_accesses 166856456 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 10313.606533 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 341979 # number of WriteReq misses
+system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2134144 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002050 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1192.736607 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1192.980326 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 595968094 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 47263.919107 # average overall miss latency
+system.cpu.dcache.demand_accesses 598370296 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 9051.301930 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency
system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000955 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 569002 # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate 0.004965 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2971204 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000955 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 595968094 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 47263.919107 # average overall miss latency
+system.cpu.dcache.overall_accesses 598370296 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 9051.301930 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 595399092 # number of overall hits
system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000955 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 569002 # number of overall misses
+system.cpu.dcache.overall_miss_rate 0.004965 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2971204 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000955 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@@ -132,7 +132,7 @@ system.cpu.dcache.replacements 495151 # nu
system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use
-system.cpu.dcache.total_refs 595470173 # Total number of references to valid blocks.
+system.cpu.dcache.total_refs 595591849 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 338813 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked
@@ -166,13 +166,13 @@ system.cpu.fetch.rateDist.min_value 0
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 356679310 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 9956.762749 # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses 356679455 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 8992.990654 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses 1498 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
@@ -185,13 +185,13 @@ system.cpu.icache.blocked_no_targets 0 # nu
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 356679310 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 9956.762749 # average overall miss latency
+system.cpu.icache.demand_accesses 356679455 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 8992.990654 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency
system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses
+system.cpu.icache.demand_misses 1498 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
@@ -199,14 +199,14 @@ system.cpu.icache.demand_mshr_misses 1353 # nu
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 356679310 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 9956.762749 # average overall miss latency
+system.cpu.icache.overall_accesses 356679455 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 8992.990654 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 356677957 # number of overall hits
system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1353 # number of overall misses
+system.cpu.icache.overall_misses 1498 # number of overall misses
system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
index 8ee292d5b..d3d1e3cfb 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
@@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2008 13:27:50
-M5 started Mon Feb 25 16:16:45 2008
-M5 executing on tater
+M5 compiled Mar 17 2008 06:14:16
+M5 started Mon Mar 17 06:14:18 2008
+M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1102714100000 because target called exit()