summaryrefslogtreecommitdiff
path: root/tests/long/00.gzip/ref
diff options
context:
space:
mode:
authorNathan Binkert <nate@binkert.org>2009-04-08 22:21:30 -0700
committerNathan Binkert <nate@binkert.org>2009-04-08 22:21:30 -0700
commit374ba9bae359e68c1496f8db25c38a817af2da19 (patch)
tree48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/long/00.gzip/ref
parente0de2c34433be76eac7798e58e1ae02f5bffb732 (diff)
downloadgem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz
tests: update tests for TLB unification
Diffstat (limited to 'tests/long/00.gzip/ref')
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt40
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout10
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt40
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt40
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt8
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-atomic/simout10
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-atomic/simout10
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini4
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-timing/simout10
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt8
24 files changed, 157 insertions, 109 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 068fb2315..b2e89e8ab 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 0988daaa5..635bbafa8 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:15:58
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:37:48
M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index b3f903358..ace5a05aa 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 309694 # Simulator instruction rate (inst/s)
-host_mem_usage 206028 # Number of bytes of host memory used
-host_seconds 1826.17 # Real time elapsed on the host
-host_tick_rate 91491135 # Simulator tick rate (ticks/s)
+host_inst_rate 312901 # Simulator instruction rate (inst/s)
+host_mem_usage 206004 # Number of bytes of host memory used
+host_seconds 1807.45 # Real time elapsed on the host
+host_tick_rate 92438667 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.167078 # Number of seconds simulated
@@ -123,10 +123,14 @@ system.cpu.decode.DECODE:RunCycles 123896058 # Nu
system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
-system.cpu.dtb.accesses 163077390 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 163013880 # DTB hits
-system.cpu.dtb.misses 63510 # DTB misses
+system.cpu.dtb.data_accesses 163077390 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 163013880 # DTB hits
+system.cpu.dtb.data_misses 63510 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 122284109 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 122260496 # DTB read hits
@@ -319,10 +323,22 @@ system.cpu.iq.iqSquashedInstsExamined 53519286 # Nu
system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 66014446 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 66014406 # ITB hits
-system.cpu.itb.misses 40 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 66014446 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 66014406 # ITB hits
+system.cpu.itb.fetch_misses 40 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 53e8ae1eb..af1fb07c3 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.tracer]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 2a4b52a28..512d13649 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py long/00.gzip/alpha/tru64/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:34:49
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index d5f13f08c..aa16ad6b4 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 6175770 # Simulator instruction rate (inst/s)
-host_mem_usage 195684 # Number of bytes of host memory used
-host_seconds 97.45 # Real time elapsed on the host
-host_tick_rate 3087904278 # Simulator tick rate (ticks/s)
+host_inst_rate 5975527 # Simulator instruction rate (inst/s)
+host_mem_usage 197448 # Number of bytes of host memory used
+host_seconds 100.72 # Real time elapsed on the host
+host_tick_rate 2987780856 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300930958000 # Number of ticks simulated
-system.cpu.dtb.accesses 153970296 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 153965363 # DTB hits
-system.cpu.dtb.misses 4933 # DTB misses
+system.cpu.dtb.data_accesses 153970296 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 153965363 # DTB hits
+system.cpu.dtb.data_misses 4933 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
@@ -21,10 +25,22 @@ system.cpu.dtb.write_acv 0 # DT
system.cpu.dtb.write_hits 39451321 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 601861917 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 601861897 # ITB hits
-system.cpu.itb.misses 20 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 601861917 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 601861897 # ITB hits
+system.cpu.itb.fetch_misses 20 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 6d294469b..b0f992d6d 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 8b3b6bb5d..20994514f 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py long/00.gzip/alpha/tru64/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:34:42
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 57d9b05f8..d4bd93848 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1969135 # Simulator instruction rate (inst/s)
-host_mem_usage 203124 # Number of bytes of host memory used
-host_seconds 305.65 # Real time elapsed on the host
-host_tick_rate 2545444210 # Simulator tick rate (ticks/s)
+host_inst_rate 3011769 # Simulator instruction rate (inst/s)
+host_mem_usage 204988 # Number of bytes of host memory used
+host_seconds 199.84 # Real time elapsed on the host
+host_tick_rate 3893225431 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated
@@ -71,10 +71,14 @@ system.cpu.dcache.tagsinuse 4094.195523 # Cy
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks
-system.cpu.dtb.accesses 153970296 # DTB accesses
-system.cpu.dtb.acv 0 # DTB access violations
-system.cpu.dtb.hits 153965363 # DTB hits
-system.cpu.dtb.misses 4933 # DTB misses
+system.cpu.dtb.data_accesses 153970296 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 153965363 # DTB hits
+system.cpu.dtb.data_misses 4933 # DTB misses
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 114516673 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_hits 114514042 # DTB read hits
@@ -137,10 +141,22 @@ system.cpu.icache.total_refs 601861103 # To
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 601861918 # ITB accesses
-system.cpu.itb.acv 0 # ITB acv
-system.cpu.itb.hits 601861898 # ITB hits
-system.cpu.itb.misses 20 # ITB misses
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.fetch_accesses 601861918 # ITB accesses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_hits 601861898 # ITB hits
+system.cpu.itb.fetch_misses 20 # ITB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index ee1f88977..35d154fac 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -132,7 +132,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index 293987f44..f6e5574f7 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:30:04
+M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 3e5a615cf..c367ac34c 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 159348 # Simulator instruction rate (inst/s)
-host_mem_usage 206344 # Number of bytes of host memory used
-host_seconds 8821.04 # Real time elapsed on the host
-host_tick_rate 125003315 # Simulator tick rate (ticks/s)
+host_inst_rate 150366 # Simulator instruction rate (inst/s)
+host_mem_usage 208016 # Number of bytes of host memory used
+host_seconds 9347.96 # Real time elapsed on the host
+host_tick_rate 117957212 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618365 # Number of instructions simulated
sim_seconds 1.102659 # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 8d0eebe28..92041a7ce 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.tracer]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index d1dad3acf..2a36b7985 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:46:25
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:31:00
+M5 executing on maize
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index d5f28736a..077429fb4 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 3714547 # Simulator instruction rate (inst/s)
-host_mem_usage 197792 # Number of bytes of host memory used
-host_seconds 401.00 # Real time elapsed on the host
-host_tick_rate 1857278454 # Simulator tick rate (ticks/s)
+host_inst_rate 3659022 # Simulator instruction rate (inst/s)
+host_mem_usage 199544 # Number of bytes of host memory used
+host_seconds 407.08 # Real time elapsed on the host
+host_tick_rate 1829515892 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 90217b2a5..7de5a10fa 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=SparcDTB
+type=SparcTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=SparcITB
+type=SparcTLB
size=64
[system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index d75186ab5..73072ad1d 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Mar 16 2009 00:51:12
-M5 revision 208de84f046d 6013 default tip
-M5 started Mar 16 2009 00:51:29
-M5 executing on zizzer
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:32:24
+M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 8851d2d2a..f480451f2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1328193 # Simulator instruction rate (inst/s)
-host_mem_usage 205396 # Number of bytes of host memory used
-host_seconds 1121.47 # Real time elapsed on the host
-host_tick_rate 1851148785 # Simulator tick rate (ticks/s)
+host_inst_rate 1898996 # Simulator instruction rate (inst/s)
+host_mem_usage 207084 # Number of bytes of host memory used
+host_seconds 784.37 # Real time elapsed on the host
+host_tick_rate 2646697045 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.076001 # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 1f354a5d6..8edc68d8c 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -39,11 +39,11 @@ dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=X86DTB
+type=X86TLB
size=64
[system.cpu.itb]
-type=X86ITB
+type=X86TLB
size=64
[system.cpu.tracer]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 875533d57..a87cf6c93 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2009 22:05:32
-M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch
-M5 started Feb 24 2009 22:07:57
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:59:49
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index 0158d9e3d..d6c1760ba 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1045935 # Simulator instruction rate (inst/s)
-host_mem_usage 197296 # Number of bytes of host memory used
-host_seconds 1548.25 # Real time elapsed on the host
-host_tick_rate 621947296 # Simulator tick rate (ticks/s)
+host_inst_rate 2819266 # Simulator instruction rate (inst/s)
+host_mem_usage 199720 # Number of bytes of host memory used
+host_seconds 574.39 # Real time elapsed on the host
+host_tick_rate 1676428354 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 0.962929 # Number of seconds simulated
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 1e457c793..3764c63b0 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=X86DTB
+type=X86TLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=X86ITB
+type=X86TLB
size=64
[system.cpu.l2cache]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 4f608c9b1..d1ddd37b9 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2009 22:05:32
-M5 revision dda4746d9215 5940 default qtip tip rtcbcd.patch
-M5 started Feb 24 2009 22:07:57
-M5 executing on tater
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 13:09:59
+M5 executing on maize
+command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index b764de67a..2cd851868 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 660241 # Simulator instruction rate (inst/s)
-host_mem_usage 204740 # Number of bytes of host memory used
-host_seconds 2452.69 # Real time elapsed on the host
-host_tick_rate 739961389 # Simulator tick rate (ticks/s)
+host_inst_rate 1747793 # Simulator instruction rate (inst/s)
+host_mem_usage 207260 # Number of bytes of host memory used
+host_seconds 926.52 # Real time elapsed on the host
+host_tick_rate 1958830620 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 1.814897 # Number of seconds simulated