diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-23 10:59:13 -0500 |
| commit | 5d5b0f49cc125973fb7048ad86bf85ab5ed57772 (patch) | |
| tree | 0840a5055d8d8103eb22bcbe1ad90498e3db8aee /tests/long/00.gzip/ref | |
| parent | d0b0a555151232566550c837f9d4d061bf3d4686 (diff) | |
| download | gem5-5d5b0f49cc125973fb7048ad86bf85ab5ed57772.tar.xz | |
Stats: Update stats for minor O3 changes below.
Diffstat (limited to 'tests/long/00.gzip/ref')
| -rwxr-xr-x | tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 996 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 842 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 10 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 826 |
6 files changed, 1348 insertions, 1344 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index df78a3a5d..7084f92e2 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 4 2011 13:56:47 -M5 started May 4 2011 13:57:03 -M5 executing on nadc-0364 +M5 compiled May 16 2011 15:11:25 +M5 started May 16 2011 16:32:58 +M5 executing on nadc-0271 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 189747670000 because target called exit() +Exiting @ tick 189745250000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index b2bd08a2b..1e34e6b02 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,530 +1,530 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 210962 # Simulator instruction rate (inst/s) -host_mem_usage 262196 # Number of bytes of host memory used -host_seconds 2855.31 # Real time elapsed on the host -host_tick_rate 66454392 # Simulator tick rate (ticks/s) +sim_seconds 0.189745 # Number of seconds simulated +sim_ticks 189745250000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 602359850 # Number of instructions simulated -sim_seconds 0.189748 # Number of seconds simulated -sim_ticks 189747670000 # Number of ticks simulated -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 74615208 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 80130233 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1670 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3884107 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 80516162 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 86913734 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1397693 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 3943213 # The number of times a branch was mispredicted -system.cpu.commit.branches 70828611 # Number of branches committed -system.cpu.commit.bw_lim_events 15126616 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 602359901 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 6307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 75686006 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 366955970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.641505 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.022822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118814632 32.38% 32.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 123407521 33.63% 66.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52313499 14.26% 80.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12481991 3.40% 83.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20938472 5.71% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13691845 3.73% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7616390 2.08% 95.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2565004 0.70% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15126616 4.12% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366955970 # Number of insts commited each cycle -system.cpu.commit.count 602359901 # Number of instructions committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.int_insts 533522679 # Number of committed integer instructions. -system.cpu.commit.loads 148952604 # Number of loads committed -system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.refs 219173627 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 602359850 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359850 # Number of Instructions Simulated -system.cpu.cpi 0.630014 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630014 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1349 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 1334 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.011119 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 138720806 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13339.905680 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8226.668223 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 138476956 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3252936000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001758 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 243850 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 46844 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1620703000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197006 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 1337 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 1337 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17857.107875 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.095668 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 67921343 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26717590518 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.021553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1496188 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1248875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2561939027 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247313 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 464.535408 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 208138337 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17224.064370 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9413.601550 # average overall mshr miss latency -system.cpu.dcache.demand_hits 206398299 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29970526518 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1740038 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1295719 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4182642027 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 444319 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4094.816119 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 208138337 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17224.064370 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9413.601550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 206398299 # number of overall hits -system.cpu.dcache.overall_miss_latency 29970526518 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1740038 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1295719 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4182642027 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 444319 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 440221 # number of replacements -system.cpu.dcache.sampled_refs 444317 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.816119 # Cycle average of tags in use -system.cpu.dcache.total_refs 206400979 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88948000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 394697 # number of writebacks -system.cpu.decode.BlockedCycles 57854165 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 1286 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 5859491 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 711052352 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 160285716 # Number of cycles decode is idle -system.cpu.decode.RunCycles 140722772 # Number of cycles decode is running -system.cpu.decode.SquashCycles 11629973 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 4744 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 8093316 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses +host_inst_rate 57706 # Simulator instruction rate (inst/s) +host_tick_rate 18177630 # Simulator tick rate (ticks/s) +host_mem_usage 255472 # Number of bytes of host memory used +host_seconds 10438.39 # Real time elapsed on the host +sim_insts 602359840 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 86913734 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 70195415 # Number of cache lines fetched -system.cpu.fetch.Cycles 151344798 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 922649 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 678928974 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4471477 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.229025 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 70195415 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 76012901 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.789031 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 378585942 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.910009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.919514 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 379490501 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 86928352 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80528545 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3884028 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 80092626 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 74490175 # Number of BTB hits +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.usedRAS 1400314 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1695 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 70199329 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 678993278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86928352 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 75890489 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151223447 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473449 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 70199329 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 924096 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 378585601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.910199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.920341 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 227241307 60.02% 60.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25123172 6.64% 66.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17643544 4.66% 71.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 21901113 5.78% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11234102 2.97% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11763660 3.11% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4451384 1.18% 84.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7295384 1.93% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 51932276 13.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 227362317 60.06% 60.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25157685 6.65% 66.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17486331 4.62% 71.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 21712752 5.74% 77.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11244311 2.97% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11955687 3.16% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4446495 1.17% 84.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7289466 1.93% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 51930557 13.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 378585942 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 378585601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.229066 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.789223 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 160153181 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 58093543 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 140600980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8092430 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11645467 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 5860940 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1284 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 711110342 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4730 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11645467 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 169808793 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7731895 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 102804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 138994558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50302084 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 699378515 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 44454073 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4930432 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723286205 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3254558347 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3254558219 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 627417450 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 95868750 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6063 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6060 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 83251971 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172882787 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80813690 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 15992884 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23084405 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 678074240 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7046 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 648954836 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 321485 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 74818706 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 185294154 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 741 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 378585601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.714156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.635088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99002495 26.15% 26.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 107489876 28.39% 54.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72418873 19.13% 73.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 48797355 12.89% 86.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 22456398 5.93% 92.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17049752 4.50% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6015477 1.59% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3775065 1.00% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1580310 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 378585601 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164864 5.19% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2380738 74.98% 80.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 629773 19.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 405017368 62.41% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6545 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 167786137 25.85% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76144783 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 648954836 # Type of FU issued +system.cpu.iq.rate 1.710069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3175375 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004893 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1679992097 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 753424475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 636613588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 652130191 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25625639 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 23930184 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 271058 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 524844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10592669 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 15888 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 11645467 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 694588 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38667 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 678142321 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3267373 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172882787 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80813690 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5710 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3854 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 524844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3752039 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 638545 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4390584 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642328929 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 165615332 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6625907 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 61035 # number of nop insts executed +system.cpu.iew.exec_refs 240294143 # number of memory reference insts executed +system.cpu.iew.exec_branches 74636278 # Number of branches executed +system.cpu.iew.exec_stores 74678811 # Number of stores executed +system.cpu.iew.exec_rate 1.692609 # Inst execution rate +system.cpu.iew.wb_sent 637663585 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 636613604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 410591202 # num instructions producing a value +system.cpu.iew.wb_consumers 620919251 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.677548 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661263 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 602359891 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 75781554 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6305 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3943142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366940135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.641575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.021399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118738354 32.36% 32.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 123466865 33.65% 66.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52180899 14.22% 80.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12560554 3.42% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20975428 5.72% 89.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13806386 3.76% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7633759 2.08% 95.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2509750 0.68% 95.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15068140 4.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366940135 # Number of insts commited each cycle +system.cpu.commit.count 602359891 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 219173623 # Number of memory references committed +system.cpu.commit.loads 148952602 # Number of loads committed +system.cpu.commit.membars 1328 # Number of memory barriers committed +system.cpu.commit.branches 70828609 # Number of branches committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.int_insts 533522671 # Number of committed integer instructions. +system.cpu.commit.function_calls 997573 # Number of function calls committed. +system.cpu.commit.bw_lim_events 15068140 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 1030012828 # The number of ROB reads +system.cpu.rob.rob_writes 1367937117 # The number of ROB writes +system.cpu.timesIdled 36799 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 904900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359840 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359840 # Number of Instructions Simulated +system.cpu.cpi 0.630006 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.630006 # CPI: Total CPI of All Threads +system.cpu.ipc 1.587286 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.587286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3206207435 # number of integer regfile reads +system.cpu.int_regfile_writes 661050575 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 70195415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35447.995666 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34312.158470 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 70194492 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32718500 # number of ReadReq miss cycles +system.cpu.misc_regfile_reads 912573919 # number of misc regfile reads +system.cpu.misc_regfile_writes 2672 # number of misc regfile writes +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 627.011637 # Cycle average of tags in use +system.cpu.icache.total_refs 70198409 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 96294.113855 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 627.011637 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.306158 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 70198409 # number of ReadReq hits +system.cpu.icache.demand_hits 70198409 # number of demand (read+write) hits +system.cpu.icache.overall_hits 70198409 # number of overall hits +system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses +system.cpu.icache.demand_misses 920 # number of demand (read+write) misses +system.cpu.icache.overall_misses 920 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32585000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32585000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32585000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 70199329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 70199329 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 70199329 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 923 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 191 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25116500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 732 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 96156.838356 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35418.478261 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35418.478261 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35418.478261 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 70195415 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35447.995666 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34312.158470 # average overall mshr miss latency -system.cpu.icache.demand_hits 70194492 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32718500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 923 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 191 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25116500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 731 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 731 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 731 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 25045500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25045500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25045500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 732 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 626.402984 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.305861 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 70195415 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35447.995666 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34312.158470 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 70194492 # number of overall hits -system.cpu.icache.overall_miss_latency 32718500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 923 # number of overall misses -system.cpu.icache.overall_mshr_hits 191 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25116500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 732 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 43 # number of replacements -system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34261.969904 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 626.402984 # Cycle average of tags in use -system.cpu.icache.total_refs 70194492 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 909399 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 4390377 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 74630961 # Number of branches executed -system.cpu.iew.exec_nop 61033 # number of nop insts executed -system.cpu.iew.exec_rate 1.692381 # Inst execution rate -system.cpu.iew.exec_refs 240248450 # number of memory reference insts executed -system.cpu.iew.exec_stores 74641760 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 692845 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 172870468 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5721 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3255991 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 80793372 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 678046798 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 165606690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6567715 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 642250536 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 7466 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3846 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 11629973 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 38806 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 12320 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 25624582 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 272347 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 522665 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 15873 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 23917863 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 10572349 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 522665 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 636797 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3753580 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 620419783 # num instructions consuming a value -system.cpu.iew.wb_count 636524370 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.661688 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 410524106 # num instructions producing a value -system.cpu.iew.wb_rate 1.677292 # insts written-back per cycle -system.cpu.iew.wb_sent 637578270 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 3205843747 # number of integer regfile reads -system.cpu.int_regfile_writes 660980878 # number of integer regfile writes -system.cpu.ipc 1.587265 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.587265 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 404976250 62.42% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6544 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 167780307 25.86% 88.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76055147 11.72% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 648818251 # Type of FU issued -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 3420971 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005273 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164650 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2528736 73.92% 78.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 727585 21.27% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 652239202 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1679971887 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 636524354 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 753225503 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 677978706 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 648818251 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7059 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 74717328 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 328508 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 752 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 185330852 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 378585942 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.713794 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.641678 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99098284 26.18% 26.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 107923682 28.51% 54.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 72401438 19.12% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 48461841 12.80% 86.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21953161 5.80% 92.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16842853 4.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6368110 1.68% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3821983 1.01% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1714590 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 378585942 # Number of insts issued each cycle -system.cpu.iq.rate 1.709687 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 247312 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.062545 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.030776 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 188954 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2003142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235969 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58358 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822989000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235969 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58358 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 197735 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34360.710576 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.859290 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 165001 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1124763500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.165545 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32734 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1018296000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32727 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 440236 # number of replacements +system.cpu.dcache.tagsinuse 4094.816019 # Cycle average of tags in use +system.cpu.dcache.total_refs 206409236 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444332 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 464.538309 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 88952000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.816019 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 138485254 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67921309 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1329 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1335 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 206406563 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 206406563 # number of overall hits +system.cpu.dcache.ReadReq_misses 243961 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1496222 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1740183 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1740183 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3253587000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26715936018 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 29969523018 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 29969523018 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 138729215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1335 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 208146746 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 208146746 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001759 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.021554 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.011161 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13336.504605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17855.596307 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17222.052519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17222.052519 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 394716 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 46944 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1248905 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1295849 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1295849 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197017 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247317 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 444334 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 444334 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1620169000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2562065527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4182234527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4182234527 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8223.498480 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.439614 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 72895 # number of replacements +system.cpu.l2cache.tagsinuse 17837.050931 # Cycle average of tags in use +system.cpu.l2cache.total_refs 420745 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88410 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.759020 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1909.078024 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15927.972907 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058260 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.486083 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165017 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 394716 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_hits 188953 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 353970 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 353970 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32728 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 394697 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 394697 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.758732 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91091 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91091 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1124545500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2003459500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3128005000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3128005000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 197745 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 394716 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247316 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445061 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445061 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165506 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235986 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204671 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204671 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34360.348937 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34327.561983 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34339.341977 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34339.341977 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 445047 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34337.872700 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31193.775045 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353955 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3127905500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.204680 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91092 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2841285000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.204664 # mshr miss rate for demand accesses +system.cpu.l2cache.writebacks 58107 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32722 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses 91085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1908.878881 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15928.587231 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058254 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486102 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 445047 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34337.872700 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31193.775045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353955 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3127905500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.204680 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91092 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2841285000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.204664 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 91085 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72893 # number of replacements -system.cpu.l2cache.sampled_refs 88408 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1018131500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823239000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2841370500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2841370500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165476 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.586517 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31239.638127 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17837.466112 # Cycle average of tags in use -system.cpu.l2cache.total_refs 420710 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58103 # number of writebacks -system.cpu.memDep0.conflictingLoads 15581715 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22335111 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 172870468 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80793372 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 912454826 # number of misc regfile reads -system.cpu.misc_regfile_writes 2676 # number of misc regfile writes -system.cpu.numCycles 379495341 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 7724801 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 627417466 # Number of HB maps that are committed -system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers -system.cpu.rename.IQFullEvents 44461884 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 169816321 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 4814649 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 165 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 3254253647 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 699315987 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 723227895 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 139243664 # Number of cycles rename is running -system.cpu.rename.SquashCycles 11629973 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 50068276 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 95810424 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 3254253519 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 102907 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 6090 # count of serializing insts renamed -system.cpu.rename.skidInsts 82758432 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 6087 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1029874649 # The number of ROB reads -system.cpu.rob.rob_writes 1367730511 # The number of ROB writes -system.cpu.timesIdled 36653 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 750396309..e576e666c 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout +Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 13:27:10 -M5 started Apr 21 2011 13:30:00 -M5 executing on maize +M5 compiled May 17 2011 09:24:34 +M5 started May 18 2011 08:03:10 +M5 executing on nadc-0214 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -42,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 582418059000 because target called exit() +Exiting @ tick 582418265000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 9d595253b..15c38b8eb 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,319 +1,111 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 154343 # Simulator instruction rate (inst/s) -host_mem_usage 212152 # Number of bytes of host memory used -host_seconds 9107.03 # Real time elapsed on the host -host_tick_rate 63952564 # Simulator tick rate (ticks/s) +sim_seconds 0.582418 # Number of seconds simulated +sim_ticks 582418265000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 199078 # Simulator instruction rate (inst/s) +host_tick_rate 82488656 # Simulator tick rate (ticks/s) +host_mem_usage 245404 # Number of bytes of host memory used +host_seconds 7060.59 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated -sim_seconds 0.582418 # Number of seconds simulated -sim_ticks 582418059000 # Number of ticks simulated +system.cpu.workload.num_syscalls 49 # Number of system calls +system.cpu.numCycles 1164836531 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 103713430 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 103713430 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5339068 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 99018529 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 97659626 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 97659749 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 99018650 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5339067 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 103713551 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 103713551 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 5339067 # The number of times a branch was mispredicted -system.cpu.commit.branches 86248929 # Number of branches committed -system.cpu.commit.bw_lim_events 26710610 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 199490556 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1136580592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.310530 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1136580592 # Number of insts commited each cycle -system.cpu.commit.count 1489523295 # Number of instructions committed -system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. -system.cpu.commit.loads 402512844 # Number of loads committed -system.cpu.commit.membars 51356 # Number of memory barriers committed -system.cpu.commit.refs 569360986 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1405604152 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.828709 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 291461478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14664.632652 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7474.067095 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 290645276 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11969302500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002800 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 816202 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 602863 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1594510000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000732 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 213339 # number of ReadReq MSHR misses -system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15381.021476 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13048.542893 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 165025455 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28014392657 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010916 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1821361 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1553325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3497479243 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001606 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 268036 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 946.591376 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 458308294 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15159.332747 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency -system.cpu.dcache.demand_hits 455670731 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 39983695157 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005755 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2637563 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2156188 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5091989243 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001050 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481375 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4095.405595 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999855 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 458308294 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15159.332747 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 455670731 # number of overall hits -system.cpu.dcache.overall_miss_latency 39983695157 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005755 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2637563 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2156188 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5091989243 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001050 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481375 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 477286 # number of replacements -system.cpu.dcache.sampled_refs 481382 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.405595 # Cycle average of tags in use -system.cpu.dcache.total_refs 455672050 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 132278000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428224 # number of writebacks -system.cpu.decode.BlockedCycles 373408138 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 1727466392 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 394807577 # Number of cycles decode is idle -system.cpu.decode.RunCycles 348667632 # Number of cycles decode is running -system.cpu.decode.SquashCycles 27885594 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 19696634 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 103713551 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 170870865 # Number of cache lines fetched -system.cpu.fetch.Cycles 370648133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1257771 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1732289789 # Number of instructions fetch has processed +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 170870341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1732290571 # Number of instructions fetch has processed +system.cpu.fetch.Branches 103713430 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 97659626 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 370649677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5787764 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 5787763 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.089037 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 170870865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 97659749 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.487153 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1164465575 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.491538 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 170870341 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1258030 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1164465958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.491542 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.715145 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 793817442 68.17% 68.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 81924135 7.04% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44978693 3.86% 79.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22977276 1.97% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 793816281 68.17% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 81924128 7.04% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44979241 3.86% 79.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22976761 1.97% 81.04% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 33360505 2.86% 83.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 33148842 2.85% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14858388 1.28% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7508131 0.64% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 131892163 11.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 33149354 2.85% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14860425 1.28% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7508136 0.64% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 131891127 11.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1164465575 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 16956220 # number of floating regfile reads -system.cpu.fp_regfile_writes 10464632 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 170870865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35272.495756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.283732 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 170869098 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 62326500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1767 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 470 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1297 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 131843.439815 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 170870865 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35272.495756 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency -system.cpu.icache.demand_hits 170869098 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 62326500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses -system.cpu.icache.demand_misses 1767 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 470 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1297 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1047.623620 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.511535 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 170870865 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35272.495756 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 170869098 # number of overall hits -system.cpu.icache.overall_miss_latency 62326500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.overall_misses 1767 # number of overall misses -system.cpu.icache.overall_mshr_hits 470 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45468000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 159 # number of replacements -system.cpu.icache.sampled_refs 1296 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1047.623620 # Cycle average of tags in use -system.cpu.icache.total_refs 170869098 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 370544 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 5675287 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 89603944 # Number of branches executed -system.cpu.iew.exec_nop 100373819 # number of nop insts executed -system.cpu.iew.exec_rate 1.267070 # Inst execution rate -system.cpu.iew.exec_refs 591399205 # number of memory reference insts executed -system.cpu.iew.exec_stores 170154785 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 2507924 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 461157302 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4553877 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 187022162 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1689106884 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 421244420 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6318503 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1475928628 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 66196 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 58644458 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 20174020 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 1209973999 # num instructions consuming a value -system.cpu.iew.wb_count 1473173854 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.961076 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1162877329 # num instructions producing a value -system.cpu.iew.wb_rate 1.264705 # insts written-back per cycle -system.cpu.iew.wb_sent 1474297623 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 1997794756 # number of integer regfile reads -system.cpu.int_regfile_writes 1296594839 # number of integer regfile writes -system.cpu.ipc 1.206697 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.206697 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1482247131 # Type of FU issued -system.cpu.iq.fp_alu_accesses 9142959 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 17762219 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 8523024 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 9165283 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 3391020 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst) +system.cpu.fetch.rateDist::total 1164465958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.089037 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.487153 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 394807963 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 373406946 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 348668673 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19696602 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27885774 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1727469213 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 27885774 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 433132489 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115497751 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53046647 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 325738473 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 209164824 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1709743087 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 128337088 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40459305 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 28107626 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1426817560 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2887436309 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2853766100 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33670209 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 182047108 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3085415 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3085429 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 378978234 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 461157304 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 187023629 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 386274628 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 159918062 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1585635160 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3099558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1482248202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 280896 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 182707220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 240691130 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 855887 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1164465958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.272900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.148645 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 309299023 26.56% 26.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 465738912 40.00% 66.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 229120955 19.68% 86.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 104114644 8.94% 95.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 41468820 3.56% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8912789 0.77% 99.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5349021 0.46% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 304255 0.03% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 157539 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1164465958 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 187446 5.53% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available @@ -339,139 +131,347 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.85% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2748470 81.06% 92.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 240369 7.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 1476495192 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4114870575 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1464650830 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 1762732094 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1585633508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1482247131 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3099557 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 182705519 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 281937 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 855886 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 240684944 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1164465575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.272899 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1164465575 # Number of insts issued each cycle -system.cpu.iq.rate 1.272494 # Inst issue rate -system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026 # average ReadExReq mshr miss latency +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 883945192 59.64% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2632003 0.18% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 424002994 28.61% 88.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171668013 11.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1482248202 # Type of FU issued +system.cpu.iq.rate 1.272495 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3390497 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002287 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4114870963 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1762732436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1464650831 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17762792 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9168295 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8523374 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1476495195 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9143504 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 129748862 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 58644460 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 460365 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20175487 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 27885774 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2507670 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 128778 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1689108521 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4553883 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 461157304 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 187023629 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66282 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8454 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 670428 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5675288 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1475929151 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 421244589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6319051 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 100373803 # number of nop insts executed +system.cpu.iew.exec_refs 591399372 # number of memory reference insts executed +system.cpu.iew.exec_branches 89603944 # Number of branches executed +system.cpu.iew.exec_stores 170154783 # Number of stores executed +system.cpu.iew.exec_rate 1.267070 # Inst execution rate +system.cpu.iew.wb_sent 1474297977 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1473174205 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1162879989 # num instructions producing a value +system.cpu.iew.wb_consumers 1209979019 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.264705 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.961075 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 199492196 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 5339068 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1136580795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.310530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.747402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 402923295 35.45% 35.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 477569254 42.02% 77.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55696756 4.90% 82.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 97088676 8.54% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 32659153 2.87% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8439015 0.74% 94.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 25679683 2.26% 96.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9814988 0.86% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 26709975 2.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1136580795 # Number of insts commited each cycle +system.cpu.commit.count 1489523295 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 569360986 # Number of memory references committed +system.cpu.commit.loads 402512844 # Number of loads committed +system.cpu.commit.membars 51356 # Number of memory barriers committed +system.cpu.commit.branches 86248929 # Number of branches committed +system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.bw_lim_events 26709975 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 2798821441 # The number of ROB reads +system.cpu.rob.rob_writes 3405949800 # The number of ROB writes +system.cpu.timesIdled 11505 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 370573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1405604152 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated +system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.828709 # CPI: Total CPI of All Threads +system.cpu.ipc 1.206696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206696 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1997795279 # number of integer regfile reads +system.cpu.int_regfile_writes 1296594841 # number of integer regfile writes +system.cpu.fp_regfile_reads 16957636 # number of floating regfile reads +system.cpu.fp_regfile_writes 10465342 # number of floating regfile writes +system.cpu.misc_regfile_reads 597198734 # number of misc regfile reads +system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes +system.cpu.icache.replacements 159 # number of replacements +system.cpu.icache.tagsinuse 1046.779418 # Cycle average of tags in use +system.cpu.icache.total_refs 170868575 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1295 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 131944.845560 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1046.779418 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.511123 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 170868575 # number of ReadReq hits +system.cpu.icache.demand_hits 170868575 # number of demand (read+write) hits +system.cpu.icache.overall_hits 170868575 # number of overall hits +system.cpu.icache.ReadReq_misses 1766 # number of ReadReq misses +system.cpu.icache.demand_misses 1766 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 170870341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 170870341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 170870341 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35265.855040 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35265.855040 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35265.855040 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 470 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 470 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 470 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 45432500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45432500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45432500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35055.941358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35055.941358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35055.941358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 477286 # number of replacements +system.cpu.dcache.tagsinuse 4095.405832 # Cycle average of tags in use +system.cpu.dcache.total_refs 455671846 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 481382 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 946.590953 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 132241000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.405832 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999855 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 290645446 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 165025081 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.demand_hits 455670527 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 455670527 # number of overall hits +system.cpu.dcache.ReadReq_misses 816201 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1821735 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.demand_misses 2637936 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2637936 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11969600500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28019650157 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency 39989250657 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39989250657 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 291461647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 458308463 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 458308463 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002800 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010919 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate 0.005756 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.005756 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14665.015725 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15380.749756 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15159.295243 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15159.295243 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 428224 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 602862 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1553699 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2156561 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2156561 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213339 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 268036 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses 481375 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 481375 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1594439500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3497902243 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5092341743 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5092341743 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000732 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001606 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.001050 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001050 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7473.736635 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13050.121040 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10578.741611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10578.741611 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 75915 # number of replacements +system.cpu.l2cache.tagsinuse 17662.572587 # Cycle average of tags in use +system.cpu.l2cache.total_refs 467082 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91426 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.108853 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1959.264776 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15703.307811 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.059792 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.479227 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 180932 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 428224 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 207600 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2079988000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.225521 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_hits 388532 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 388532 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33695 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 60451 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893368000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225521 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 60451 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 214628 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34037.437678 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.970916 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 180932 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1146925500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.156997 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33696 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044743500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156997 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33696 # number of ReadReq MSHR misses +system.cpu.l2cache.demand_misses 94146 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94146 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1146858500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2079993500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3226852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3226852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214627 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 428224 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 428224 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.108819 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 482678 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 482678 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.156993 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.225521 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195049 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195049 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.459415 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.925427 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34274.977163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34274.977163 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482679 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34275.266339 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 388532 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3226913500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.195051 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 94147 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 59282 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2938111500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.195051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 94147 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1959.521413 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15703.307498 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.059800 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.479227 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 482679 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34275.266339 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 388532 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3226913500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.195051 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 94147 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2938111500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.195051 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 94147 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 33695 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60451 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94146 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94146 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 75916 # number of replacements -system.cpu.l2cache.sampled_refs 91427 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1044714500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893375500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2938090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2938090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156993 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225521 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195049 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195049 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.030420 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.830094 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.804899 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.804899 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17662.828910 # Cycle average of tags in use -system.cpu.l2cache.total_refs 467084 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 59282 # number of writebacks -system.cpu.memDep0.conflictingLoads 386274637 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 159916794 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 461157302 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 187022162 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 597198570 # number of misc regfile reads -system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.numCycles 1164836119 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 115497905 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.FullRegisterEvents 28107626 # Number of times there has been no free registers -system.cpu.rename.IQFullEvents 128337052 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 433132347 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 2887426636 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 1709740875 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 1426816340 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 325737783 # Number of cycles rename is running -system.cpu.rename.SquashCycles 27885594 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 209164686 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 182045888 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 33660518 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 2853766118 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 3085415 # count of serializing insts renamed -system.cpu.rename.skidInsts 378977297 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 3085429 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 2798818963 # The number of ROB reads -system.cpu.rob.rob_writes 3405946340 # The number of ROB writes -system.cpu.timesIdled 11499 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 49 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index fc45f8a25..a5d2218be 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,3 +1,5 @@ +Redirecting stdout to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simout +Redirecting stderr to build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2011 13:30:37 -M5 started Apr 21 2011 13:30:43 -M5 executing on maize +M5 compiled May 17 2011 12:22:59 +M5 started May 18 2011 08:01:14 +M5 executing on nadc-0105 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1066,4 +1068,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 751079230500 because target called exit() +Exiting @ tick 750278436000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index a21571816..64628a88b 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 131052 # Simulator instruction rate (inst/s) -host_mem_usage 215332 # Number of bytes of host memory used -host_seconds 12372.92 # Real time elapsed on the host -host_tick_rate 60703496 # Simulator tick rate (ticks/s) +sim_seconds 0.750278 # Number of seconds simulated +sim_ticks 750278436000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 180615 # Simulator instruction rate (inst/s) +host_tick_rate 83571906 # Simulator tick rate (ticks/s) +host_mem_usage 250232 # Number of bytes of host memory used +host_seconds 8977.64 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.751079 # Number of seconds simulated -sim_ticks 751079230500 # Number of ticks simulated +system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.numCycles 1500556873 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 179206646 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 179206646 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 8463551 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 169776881 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 168588435 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 168460210 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 169652659 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 8971423 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted -system.cpu.commit.branches 107161579 # Number of branches committed -system.cpu.commit.bw_lim_events 11445860 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 1402522347 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.156127 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1402522347 # Number of insts commited each cycle -system.cpu.commit.count 1621493982 # Number of instructions committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. -system.cpu.commit.loads 419042125 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 607228182 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 1621493982 # Number of Instructions Simulated -system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.926404 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 325401931 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10107.251018 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7152.951878 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 325183672 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2205998500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 218259 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 3345 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1537269500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 214914 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19574.534314 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10012.304968 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186952974 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24137025496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006552 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1233083 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 982981 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2504097497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 250102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15974.978853 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1101.331236 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 472140500 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 513587988 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18150.803874 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency -system.cpu.dcache.demand_hits 512136646 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26343023996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002826 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1451342 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 986326 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4041366997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 465016 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999792 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 512136646 # number of overall hits -system.cpu.dcache.overall_miss_latency 26343023996 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002826 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1451342 # number of overall misses -system.cpu.dcache.overall_mshr_hits 986326 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4041366997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 465016 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 460920 # number of replacements -system.cpu.dcache.sampled_refs 465016 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.146726 # Cycle average of tags in use -system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 411408 # number of writebacks -system.cpu.decode.BlockedCycles 587921420 # Number of cycles decode is blocked -system.cpu.decode.DecodedInsts 2472731706 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 429893143 # Number of cycles decode is idle -system.cpu.decode.RunCycles 331529130 # Number of cycles decode is running -system.cpu.decode.SquashCycles 99378480 # Number of cycles decode is squashing -system.cpu.decode.UnblockCycles 53178654 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched -system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 625222 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1408639601 # Number of instructions fetch has processed +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 168643185 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1398775423 # Number of instructions fetch has processed +system.cpu.fetch.Branches 179206646 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 168588435 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 401459368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14868125 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 15384200 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.119823 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 170058043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 168460210 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.937744 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1501900827 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.699260 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.059388 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 168643185 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 821564 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1500265844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.692515 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.050179 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1104715792 73.55% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26107791 1.74% 75.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14369087 0.96% 76.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13756932 0.92% 77.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 30207594 2.01% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 20132707 1.34% 80.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34410865 2.29% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37556252 2.50% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220643807 14.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1101846908 73.44% 73.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25629201 1.71% 75.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 17503252 1.17% 76.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17259352 1.15% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30203070 2.01% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16882652 1.13% 80.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34105222 2.27% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37737433 2.52% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 219098754 14.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1501900827 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 170058043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35240.756303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.058688 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 170056853 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 41936500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1190 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 321 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 30694000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 869 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 195692.581128 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 170058043 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35240.756303 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency -system.cpu.icache.demand_hits 170056853 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 41936500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1190 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 30694000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 869 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.387535 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 170056853 # number of overall hits -system.cpu.icache.overall_miss_latency 41936500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1190 # number of overall misses -system.cpu.icache.overall_mshr_hits 321 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 30694000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 869 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 11 # number of replacements -system.cpu.icache.sampled_refs 869 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 793.670730 # Cycle average of tags in use -system.cpu.icache.total_refs 170056853 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 111429178 # Number of branches executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 1.227514 # Inst execution rate -system.cpu.iew.exec_refs 636597814 # number of memory reference insts executed -system.cpu.iew.exec_stores 191695864 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 312936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 250798855 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2343198083 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 444901950 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13067063 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1843921293 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 56293 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 119484333 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 6399400 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 47 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 196809249 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 62612798 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 2082700302 # num instructions consuming a value -system.cpu.iew.wb_count 1838995466 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.683970 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1424504384 # num instructions producing a value -system.cpu.iew.wb_rate 1.224235 # insts written-back per cycle -system.cpu.iew.wb_sent 1842743630 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads -system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes -system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued +system.cpu.fetch.rateDist::total 1500265844 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119427 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.932171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 426619882 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 588582259 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 331774062 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 54890410 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 98399231 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2463603655 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 98399231 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 490140995 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 167797271 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 309381141 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 434544169 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2390094348 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 298397694 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 109374277 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2388910462 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5790943512 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5790943448 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 770915812 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 713558954 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 613723437 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250366407 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 539421468 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 206415389 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2337617045 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1854722734 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 196953 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 715983422 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1505792788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1500265844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.236263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.216770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 461494018 30.76% 30.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 582014055 38.79% 69.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 214930558 14.33% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153972669 10.26% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 64799231 4.32% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 17691341 1.18% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4397619 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 840611 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125742 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1500265844 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 159647 3.75% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3486871 81.91% 85.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 610438 14.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 27575645 1.49% 1.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1184540758 63.87% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued @@ -287,179 +165,301 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 450487645 24.29% 89.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192118686 10.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1856988356 # Type of FU issued -system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses +system.cpu.iq.FU_type_0::total 1854722734 # Type of FU issued +system.cpu.iq.rate 1.236023 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4256956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002295 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5214165186 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3059990828 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1837811582 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 4273878 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 3071160852 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2343198002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1856988356 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 721564206 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 1501900827 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.236425 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1501900827 # Number of insts issued each cycle -system.cpu.iq.rate 1.236213 # Inst issue rate -system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 191287 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2024064500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235198 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58826 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832767000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58826 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 215772 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34136.783762 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.222249 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 182665 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1130166500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.153435 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33107 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026523000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153435 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33107 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 411408 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 411408 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.099879 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1831404026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 117971084 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 194681312 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16091 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6391116 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 62180350 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30252 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 98399231 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1363305 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 110880 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2337617123 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 338195 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 613723437 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 250366407 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 56702 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6391116 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4450206 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4153743 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8603949 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1842187665 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 444314021 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12535069 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 636013673 # number of memory reference insts executed +system.cpu.iew.exec_branches 111427506 # Number of branches executed +system.cpu.iew.exec_stores 191699652 # Number of stores executed +system.cpu.iew.exec_rate 1.227669 # Inst execution rate +system.cpu.iew.wb_sent 1840965230 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1837811594 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1424401809 # num instructions producing a value +system.cpu.iew.wb_consumers 2083960582 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 1.224753 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683507 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 716132515 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8463578 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1401866613 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.156668 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.378442 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 520031376 37.10% 37.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 533018726 38.02% 75.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 125308330 8.94% 84.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 139235246 9.93% 93.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 43288203 3.09% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23453801 1.67% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4331063 0.31% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1854281 0.13% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11345587 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1401866613 # Number of insts commited each cycle +system.cpu.commit.count 1621493982 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 607228182 # Number of memory references committed +system.cpu.commit.loads 419042125 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 107161579 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.bw_lim_events 11345587 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 3728147523 # The number of ROB reads +system.cpu.rob.rob_writes 4773653528 # The number of ROB writes +system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 291029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1621493982 # Number of Instructions Simulated +system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated +system.cpu.cpi 0.925416 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.925416 # CPI: Total CPI of All Threads +system.cpu.ipc 1.080595 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.080595 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3235784294 # number of integer regfile reads +system.cpu.int_regfile_writes 1830729236 # number of integer regfile writes +system.cpu.fp_regfile_reads 12 # number of floating regfile reads +system.cpu.misc_regfile_reads 930213220 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 793.330591 # Cycle average of tags in use +system.cpu.icache.total_refs 168641986 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 875 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 192733.698286 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 793.330591 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.387368 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 168641986 # number of ReadReq hits +system.cpu.icache.demand_hits 168641986 # number of demand (read+write) hits +system.cpu.icache.overall_hits 168641986 # number of overall hits +system.cpu.icache.ReadReq_misses 1199 # number of ReadReq misses +system.cpu.icache.demand_misses 1199 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1199 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 42201000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 42201000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 42201000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 168643185 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 168643185 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 168643185 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35196.830692 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35196.830692 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35196.830692 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 324 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 324 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 875 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 875 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 875 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 30921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 30921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 30921000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35338.285714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 460957 # number of replacements +system.cpu.dcache.tagsinuse 4095.145869 # Cycle average of tags in use +system.cpu.dcache.total_refs 513034277 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 465053 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1103.173782 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317696000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.145869 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 326108931 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186925346 # number of WriteReq hits +system.cpu.dcache.demand_hits 513034277 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 513034277 # number of overall hits +system.cpu.dcache.ReadReq_misses 218266 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1260711 # number of WriteReq misses +system.cpu.dcache.demand_misses 1478977 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1478977 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2205272500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24390827496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 26596099996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 26596099996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 326327197 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 514513254 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 514513254 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000669 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006699 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.002875 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002875 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10103.600652 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19346.882431 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17982.767816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17982.767816 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 474736000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29560 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16060.081191 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 411400 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3331 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1010593 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1013924 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1013924 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 214935 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 250118 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 465053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 465053 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1536673000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2518183497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4054856497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4054856497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7149.477749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10067.981901 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 73679 # number of replacements +system.cpu.l2cache.tagsinuse 18021.980204 # Cycle average of tags in use +system.cpu.l2cache.total_refs 455469 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89282 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.101465 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1918.737195 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16103.243009 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058555 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.491432 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 182682 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 411400 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 191297 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 373979 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 373979 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33118 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58831 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91949 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91949 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130130500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2026415500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3156546000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3156546000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 215800 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 411400 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 250128 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 465928 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 465928 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.153466 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235204 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197346 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197346 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34124.358355 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34444.689024 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34329.312989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34329.312989 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 465885 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34310.106273 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 373952 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3154231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.197330 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91933 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 58539 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2859290000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.197330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91933 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058491 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491164 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 373952 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3154231000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.197330 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91933 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2859290000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.197330 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91933 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 33118 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58831 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91949 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91949 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 73660 # number of replacements -system.cpu.l2cache.sampled_refs 89268 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026873000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832918500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2859791500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2859791500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235204 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197346 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197346 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.491938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.657731 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18011.074755 # Cycle average of tags in use -system.cpu.l2cache.total_refs 455256 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58532 # number of writebacks -system.cpu.memDep0.conflictingLoads 528261825 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 206728085 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 615851374 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250798855 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 931071836 # number of misc regfile reads -system.cpu.numCycles 1502158462 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 169288978 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 298516669 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 493321936 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 5808956116 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 2397077126 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 2395694665 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 310095488 # Number of cycles rename is running -system.cpu.rename.SquashCycles 99378480 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 429812969 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 777700015 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 5808956052 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 2976 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 89 # count of serializing insts renamed -system.cpu.rename.skidInsts 706930007 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 89 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3734283918 # The number of ROB reads -system.cpu.rob.rob_writes 4785794667 # The number of ROB writes -system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 48 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |