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authorGabe Black <gblack@eecs.umich.edu>2010-05-03 00:45:01 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-05-03 00:45:01 -0700
commit8b0c83008e6c1964c9606a47213f11599ab186c5 (patch)
treeb15e4205be5850c21bcfa241b548173cb8a088b7 /tests/long/00.gzip/ref
parent2ee7a892092086db1bdf707438a9c10bf1426a69 (diff)
downloadgem5-8b0c83008e6c1964c9606a47213f11599ab186c5.tar.xz
X86: Update stats for the updated auxilliary vectors.
Diffstat (limited to 'tests/long/00.gzip/ref')
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini2
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-atomic/simout10
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt18
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini2
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-timing/simout10
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt216
6 files changed, 129 insertions, 129 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index 8ce850818..8edc68d8c 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -57,7 +57,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index dd9141c9e..21af511ee 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 25 2010 03:41:05
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:41:09
-M5 executing on SC2B0619
+M5 compiled May 2 2010 23:23:01
+M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
+M5 started May 2 2010 23:23:02
+M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -44,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 962929075000 because target called exit()
+Exiting @ tick 962929106000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index eeabe51c0..4551896c4 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1572419 # Simulator instruction rate (inst/s)
-host_mem_usage 188984 # Number of bytes of host memory used
-host_seconds 1029.86 # Real time elapsed on the host
-host_tick_rate 935012313 # Simulator tick rate (ticks/s)
+host_inst_rate 3183370 # Simulator instruction rate (inst/s)
+host_mem_usage 217548 # Number of bytes of host memory used
+host_seconds 508.70 # Real time elapsed on the host
+host_tick_rate 1892936287 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1619366736 # Number of instructions simulated
+sim_insts 1619366787 # Number of instructions simulated
sim_seconds 0.962929 # Number of seconds simulated
-sim_ticks 962929075000 # Number of ticks simulated
+sim_ticks 962929106000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1925858151 # number of cpu cycles simulated
-system.cpu.num_insts 1619366736 # Number of instructions executed
-system.cpu.num_refs 607228174 # Number of memory references
+system.cpu.numCycles 1925858213 # number of cpu cycles simulated
+system.cpu.num_insts 1619366787 # Number of instructions executed
+system.cpu.num_refs 607228182 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index c67ff9af1..bf0f0affa 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -157,7 +157,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 68f564509..0c109578a 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 25 2010 03:41:05
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:47:37
-M5 executing on SC2B0619
+M5 compiled May 2 2010 23:23:01
+M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
+M5 started May 2 2010 23:23:02
+M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -44,4 +44,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1814726932000 because target called exit()
+Exiting @ tick 1814725999000 because target called exit()
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 59d079222..a907a8948 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,82 +1,82 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 992380 # Simulator instruction rate (inst/s)
-host_mem_usage 196544 # Number of bytes of host memory used
-host_seconds 1631.80 # Real time elapsed on the host
-host_tick_rate 1112100106 # Simulator tick rate (ticks/s)
+host_inst_rate 1830893 # Simulator instruction rate (inst/s)
+host_mem_usage 225176 # Number of bytes of host memory used
+host_seconds 884.47 # Real time elapsed on the host
+host_tick_rate 2051770366 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1619366736 # Number of instructions simulated
-sim_seconds 1.814727 # Number of seconds simulated
-sim_ticks 1814726932000 # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20884.820230 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17884.820230 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 418844783 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4121306000 # number of ReadReq miss cycles
+sim_insts 1619366787 # Number of instructions simulated
+sim_seconds 1.814726 # Number of seconds simulated
+sim_ticks 1814725999000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 20886.624165 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17886.624165 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4121474000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 197335 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3529301000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3529496000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 197335 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 188186056 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 187876631 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17327800000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_hits 187876653 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17326624000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 309425 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16399525000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses 309404 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 16398412000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 309425 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 309404 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1372.614288 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42325.964954 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 606721414 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21449106000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000835 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 506760 # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 42326.481558 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 606721452 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 21448098000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 506730 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 19928826000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000835 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 506760 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 19927908000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 506730 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.901154 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42325.964954 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39325.964954 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4094.901606 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 42326.481558 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 606721414 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21449106000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000835 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 506760 # number of overall misses
+system.cpu.dcache.overall_hits 606721452 # number of overall hits
+system.cpu.dcache.overall_miss_latency 21448098000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 506730 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 19928826000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000835 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 506760 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 19927908000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 506730 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 437970 # number of replacements
-system.cpu.dcache.sampled_refs 442066 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 437952 # number of replacements
+system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.901154 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606786108 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 779430000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 306212 # number of writebacks
-system.cpu.icache.ReadReq_accesses 1186516703 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tagsinuse 4094.901606 # Cycle average of tags in use
+system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 779585000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 306191 # number of writebacks
+system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1186515981 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
@@ -85,16 +85,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1643373.934903 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1186516703 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1186515981 # number of demand (read+write) hits
+system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
@@ -106,12 +106,12 @@ system.cpu.icache.fast_writes 0 # nu
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 660.164909 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::0 660.164839 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1186515981 # number of overall hits
+system.cpu.icache.overall_hits 1186516018 # number of overall hits
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 722 # number of overall misses
@@ -124,92 +124,92 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 660.164909 # Cycle average of tags in use
-system.cpu.icache.total_refs 1186515981 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 660.164839 # Cycle average of tags in use
+system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadExReq_accesses 244731 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 12726012000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 12725544000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 244731 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 9789240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 244722 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9788880000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 244731 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 198057 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_mshr_misses 244722 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 164987 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1719640000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.166972 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33070 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1322800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166972 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33070 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 64694 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_hits 164971 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1720004000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.167015 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33077 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1323080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.167015 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33077 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 64682 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3364088000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 3363464000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 64694 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587760000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 64682 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 64694 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 306212 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 306212 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 64682 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 306191 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 306191 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.429569 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.428492 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 442788 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 164987 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14445652000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.627391 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 277801 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 164971 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 14445548000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.627412 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 277799 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11112040000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.627391 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 277801 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 11111960000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.627412 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 277799 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.052737 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.452189 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1728.087970 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14817.313734 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 442788 # number of overall (read+write) accesses
+system.cpu.l2cache.occ_%::0 0.052754 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.452175 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1728.633036 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14816.859075 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 164987 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14445652000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.627391 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 277801 # number of overall misses
+system.cpu.l2cache.overall_hits 164971 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 14445548000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.627412 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 277799 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11112040000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.627391 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 277801 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 11111960000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.627412 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 277799 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 81543 # number of replacements
-system.cpu.l2cache.sampled_refs 97060 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 81557 # number of replacements
+system.cpu.l2cache.sampled_refs 97073 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16545.401704 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 332874 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16545.492111 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 332814 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61555 # number of writebacks
+system.cpu.l2cache.writebacks 61569 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 3629453864 # number of cpu cycles simulated
-system.cpu.num_insts 1619366736 # Number of instructions executed
-system.cpu.num_refs 607228174 # Number of memory references
+system.cpu.numCycles 3629451998 # number of cpu cycles simulated
+system.cpu.num_insts 1619366787 # Number of instructions executed
+system.cpu.num_refs 607228182 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------