diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
| commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
| tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/long/00.gzip/ref | |
| parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
| download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz | |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/long/00.gzip/ref')
9 files changed, 544 insertions, 522 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 12a85f3ff..d33b7fe91 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 1244f3aca..7c98f6fbe 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 22 2011 10:22:27 -M5 revision c70e4f3301ed 7980 default ext/rfe_stats_updates.patch qtip tip -M5 started Feb 22 2011 10:22:49 +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:10:13 M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 216988269500 because target called exit() +Exiting @ tick 212151683000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 7e719ad32..c117cacbc 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,130 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123576 # Simulator instruction rate (inst/s) -host_mem_usage 255024 # Number of bytes of host memory used -host_seconds 4860.01 # Real time elapsed on the host -host_tick_rate 44647688 # Simulator tick rate (ticks/s) +host_inst_rate 130169 # Simulator instruction rate (inst/s) +host_mem_usage 255152 # Number of bytes of host memory used +host_seconds 4627.51 # Real time elapsed on the host +host_tick_rate 45845717 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 600581343 # Number of instructions simulated -sim_seconds 0.216988 # Number of seconds simulated -sim_ticks 216988269500 # Number of ticks simulated +sim_insts 602359950 # Number of instructions simulated +sim_seconds 0.212152 # Number of seconds simulated +sim_ticks 212151683000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 80605280 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 86769998 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3926724 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 92457743 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 92457743 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 70067581 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7237688 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 77353146 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 83702663 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1593 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3826409 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 84369915 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 91120892 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1482138 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 70826872 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 7259535 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 415627277 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.445000 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.803105 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 408127750 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.475910 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.811076 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 151327612 36.41% 36.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 131463127 31.63% 68.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 59591085 14.34% 82.38% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64% 87.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 16801337 4.04% 91.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14774918 3.55% 94.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 12865599 3.10% 97.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2265832 0.55% 98.26% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7237688 1.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 143768271 35.23% 35.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 130628056 32.01% 67.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 60243177 14.76% 81.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 18962619 4.65% 86.64% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 17622510 4.32% 90.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 14296756 3.50% 94.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 13120148 3.21% 97.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2226678 0.55% 98.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7259535 1.78% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 415627277 # Number of insts commited each cycle -system.cpu.commit.COM:count 600581394 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 408127750 # Number of insts commited each cycle +system.cpu.commit.COM:count 602360001 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 531746837 # Number of committed integer instructions. -system.cpu.commit.COM:loads 148953025 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 219174038 # Number of memory references committed +system.cpu.commit.COM:function_calls 997573 # Number of function calls committed. +system.cpu.commit.COM:int_insts 533522759 # Number of committed integer instructions. +system.cpu.commit.COM:loads 148952624 # Number of loads committed +system.cpu.commit.COM:membars 1328 # Number of memory barriers committed +system.cpu.commit.COM:refs 219173667 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4754311 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 600581394 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 3642 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 121349980 # The number of squashed insts skipped by commit -system.cpu.committedInsts 600581343 # Number of Instructions Simulated -system.cpu.committedInsts_total 600581343 # Number of Instructions Simulated -system.cpu.cpi 0.722594 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.722594 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 140357692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13126.895414 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.393105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 140121332 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3102673000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001684 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 236360 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 40725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1525443000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 195635 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 17787.364223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.276216 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 67933393 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26422506996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.021399 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1485465 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1237601 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2567939504 # number of WriteReq MSHR miss cycles +system.cpu.commit.branchMispredicts 3887306 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 602360001 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 6327 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 105586113 # The number of squashed insts skipped by commit +system.cpu.committedInsts 602359950 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359950 # Number of Instructions Simulated +system.cpu.cpi 0.704402 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.704402 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1392 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 10807.692308 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 1379 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 140500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.009339 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 13 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 13 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 139573989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13187.861272 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7875.361074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 139338017 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3111966000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001691 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 235972 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 40375 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1540397000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195597 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 1357 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 1357 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 19453.548688 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10358.949737 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 68088613 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 25852171016 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019144 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1328918 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1081042 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2567735025 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247864 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4386.427788 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 247876 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4395.291476 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 469.123191 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked +system.cpu.dcache.avg_refs 467.742670 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 2182 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 9597504 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 9590526 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 209776550 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 17147.607914 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency -system.cpu.dcache.demand_hits 208054725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29525179996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008208 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1721825 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1278326 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4093382504 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 443499 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 208991520 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18508.736727 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency +system.cpu.dcache.demand_hits 207426630 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 28964137016 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.007488 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1564890 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1121417 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4108132025 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002122 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 443473 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.932523 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 209776550 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 17147.607914 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4094.932917 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 208991520 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18508.736727 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 208054725 # number of overall hits -system.cpu.dcache.overall_miss_latency 29525179996 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008208 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1721825 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1278326 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4093382504 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 443499 # number of overall MSHR misses +system.cpu.dcache.overall_hits 207426630 # number of overall hits +system.cpu.dcache.overall_miss_latency 28964137016 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.007488 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1564890 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1121417 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4108132025 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002122 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 443473 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 439401 # number of replacements -system.cpu.dcache.sampled_refs 443497 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 439373 # number of replacements +system.cpu.dcache.sampled_refs 443469 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.932523 # Cycle average of tags in use -system.cpu.dcache.total_refs 208054728 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 90723000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 394050 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 84141899 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 763381679 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 172755505 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 145178933 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 17467706 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 13550939 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.932917 # Cycle average of tags in use +system.cpu.dcache.total_refs 207429374 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 89412000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 394062 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 84592597 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 1269 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 6208796 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 740088879 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 168706146 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 141255851 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15304229 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 4703 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 13573155 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -146,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 92457743 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 75163466 # Number of cache lines fetched -system.cpu.fetch.Cycles 161721841 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 803288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 727645114 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 5447051 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.213048 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 75163466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 80605280 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.676692 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 433094982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.793896 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.871529 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 91120892 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 73409824 # Number of cache lines fetched +system.cpu.fetch.Cycles 157341177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 853332 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 706778220 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2056 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4584124 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.214754 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 73409824 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 78835284 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.665738 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 423431978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.775923 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.853239 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 271374463 62.66% 62.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26620223 6.15% 68.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11465885 2.65% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12676536 2.93% 84.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5122176 1.18% 85.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 266090925 62.84% 62.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25382675 5.99% 68.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18707202 4.42% 73.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23120734 5.46% 78.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11518747 2.72% 81.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12813304 3.03% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4581816 1.08% 85.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7541689 1.78% 87.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53674886 12.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 433094982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 423431978 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 75163466 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35392.896175 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34027.443106 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 75162551 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32384500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 915 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 168 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25418500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 73409824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35098.824786 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34224.447514 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 73408888 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32852500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 936 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 212 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 24778500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 747 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 100889.330201 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 101956.788889 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 75163466 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35392.896175 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34027.443106 # average overall mshr miss latency -system.cpu.icache.demand_hits 75162551 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32384500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000012 # miss rate for demand accesses -system.cpu.icache.demand_misses 915 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 168 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25418500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 73409824 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35098.824786 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency +system.cpu.icache.demand_hits 73408888 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32852500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses +system.cpu.icache.demand_misses 936 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 212 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 24778500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 747 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.323287 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 662.091546 # Average occupied blocks per context -system.cpu.icache.overall_accesses 75163466 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35392.896175 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34027.443106 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.307623 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 630.012478 # Average occupied blocks per context +system.cpu.icache.overall_accesses 73409824 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35098.824786 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 75162551 # number of overall hits -system.cpu.icache.overall_miss_latency 32384500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000012 # miss rate for overall accesses -system.cpu.icache.overall_misses 915 # number of overall misses -system.cpu.icache.overall_mshr_hits 168 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25418500 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 73408888 # number of overall hits +system.cpu.icache.overall_miss_latency 32852500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses +system.cpu.icache.overall_misses 936 # number of overall misses +system.cpu.icache.overall_mshr_hits 212 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 24778500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 747 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 23 # number of replacements -system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks. +system.cpu.icache.replacements 33 # number of replacements +system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 662.091546 # Cycle average of tags in use -system.cpu.icache.total_refs 75162551 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 630.012478 # Cycle average of tags in use +system.cpu.icache.total_refs 73408888 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 881558 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 74261585 # Number of branches executed -system.cpu.iew.EXEC:nop 62913 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.487680 # Inst execution rate -system.cpu.iew.EXEC:refs 240772759 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 74373435 # Number of stores executed +system.cpu.idleCycles 871389 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 73892971 # Number of branches executed +system.cpu.iew.EXEC:nop 61798 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.506493 # Inst execution rate +system.cpu.iew.EXEC:refs 238982736 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 73900874 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 747728792 # num instructions consuming a value -system.cpu.iew.WB:count 638494059 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.593986 # average fanout of values written-back +system.cpu.iew.WB:consumers 738975685 # num instructions consuming a value +system.cpu.iew.WB:count 633750064 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.595052 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 444140095 # num instructions producing a value -system.cpu.iew.WB:rate 1.471264 # insts written-back per cycle -system.cpu.iew.WB:sent 640207091 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5262481 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 938808 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 184696679 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 3886 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3056896 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 88578804 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 721929028 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 166399324 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7744349 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 645618045 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 15544 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 439728869 # num instructions producing a value +system.cpu.iew.WB:rate 1.493625 # insts written-back per cycle +system.cpu.iew.WB:sent 634774515 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4294677 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 946102 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 181732576 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5902 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2934920 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 84682953 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 707943366 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 165081862 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6085968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 639209952 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 15519 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10568 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 17467706 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 68840 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2353 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15304229 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 50818 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8986 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 24659910 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 40290 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8944 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 24296735 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 57403 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 927620 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15164 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 35743653 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 18357791 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1455468 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 1741672216 # number of integer regfile reads -system.cpu.int_regfile_writes 500762058 # number of integer regfile writes -system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 930118 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15159 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 32779951 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 14461910 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 930118 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 636408 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3658269 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1727320002 # number of integer regfile reads +system.cpu.int_regfile_writes 496802288 # number of integer regfile writes +system.cpu.ipc 1.419645 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.419645 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 408522313 62.53% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6689 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 168909835 25.85% 88.38% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 75923554 11.62% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 402470959 62.37% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6564 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 167645097 25.98% 88.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 75173297 11.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 653362394 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7689776 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011770 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 645295920 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 7755028 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.012018 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 110224 1.43% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7362915 95.75% 97.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 216637 2.82% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 198697 2.56% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 7348141 94.75% 97.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 208190 2.68% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 433094982 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.508589 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.485286 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 423431978 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.523966 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.473546 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 131707315 30.41% 30.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 125173244 28.90% 59.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 78416793 18.11% 77.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 46415103 10.72% 88.14% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 32898080 7.60% 95.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 12956560 2.99% 98.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 3885385 0.90% 99.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 717191 0.17% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 925311 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 124767045 29.47% 29.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 123576315 29.18% 58.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 78343969 18.50% 77.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 46750040 11.04% 88.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 32770284 7.74% 95.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 12193598 2.88% 98.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 3344839 0.79% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 823717 0.19% 99.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 862171 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 433094982 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.505525 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 423431978 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.520836 # Inst issue rate system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 661052150 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1748135502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 638494043 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 843674084 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 721862229 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 653362394 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 120901183 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 625992 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 244 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 239953447 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.int_alu_accesses 653050928 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1722505687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 633750048 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 814020305 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 707874308 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 645295920 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7260 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 105229644 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 726877 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 933 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 212022368 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -403,114 +415,114 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 247865 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.344792 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.636053 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 189395 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2015598000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235895 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58470 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828569500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58470 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 196377 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34258.354481 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31117.674945 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 163670 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1120488000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.166552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32707 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1017423500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166496 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32696 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses 247874 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.539920 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.130694 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 189432 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2008274000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235773 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58442 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1826963000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235773 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58442 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 196316 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34255.152982 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.089447 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 163665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1118465000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.166319 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32651 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency 1015393000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32645 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_rate 0.333333 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.333333 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 394050 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 394050 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6190.332326 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 394062 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 394062 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5824.362606 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.731748 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 331 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 4.737794 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 353 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 2049000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 2056000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444242 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34395.582219 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.701775 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353065 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3136086000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.205242 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2845993000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.205217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses 444190 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34324.690152 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 353097 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3126739000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.205077 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91093 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 2842356000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.205063 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91087 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.056947 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.488639 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1866.034580 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16011.711774 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 444242 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34395.582219 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.701775 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.056232 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.489259 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1842.604757 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16032.025879 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 444190 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34324.690152 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353065 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3136086000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.205242 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91177 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2845993000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.205217 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91166 # number of overall MSHR misses +system.cpu.l2cache.overall_hits 353097 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3126739000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.205077 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91093 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 2842356000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.205063 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91087 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72987 # number of replacements -system.cpu.l2cache.sampled_refs 88484 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 72891 # number of replacements +system.cpu.l2cache.sampled_refs 88396 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17877.746353 # Cycle average of tags in use -system.cpu.l2cache.total_refs 418684 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17874.630636 # Cycle average of tags in use +system.cpu.l2cache.total_refs 418802 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58152 # number of writebacks -system.cpu.memDep0.conflictingLoads 56143840 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33466009 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 184696679 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88578804 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 960863165 # number of misc regfile reads -system.cpu.misc_regfile_writes 9367 # number of misc regfile writes -system.cpu.numCycles 433976540 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58120 # number of writebacks +system.cpu.memDep0.conflictingLoads 59394757 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28028248 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 181732576 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84682953 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 939363465 # number of misc regfile reads +system.cpu.misc_regfile_writes 9368 # number of misc regfile writes +system.cpu.numCycles 424303367 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12394449 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 63310870 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 190431447 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2146129408 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 749361548 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 579635256 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 140764920 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 17467706 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 71980154 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 110388313 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:BlockCycles 12681660 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 471025546 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 63633162 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 186161185 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2954668 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 2083466922 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 728669573 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 566468470 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 137330990 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15304229 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 71846492 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 95442921 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2146129312 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 56306 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 128598458 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3954 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1130320351 # The number of ROB reads -system.cpu.rob.rob_writes 1461345715 # The number of ROB writes -system.cpu.timesIdled 36569 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 2083466826 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 107422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 6263 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 128424972 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 6268 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1108813717 # The number of ROB reads +system.cpu.rob.rob_writes 1431196844 # The number of ROB writes +system.cpu.timesIdled 36620 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini index 17d38a039..e931d99dc 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -66,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout index f425b3c91..cf49f4125 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:00:03 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:23:27 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 300302141500 because target called exit() +Exiting @ tick 301191370000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index fb68d0899..0eb8d8824 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1026292 # Simulator instruction rate (inst/s) -host_mem_usage 229344 # Number of bytes of host memory used -host_seconds 585.20 # Real time elapsed on the host -host_tick_rate 513165203 # Simulator tick rate (ticks/s) +host_inst_rate 1838558 # Simulator instruction rate (inst/s) +host_mem_usage 246240 # Number of bytes of host memory used +host_seconds 327.63 # Real time elapsed on the host +host_tick_rate 919312999 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 600581394 # Number of instructions simulated -sim_seconds 0.300302 # Number of seconds simulated -sim_ticks 300302141500 # Number of ticks simulated +sim_insts 602359851 # Number of instructions simulated +sim_seconds 0.301191 # Number of seconds simulated +sim_ticks 301191370000 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -52,24 +52,24 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 600604284 # number of cpu cycles simulated +system.cpu.numCycles 602382741 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 600604284 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 602382741 # Number of busy cycles +system.cpu.num_conditional_control_insts 67016068 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 1993596 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 600581394 # Number of instructions executed -system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses -system.cpu.num_int_insts 531746837 # number of integer instructions -system.cpu.num_int_register_reads 1690709529 # number of times the integer registers were read -system.cpu.num_int_register_writes 456307392 # number of times the integer registers were written -system.cpu.num_load_insts 148953025 # Number of load instructions -system.cpu.num_mem_refs 219174038 # number of memory refs +system.cpu.num_insts 602359851 # Number of instructions executed +system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_int_register_reads 1694262461 # number of times the integer registers were read +system.cpu.num_int_register_writes 458085654 # number of times the integer registers were written +system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index de769cd56..cd3bf6aae 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -51,6 +51,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -86,6 +87,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -121,6 +123,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=10000 max_miss_count=0 mshrs=10 @@ -166,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index 70559ac7d..3d2816f3e 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:56:16 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:25 -M5 executing on burrito +M5 compiled Mar 11 2011 20:10:09 +M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch +M5 started Mar 11 2011 20:13:11 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 796759936000 because target called exit() +Exiting @ tick 796762926000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index 2b5fb88ae..bc2095464 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,27 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 452045 # Simulator instruction rate (inst/s) -host_mem_usage 237056 # Number of bytes of host memory used -host_seconds 1324.25 # Real time elapsed on the host -host_tick_rate 601669731 # Simulator tick rate (ticks/s) +host_inst_rate 732997 # Simulator instruction rate (inst/s) +host_mem_usage 253960 # Number of bytes of host memory used +host_seconds 819.10 # Real time elapsed on the host +host_tick_rate 972728993 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 598619824 # Number of instructions simulated -sim_seconds 0.796760 # Number of seconds simulated -sim_ticks 796759936000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3956862000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3387333000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) +sim_insts 600398281 # Number of instructions simulated +sim_seconds 0.796763 # Number of seconds simulated +sim_ticks 796762926000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 69171110 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses @@ -30,49 +34,49 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # m system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 22578.791611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency -system.cpu.dcache.demand_hits 216774877 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9880276000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002015 # miss rate for demand accesses -system.cpu.dcache.demand_misses 437591 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency +system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses +system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8567503000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002015 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 437591 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.223177 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 22578.791611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 216774877 # number of overall hits -system.cpu.dcache.overall_miss_latency 9880276000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002015 # miss rate for overall accesses -system.cpu.dcache.overall_misses 437591 # number of overall misses +system.cpu.dcache.overall_hits 216771819 # number of overall hits +system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses +system.cpu.dcache.overall_misses 437564 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8567503000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002015 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 437591 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 433495 # number of replacements -system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 433468 # number of replacements +system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.223177 # Cycle average of tags in use -system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 392389 # number of writebacks +system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use +system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 392392 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 570070553 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 570069910 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses @@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 886578.398134 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 570070553 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency -system.cpu.icache.demand_hits 570069910 # number of demand (read+write) hits +system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 643 # number of demand (read+write) misses @@ -127,12 +131,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 577.728453 # Average occupied blocks per context -system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context +system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 570069910 # number of overall hits +system.cpu.icache.overall_hits 570073892 # number of overall hits system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 643 # number of overall misses @@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 577.728453 # Cycle average of tags in use -system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use +system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses 58451 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 158940 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1640392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.165608 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 31546 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1261840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165608 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 31546 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 392389 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 392389 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.718118 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 348237 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 4679844000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.205363 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 89997 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3599880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.205363 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 89997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.053819 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.492601 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1763.554655 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16141.554862 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.053777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.492610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 348237 # number of overall hits -system.cpu.l2cache.overall_miss_latency 4679844000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.205363 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 89997 # number of overall misses +system.cpu.l2cache.overall_hits 348215 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 89992 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3599880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.205363 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 89997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 71809 # number of replacements -system.cpu.l2cache.sampled_refs 87292 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 71804 # number of replacements +system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17905.109517 # Cycle average of tags in use -system.cpu.l2cache.total_refs 411854 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use +system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 57886 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1593519872 # number of cpu cycles simulated +system.cpu.numCycles 1593525852 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 1593519872 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 1593525852 # Number of busy cycles +system.cpu.num_conditional_control_insts 67016068 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 1993596 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 598619824 # Number of instructions executed -system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses -system.cpu.num_int_insts 531746837 # number of integer instructions -system.cpu.num_int_register_reads 1837343724 # number of times the integer registers were read -system.cpu.num_int_register_writes 456308029 # number of times the integer registers were written -system.cpu.num_load_insts 148953025 # Number of load instructions -system.cpu.num_mem_refs 219174038 # number of memory refs +system.cpu.num_insts 600398281 # Number of instructions executed +system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses +system.cpu.num_int_insts 533522639 # number of integer instructions +system.cpu.num_int_register_reads 1840897552 # number of times the integer registers were read +system.cpu.num_int_register_writes 458086291 # number of times the integer registers were written +system.cpu.num_load_insts 148952594 # Number of load instructions +system.cpu.num_mem_refs 219173607 # number of memory refs system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |