diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
| commit | f125ef22b997d5ba6173d9d3f0d07ae741e279bd (patch) | |
| tree | d3d103939211116d7f8ed7e04db73fbac0b9e9be /tests/long/00.gzip/ref | |
| parent | d0e04859023702ec23c97683700c638949a1dad1 (diff) | |
| download | gem5-f125ef22b997d5ba6173d9d3f0d07ae741e279bd.tar.xz | |
O3: Update stats for LSQ changes.
Diffstat (limited to 'tests/long/00.gzip/ref')
| -rwxr-xr-x | tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 742 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/arm/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt | 760 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 739 | ||||
| -rwxr-xr-x | tests/long/00.gzip/ref/x86/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt | 724 |
8 files changed, 1494 insertions, 1495 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index ac32dbe3f..5c5a7a6e9 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:00:53 -gem5 started Jul 8 2011 16:09:24 +gem5 compiled Jul 15 2011 17:43:54 +gem5 started Jul 15 2011 18:05:21 gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 145300717500 because target called exit() +Exiting @ tick 145175788500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 339674edd..4f3a6d8f3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.145301 # Number of seconds simulated -sim_ticks 145300717500 # Number of ticks simulated +sim_seconds 0.145176 # Number of seconds simulated +sim_ticks 145175788500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109615 # Simulator instruction rate (inst/s) -host_tick_rate 28162171 # Simulator tick rate (ticks/s) -host_mem_usage 246532 # Number of bytes of host memory used -host_seconds 5159.43 # Real time elapsed on the host +host_inst_rate 116167 # Simulator instruction rate (inst/s) +host_tick_rate 29819633 # Simulator tick rate (ticks/s) +host_mem_usage 246468 # Number of bytes of host memory used +host_seconds 4868.46 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 125840781 # DTB read hits -system.cpu.dtb.read_misses 26740 # DTB read misses +system.cpu.dtb.read_hits 125726238 # DTB read hits +system.cpu.dtb.read_misses 26702 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 125867521 # DTB read accesses -system.cpu.dtb.write_hits 41455603 # DTB write hits -system.cpu.dtb.write_misses 32148 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 41487751 # DTB write accesses -system.cpu.dtb.data_hits 167296384 # DTB hits -system.cpu.dtb.data_misses 58888 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 167355272 # DTB accesses -system.cpu.itb.fetch_hits 71694847 # ITB hits +system.cpu.dtb.read_accesses 125752940 # DTB read accesses +system.cpu.dtb.write_hits 41507366 # DTB write hits +system.cpu.dtb.write_misses 32028 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 41539394 # DTB write accesses +system.cpu.dtb.data_hits 167233604 # DTB hits +system.cpu.dtb.data_misses 58730 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 167292334 # DTB accesses +system.cpu.itb.fetch_hits 71588816 # ITB hits system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 71694887 # ITB accesses +system.cpu.itb.fetch_accesses 71588856 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,246 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 290601436 # number of cpu cycles simulated +system.cpu.numCycles 290351578 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits +system.cpu.BPredUnit.lookups 82068439 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75472139 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4139210 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 77758293 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69764860 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed -system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1965418 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74381248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 740847057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 82068439 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71730278 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139388095 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17359106 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 63481916 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 957 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 71588816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1228525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290282404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.552160 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 150894309 51.98% 51.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11757724 4.05% 56.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15902063 5.48% 61.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 15874475 5.47% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13293221 4.58% 71.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15622251 5.38% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6768599 2.33% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3592047 1.24% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56577715 19.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290282404 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.282652 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.551552 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90540829 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 49762589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 127167334 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9782311 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13029341 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4494723 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 873 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 729210837 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3260 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 13029341 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 98854754 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12652695 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 558 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123369042 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42376014 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 715226972 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32893526 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4012041 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 545137745 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 939207717 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 939205613 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2104 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 81282856 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 36 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 82693608 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131825687 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43890067 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17591169 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7047053 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 644543109 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 621562613 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 380292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77712656 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42125820 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 290282404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.141234 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.879500 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 70571105 24.31% 24.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 58751148 20.24% 44.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 55824387 19.23% 63.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31456534 10.84% 74.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 33062190 11.39% 86.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 24005083 8.27% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12272709 4.23% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3831324 1.32% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 507924 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290282404 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4555010 86.10% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 57 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 523123 9.89% 95.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 212105 4.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451150539 72.57% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7830 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 128375845 20.65% 93.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 42115665 6.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451240060 72.60% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7852 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 128169032 20.62% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42145620 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 621649928 # Type of FU issued -system.cpu.iq.rate 2.139184 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5190490 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008350 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1539391263 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 723910400 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 609602063 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3418 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1948 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 626838696 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11620337 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 621562613 # Type of FU issued +system.cpu.iq.rate 2.140724 # Inst issue rate +system.cpu.iq.fu_busy_cnt 5290295 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008511 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1539074805 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 722600568 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 609952454 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3412 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1900 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1604 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 626851187 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1721 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11465807 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17312357 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 134964 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 365628 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4436658 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17311645 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67694 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 365195 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4438746 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 5886 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 50751 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5929 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50756 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13016656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1515186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101274 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 690779591 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2446688 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 131826399 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 43887979 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 13029341 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1515549 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101263 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 690142973 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2399318 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 131825687 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43890067 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41001 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13794 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 365628 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4028203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 602481 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4630684 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 613929253 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 125867602 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7720675 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 41006 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13792 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 365195 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4054325 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 604453 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4658778 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 614025387 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125753017 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7537226 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 45600120 # number of nop insts executed -system.cpu.iew.exec_refs 167374804 # number of memory reference insts executed -system.cpu.iew.exec_branches 68499674 # Number of branches executed -system.cpu.iew.exec_stores 41507202 # Number of stores executed -system.cpu.iew.exec_rate 2.112616 # Inst execution rate -system.cpu.iew.wb_sent 611080780 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 609603660 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419952220 # num instructions producing a value -system.cpu.iew.wb_consumers 531843575 # num instructions consuming a value +system.cpu.iew.exec_nop 45599835 # number of nop insts executed +system.cpu.iew.exec_refs 167311882 # number of memory reference insts executed +system.cpu.iew.exec_branches 68605174 # Number of branches executed +system.cpu.iew.exec_stores 41558865 # Number of stores executed +system.cpu.iew.exec_rate 2.114765 # Inst execution rate +system.cpu.iew.wb_sent 611451889 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 609954058 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420339317 # num instructions producing a value +system.cpu.iew.wb_consumers 532241742 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.097731 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.100743 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789753 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 88769206 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 88132303 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4122409 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 277515436 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.168733 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.607930 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4138394 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 277253063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.170786 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.607112 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91720629 33.05% 33.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 75337959 27.15% 60.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31629889 11.40% 71.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9762168 3.52% 75.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10089201 3.64% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21364718 7.70% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5897222 2.13% 88.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2300204 0.83% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29413446 10.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91432186 32.98% 32.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75471271 27.22% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31359713 11.31% 71.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9812345 3.54% 75.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10073105 3.63% 78.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21591836 7.79% 86.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5927353 2.14% 88.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2268519 0.82% 89.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29316735 10.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 277515436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 277253063 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -290,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29413446 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29316735 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 938663770 # The number of ROB reads -system.cpu.rob.rob_writes 1394275800 # The number of ROB writes -system.cpu.timesIdled 2250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 69344 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 937861205 # The number of ROB reads +system.cpu.rob.rob_writes 1393014626 # The number of ROB writes +system.cpu.timesIdled 2237 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69174 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.513836 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.513836 # CPI: Total CPI of All Threads -system.cpu.ipc 1.946145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.946145 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 864545189 # number of integer regfile reads -system.cpu.int_regfile_writes 501712619 # number of integer regfile writes -system.cpu.fp_regfile_reads 277 # number of floating regfile reads +system.cpu.cpi 0.513395 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.513395 # CPI: Total CPI of All Threads +system.cpu.ipc 1.947819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.947819 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 864633877 # number of integer regfile reads +system.cpu.int_regfile_writes 501928899 # number of integer regfile writes +system.cpu.fp_regfile_reads 273 # number of floating regfile reads system.cpu.fp_regfile_writes 57 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 798.939045 # Cycle average of tags in use -system.cpu.icache.total_refs 71693570 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 940 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 76269.755319 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 799.817467 # Cycle average of tags in use +system.cpu.icache.total_refs 71587538 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 76076.023379 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 798.939045 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.390107 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 71693570 # number of ReadReq hits -system.cpu.icache.demand_hits 71693570 # number of demand (read+write) hits -system.cpu.icache.overall_hits 71693570 # number of overall hits -system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses -system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1277 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46025000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46025000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46025000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 71694847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 71694847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 71694847 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 799.817467 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.390536 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 71587538 # number of ReadReq hits +system.cpu.icache.demand_hits 71587538 # number of demand (read+write) hits +system.cpu.icache.overall_hits 71587538 # number of overall hits +system.cpu.icache.ReadReq_misses 1278 # number of ReadReq misses +system.cpu.icache.demand_misses 1278 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1278 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 45985500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 45985500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 45985500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 71588816 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 71588816 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 71588816 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36041.503524 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36041.503524 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36041.503524 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35982.394366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35982.394366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35982.394366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,158 +346,158 @@ system.cpu.icache.writebacks 0 # nu system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 940 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 940 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 940 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 33513000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 33513000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 33513000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33582500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33582500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33582500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35688.097768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35688.097768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35688.097768 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 470805 # number of replacements -system.cpu.dcache.tagsinuse 4093.951768 # Cycle average of tags in use -system.cpu.dcache.total_refs 151630549 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 474901 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 319.288755 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126064000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4093.951768 # Average occupied blocks per context +system.cpu.dcache.replacements 470793 # number of replacements +system.cpu.dcache.tagsinuse 4093.950327 # Cycle average of tags in use +system.cpu.dcache.total_refs 151670470 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474889 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 319.380887 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126051000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4093.950327 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 113482808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38147738 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 151630546 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 151630546 # number of overall hits -system.cpu.dcache.ReadReq_misses 730789 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1303583 # number of WriteReq misses -system.cpu.dcache.demand_misses 2034372 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2034372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11799719000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 19632109224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 31431828224 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 31431828224 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 114213597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 113522942 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147524 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 151670466 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151670466 # number of overall hits +system.cpu.dcache.ReadReq_misses 730602 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303797 # number of WriteReq misses +system.cpu.dcache.demand_misses 2034399 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2034399 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11799452000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19635094216 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31434546216 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31434546216 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 114253544 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 153664918 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 153664918 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.033043 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013239 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15450.383816 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15450.383816 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 917496 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 153704865 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153704865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006395 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033048 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013236 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013236 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16150.314398 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15059.932042 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15451.514780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15451.514780 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 884996 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7710.050420 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7629.275862 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423137 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 511918 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1047553 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1559471 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1559471 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218871 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256030 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 474901 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 474901 # number of overall MSHR misses +system.cpu.dcache.writebacks 423112 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 511747 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047763 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1559510 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1559510 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218855 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256034 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474889 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474889 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1640511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3027783994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4668295494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4668295494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640196500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3028456494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4668652994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4668652994 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7495.335152 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7494.443810 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11828.337229 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9831.040504 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9831.040504 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74456 # number of replacements -system.cpu.l2cache.tagsinuse 17669.602101 # Cycle average of tags in use -system.cpu.l2cache.total_refs 478138 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90356 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.291713 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74461 # number of replacements +system.cpu.l2cache.tagsinuse 17667.693378 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478022 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90361 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.290136 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1747.606056 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15921.996045 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.053333 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485901 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186860 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423137 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 196226 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383086 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383086 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32951 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92755 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92755 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1133426500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2066052500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3199479000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3199479000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219811 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423137 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256030 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 475841 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 475841 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.149906 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.233582 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194929 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194929 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34493.870950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34493.870950 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 468000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1746.744701 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15920.948677 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053306 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485869 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186848 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423112 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196221 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 383069 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 383069 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32948 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59813 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92761 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92761 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133336500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2066482500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3199819000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3199819000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219796 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423112 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475830 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475830 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.149903 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233614 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194946 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194946 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.732791 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34549.052881 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34495.305139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34495.305139 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 460000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 80 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 71 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5850 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6478.873239 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59325 # number of writebacks +system.cpu.l2cache.writebacks 59333 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32951 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92755 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92755 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32948 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59813 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92761 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92761 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1022116000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877697000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2899813000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2899813000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022013500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1878097000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2900110500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2900110500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149906 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194929 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194929 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149903 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233614 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194946 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194946 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.984460 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31399.478374 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.329837 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.329837 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index f34e7fb17..eb566e6f8 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:43 -gem5 started Jul 9 2011 00:29:29 +gem5 compiled Jul 15 2011 18:02:03 +gem5 started Jul 16 2011 00:35:36 gem5 executing on u200439-lin.austin.arm.com command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 182546630500 because target called exit() +Exiting @ tick 181676511500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 79eb9dffa..212b723af 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.182547 # Number of seconds simulated -sim_ticks 182546630500 # Number of ticks simulated +sim_seconds 0.181677 # Number of seconds simulated +sim_ticks 181676511500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66837 # Simulator instruction rate (inst/s) -host_tick_rate 20255145 # Simulator tick rate (ticks/s) -host_mem_usage 257744 # Number of bytes of host memory used -host_seconds 9012.36 # Real time elapsed on the host -sim_insts 602359825 # Number of instructions simulated +host_inst_rate 82416 # Simulator instruction rate (inst/s) +host_tick_rate 24857445 # Simulator tick rate (ticks/s) +host_mem_usage 257796 # Number of bytes of host memory used +host_seconds 7308.74 # Real time elapsed on the host +sim_insts 602359820 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 365093262 # number of cpu cycles simulated +system.cpu.numCycles 363353024 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 94055134 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86414920 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3979081 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 88956702 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 82512166 # Number of BTB hits +system.cpu.BPredUnit.lookups 93642406 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86055517 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3937297 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 88612742 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 82226729 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1838122 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1832 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 80667890 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 724099412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94055134 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84350288 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163986224 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21484785 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 102787887 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1811116 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1799 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 80077128 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 720176236 # Number of instructions fetch has processed +system.cpu.fetch.Branches 93642406 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84037845 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163199656 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20933611 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102893232 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 614 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 78002853 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1602878 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 364227401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.127111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.977166 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 623 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 77424762 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1579270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 362477887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.976296 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 200241339 54.98% 54.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25976483 7.13% 62.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 20067114 5.51% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25160816 6.91% 74.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12370660 3.40% 77.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13978922 3.84% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4846811 1.33% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7981089 2.19% 85.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53604167 14.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199278398 54.98% 54.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25830413 7.13% 62.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 19932307 5.50% 67.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25118126 6.93% 74.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12539166 3.46% 77.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13666852 3.77% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4829528 1.33% 83.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7994396 2.21% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53288701 14.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 364227401 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257619 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.983327 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 103328819 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 82990379 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 141956916 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19169051 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16782236 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6955768 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 2559 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 762233872 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 7095 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 16782236 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 116716310 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10162193 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109463 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 147645122 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72812077 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 747464015 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 176 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 58909213 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10051058 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 590 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 771173910 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3477020106 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3477019978 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 362477887 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257717 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.982029 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 102756406 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83077250 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 141158544 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19181042 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16304645 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6938686 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2613 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 758024516 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7262 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 16304645 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 116075491 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10185612 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 146924183 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72878598 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 743558817 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 188 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 58921601 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10117687 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 591 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 767454765 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3458233737 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3458233609 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417426 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 143756479 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6432 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6428 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 129949589 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 185066010 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 85818254 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 23013256 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30486769 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 718960040 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7404 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 670280843 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 854799 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 116155760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 288576013 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 364227401 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.840281 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.715695 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417418 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 140037342 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6399 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6398 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 130096693 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 183828757 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85345746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 25811031 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37497456 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 715547655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7366 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 667339389 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 840250 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 112563133 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 285197370 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1065 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 362477887 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.841049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.675765 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 91766913 25.19% 25.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93871528 25.77% 50.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 74118513 20.35% 71.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 44924126 12.33% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 26194132 7.19% 90.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19078510 5.24% 96.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7890026 2.17% 98.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 5178547 1.42% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1205106 0.33% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89414922 24.67% 24.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90190265 24.88% 49.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 79396670 21.90% 71.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 45359007 12.51% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28036434 7.73% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16328709 4.50% 96.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8232346 2.27% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5060866 1.40% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 458668 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 364227401 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 362477887 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 168001 4.86% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2622016 75.82% 80.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 668303 19.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 175813 5.16% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2586346 75.94% 81.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 643459 18.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 415768758 62.03% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175425484 26.17% 88.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79080039 11.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 414934483 62.18% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6549 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174108289 26.09% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 78290065 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 670280843 # Type of FU issued -system.cpu.iq.rate 1.835917 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3458320 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005160 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1709102170 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 835787693 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 655814402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 667339389 # Type of FU issued +system.cpu.iq.rate 1.836614 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3405618 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005103 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1701402497 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 828782976 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 653330026 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 673739143 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 670744987 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 28975081 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28288943 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 36113410 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 129451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 665732 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 15597236 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34876158 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 159827 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 665311 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 15124729 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 16028 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12631 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15440 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12578 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16782236 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 788804 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 51690 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 719036936 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2011497 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 185066010 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 85818254 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6071 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13145 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5072 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 665732 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4120759 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 486329 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4607088 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 662401467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171983852 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7879376 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16304645 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 784511 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 50454 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 715624477 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2065189 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 183828757 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85345746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6034 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5066 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 665311 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4094363 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 486296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4580659 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659689382 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170637671 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7650007 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 69492 # number of nop insts executed -system.cpu.iew.exec_refs 249361026 # number of memory reference insts executed -system.cpu.iew.exec_branches 77022435 # Number of branches executed -system.cpu.iew.exec_stores 77377174 # Number of stores executed -system.cpu.iew.exec_rate 1.814335 # Inst execution rate -system.cpu.iew.wb_sent 657949131 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 655814418 # cumulative count of insts written-back -system.cpu.iew.wb_producers 425644511 # num instructions producing a value -system.cpu.iew.wb_consumers 661906658 # num instructions consuming a value +system.cpu.iew.exec_nop 69456 # number of nop insts executed +system.cpu.iew.exec_refs 247330517 # number of memory reference insts executed +system.cpu.iew.exec_branches 76920251 # Number of branches executed +system.cpu.iew.exec_stores 76692846 # Number of stores executed +system.cpu.iew.exec_rate 1.815560 # Inst execution rate +system.cpu.iew.wb_sent 655349780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 653330042 # cumulative count of insts written-back +system.cpu.iew.wb_producers 425170180 # num instructions producing a value +system.cpu.iew.wb_consumers 661395893 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.796293 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.643058 # average fanout of values written-back +system.cpu.iew.wb_rate 1.798059 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359876 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 116686609 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4038424 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 347445166 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.733683 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.123903 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359871 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 113270616 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6301 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3996549 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 346173243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.740053 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.116155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113764130 32.74% 32.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 109130175 31.41% 64.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 49680788 14.30% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10344875 2.98% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23361064 6.72% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14153772 4.07% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8154815 2.35% 94.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1152882 0.33% 94.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 17702665 5.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 112054418 32.37% 32.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 109168598 31.54% 63.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49782434 14.38% 78.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10491888 3.03% 81.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23443534 6.77% 88.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14637280 4.23% 92.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8029663 2.32% 94.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1511197 0.44% 95.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17054231 4.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 347445166 # Number of insts commited each cycle -system.cpu.commit.count 602359876 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 346173243 # Number of insts commited each cycle +system.cpu.commit.count 602359871 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173617 # Number of memory references committed -system.cpu.commit.loads 148952599 # Number of loads committed +system.cpu.commit.refs 219173615 # Number of memory references committed +system.cpu.commit.loads 148952598 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828606 # Number of branches committed +system.cpu.commit.branches 70828605 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522659 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522655 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 17702665 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 17054231 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1048788374 # The number of ROB reads -system.cpu.rob.rob_writes 1454922610 # The number of ROB writes -system.cpu.timesIdled 36904 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 865861 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359825 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359825 # Number of Instructions Simulated -system.cpu.cpi 0.606105 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.606105 # CPI: Total CPI of All Threads -system.cpu.ipc 1.649879 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.649879 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3307885763 # number of integer regfile reads -system.cpu.int_regfile_writes 680907350 # number of integer regfile writes +system.cpu.rob.rob_reads 1044748887 # The number of ROB reads +system.cpu.rob.rob_writes 1447602374 # The number of ROB writes +system.cpu.timesIdled 36933 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 875137 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359820 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359820 # Number of Instructions Simulated +system.cpu.cpi 0.603216 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.603216 # CPI: Total CPI of All Threads +system.cpu.ipc 1.657781 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.657781 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3292742614 # number of integer regfile reads +system.cpu.int_regfile_writes 679039343 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 966917605 # number of misc regfile reads -system.cpu.misc_regfile_writes 2666 # number of misc regfile writes -system.cpu.icache.replacements 48 # number of replacements -system.cpu.icache.tagsinuse 654.116997 # Cycle average of tags in use -system.cpu.icache.total_refs 78001834 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 767 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 101697.306389 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 961073357 # number of misc regfile reads +system.cpu.misc_regfile_writes 2664 # number of misc regfile writes +system.cpu.icache.replacements 52 # number of replacements +system.cpu.icache.tagsinuse 658.859257 # Cycle average of tags in use +system.cpu.icache.total_refs 77423742 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 99644.455598 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 654.116997 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.319393 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 78001834 # number of ReadReq hits -system.cpu.icache.demand_hits 78001834 # number of demand (read+write) hits -system.cpu.icache.overall_hits 78001834 # number of overall hits -system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses -system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1019 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 35576500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 35576500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 35576500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 78002853 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 78002853 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 78002853 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 658.859257 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.321709 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 77423742 # number of ReadReq hits +system.cpu.icache.demand_hits 77423742 # number of demand (read+write) hits +system.cpu.icache.overall_hits 77423742 # number of overall hits +system.cpu.icache.ReadReq_misses 1020 # number of ReadReq misses +system.cpu.icache.demand_misses 1020 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1020 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35800500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35800500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 77424762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 77424762 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 77424762 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34913.150147 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34913.150147 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34913.150147 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35098.529412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35098.529412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35098.529412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 252 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 252 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 252 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 767 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 767 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 767 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 243 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 243 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 243 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 777 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 777 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 777 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 26271000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 26271000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 26271000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26636000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26636000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26636000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34251.629726 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34280.566281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34280.566281 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440983 # number of replacements -system.cpu.dcache.tagsinuse 4094.790768 # Cycle average of tags in use -system.cpu.dcache.total_refs 209375241 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 445079 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 470.422646 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 87857000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.790768 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 141476381 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67896188 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1340 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1332 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 209372569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 209372569 # number of overall hits -system.cpu.dcache.ReadReq_misses 248779 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1521343 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 10 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1770122 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1770122 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3280245000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26835404025 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 198500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 30115649025 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30115649025 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 141725160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 440951 # number of replacements +system.cpu.dcache.tagsinuse 4094.785016 # Cycle average of tags in use +system.cpu.dcache.total_refs 208890975 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445047 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 469.368348 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87843000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.785016 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999703 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 140815101 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 68073201 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1331 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 208888302 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 208888302 # number of overall hits +system.cpu.dcache.ReadReq_misses 248858 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1344330 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 9 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1593188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1593188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3280375500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26109782527 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 194000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 29390158027 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 29390158027 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 141063959 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1350 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1332 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 211142691 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 211142691 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001755 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.021916 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.007407 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008384 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008384 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13185.377383 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17639.285832 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 19850 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17013.318305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17013.318305 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 1351 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1331 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 210481490 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 210481490 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.019366 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.006662 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.007569 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.007569 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13181.716079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19422.152691 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 21555.555556 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18447.388524 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18447.388524 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked @@ -422,70 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 395060 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 51069 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1273974 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 10 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1325043 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1325043 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197710 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247369 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 445079 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 445079 # number of overall MSHR misses +system.cpu.dcache.writebacks 395037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51168 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1096973 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 9 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1148141 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1148141 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197690 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247357 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445047 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445047 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1624301000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2561171527 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4185472527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4185472527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1624799500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2561111027 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4185910527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4185910527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001395 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002108 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8215.573314 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.647898 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8218.926096 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.905598 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9405.547115 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72980 # number of replacements -system.cpu.l2cache.tagsinuse 17828.973663 # Cycle average of tags in use -system.cpu.l2cache.total_refs 421802 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88512 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.765478 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72983 # number of replacements +system.cpu.l2cache.tagsinuse 17823.829612 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421659 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88508 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.764078 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1911.988295 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15916.985368 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058349 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.485748 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165669 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 395060 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 188996 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 354665 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 354665 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32802 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58379 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91181 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91181 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1126009000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2004629500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3130638500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3130638500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 198471 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 395060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247375 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445846 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445846 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165274 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235994 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204512 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204512 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34327.449546 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34338.195241 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34334.329520 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34334.329520 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1903.131187 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15920.698425 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058079 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485861 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165659 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395037 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 188979 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354638 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354638 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32805 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58381 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91186 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91186 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126836000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2004580000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3131416000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3131416000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198464 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247360 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445824 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445824 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165294 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.236016 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204534 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204534 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34349.519890 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.171015 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34340.973395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34340.973395 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -494,28 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58140 # number of writebacks +system.cpu.l2cache.writebacks 58139 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32793 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58379 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91172 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91172 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32796 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58381 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91177 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91177 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1019413500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823005500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2842419000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2842419000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1020208500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822855000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2843063500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2843063500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235994 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204492 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204492 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31086.314152 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31227.076517 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165249 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236016 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204513 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204513 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.711306 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31223.428855 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31181.805719 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 589c8ec4c..a3848a023 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:08:13 -gem5 started Jul 8 2011 18:26:23 +gem5 compiled Jul 18 2011 18:04:45 +gem5 started Jul 18 2011 18:04:49 gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 563588156500 because target called exit() +Exiting @ tick 568878317500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index d52982e26..cb1a626e1 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,252 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.563588 # Number of seconds simulated -sim_ticks 563588156500 # Number of ticks simulated +sim_seconds 0.568878 # Number of seconds simulated +sim_ticks 568878317500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64765 # Simulator instruction rate (inst/s) -host_tick_rate 25968064 # Simulator tick rate (ticks/s) -host_mem_usage 251156 # Number of bytes of host memory used -host_seconds 21703.13 # Real time elapsed on the host +host_inst_rate 127390 # Simulator instruction rate (inst/s) +host_tick_rate 51557660 # Simulator tick rate (ticks/s) +host_mem_usage 254284 # Number of bytes of host memory used +host_seconds 11033.83 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1127176314 # number of cpu cycles simulated +system.cpu.numCycles 1137756636 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 108002078 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 96458356 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5419443 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 104845979 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 103526655 # Number of BTB hits +system.cpu.BPredUnit.lookups 106888514 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 95381218 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5420176 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 103841112 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 102522993 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1233 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 1230 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 182291160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1787208152 # Number of instructions fetch has processed -system.cpu.fetch.Branches 108002078 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103527888 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 384452467 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 39306331 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 526780202 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 13 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1622 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 177554256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1007248 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1126809005 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.590132 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.768689 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180638334 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1773593568 # Number of instructions fetch has processed +system.cpu.fetch.Branches 106888514 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 102524223 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 381465937 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37837382 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 543268181 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1639 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 176102907 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 948661 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1137451065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.563275 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.753191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 742356538 65.88% 65.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 85341479 7.57% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 46929286 4.16% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24554385 2.18% 79.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 34670829 3.08% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34912206 3.10% 85.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 15372705 1.36% 87.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7941055 0.70% 88.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 134730522 11.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 755985128 66.46% 66.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 84858619 7.46% 73.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 46317326 4.07% 78.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24386522 2.14% 80.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 34286806 3.01% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 34702861 3.05% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 15288834 1.34% 87.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7898837 0.69% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 133726132 11.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1126809005 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.095816 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.585562 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 243483307 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 469211226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 329903735 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50927196 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 33283541 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1773785354 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 33283541 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 303199519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 121005551 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66378557 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 319425533 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 283516304 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1755376544 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 158155356 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 64460520 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 40367810 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1464774447 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2963679380 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2929648556 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34030824 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1137451065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093947 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.558851 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 242051252 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 485212822 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 328784553 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49325481 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 32076957 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1761674668 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 32076957 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 305517434 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 121834770 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66846353 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 312365178 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 298810373 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1743986914 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 179337186 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 63010596 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 40441846 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1455333902 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2943882462 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2909924571 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 33957891 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 220003995 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3335169 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3335909 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 507197291 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 473956598 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 190918944 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 402921595 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 162419763 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1626020867 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3211854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1494042135 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 206172 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 223169277 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 302404283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 968183 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1126809005 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.325905 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.154571 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 210563450 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3348344 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3348760 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 542381303 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 470273369 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 190181130 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 405202372 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 165490113 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1617272450 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3218242 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1489328778 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 214120992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 291680058 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 974571 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1137451065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.140672 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 292007700 25.91% 25.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 411780858 36.54% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 263168713 23.36% 85.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 101528512 9.01% 94.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43990451 3.90% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 11374555 1.01% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2356617 0.21% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 448758 0.04% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152841 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 308893636 27.16% 27.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 389103497 34.21% 61.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 284410316 25.00% 86.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 106768220 9.39% 95.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 33533421 2.95% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12093348 1.06% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2169743 0.19% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 349965 0.03% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128919 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1126809005 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1137451065 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 276548 8.36% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 151088 4.56% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2447279 73.94% 86.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 434986 13.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 267660 8.55% 8.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 151678 4.84% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2460340 78.58% 91.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 251345 8.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 893364457 59.80% 59.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2623126 0.18% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 426278234 28.53% 88.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171776318 11.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 892252171 59.91% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2624686 0.18% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 423006461 28.40% 88.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171445460 11.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1494042135 # Type of FU issued -system.cpu.iq.rate 1.325473 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3309901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002215 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4100596899 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1843738328 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1474876541 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17812449 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9274219 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8514769 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1488163197 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9188839 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 140932048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1489328778 # Type of FU issued +system.cpu.iq.rate 1.309005 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3131023 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002102 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4101702594 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1825725243 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1471768719 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17605097 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9240911 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8506597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1483444207 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9015594 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 136711373 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 71443754 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20242 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 695476 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24070802 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 67760525 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20730 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 356316 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 23332988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 267 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39866 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 60 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 46765 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 33283541 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2642816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 166342 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1732819113 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4184603 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 473956598 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 190918944 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3110022 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 73740 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9229 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 695476 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5255230 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 461002 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5716232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1486789752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 422968775 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7252383 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 32076957 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2310683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98308 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1723301655 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4186060 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 470273369 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 190181130 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3115724 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 51873 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4910 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 356316 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5266619 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 459051 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5725670 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1483096593 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 420520679 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6232185 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 103586392 # number of nop insts executed -system.cpu.iew.exec_refs 593427321 # number of memory reference insts executed -system.cpu.iew.exec_branches 90250072 # Number of branches executed -system.cpu.iew.exec_stores 170458546 # Number of stores executed -system.cpu.iew.exec_rate 1.319039 # Inst execution rate -system.cpu.iew.wb_sent 1484841678 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1483391310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1170940676 # num instructions producing a value -system.cpu.iew.wb_consumers 1222219030 # num instructions consuming a value +system.cpu.iew.exec_nop 102810963 # number of nop insts executed +system.cpu.iew.exec_refs 590732580 # number of memory reference insts executed +system.cpu.iew.exec_branches 90117242 # Number of branches executed +system.cpu.iew.exec_stores 170211901 # Number of stores executed +system.cpu.iew.exec_rate 1.303527 # Inst execution rate +system.cpu.iew.wb_sent 1481375672 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1480275316 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1168908244 # num instructions producing a value +system.cpu.iew.wb_consumers 1211941530 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.316024 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.958045 # average fanout of values written-back +system.cpu.iew.wb_rate 1.301047 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.964492 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 243200723 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 233686324 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5419443 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1093526075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.362129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.820328 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5420176 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1105374719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.347528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786900 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 386645364 35.36% 35.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 450467032 41.19% 76.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52266567 4.78% 81.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 95504499 8.73% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 32424023 2.97% 93.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8856558 0.81% 93.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 27482733 2.51% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9900040 0.91% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29979259 2.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 387659384 35.07% 35.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 461508986 41.75% 76.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51139183 4.63% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 98630108 8.92% 90.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 32299027 2.92% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8730687 0.79% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 27864776 2.52% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10533124 0.95% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 27009444 2.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1093526075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1105374719 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -256,50 +255,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29979259 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 27009444 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2796205964 # The number of ROB reads -system.cpu.rob.rob_writes 3498772696 # The number of ROB writes -system.cpu.timesIdled 11331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 367309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2801510024 # The number of ROB reads +system.cpu.rob.rob_writes 3478548339 # The number of ROB writes +system.cpu.timesIdled 10892 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 305571 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.801916 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.801916 # CPI: Total CPI of All Threads -system.cpu.ipc 1.247014 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.247014 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2006108330 # number of integer regfile reads -system.cpu.int_regfile_writes 1306606440 # number of integer regfile writes -system.cpu.fp_regfile_reads 16974388 # number of floating regfile reads -system.cpu.fp_regfile_writes 10441040 # number of floating regfile writes -system.cpu.misc_regfile_reads 599300610 # number of misc regfile reads +system.cpu.cpi 0.809443 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809443 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235417 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235417 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2001717837 # number of integer regfile reads +system.cpu.int_regfile_writes 1303407681 # number of integer regfile writes +system.cpu.fp_regfile_reads 16935756 # number of floating regfile reads +system.cpu.fp_regfile_writes 10440358 # number of floating regfile writes +system.cpu.misc_regfile_reads 596613763 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.icache.replacements 162 # number of replacements -system.cpu.icache.tagsinuse 1043.489653 # Cycle average of tags in use -system.cpu.icache.total_refs 177552476 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 136894.738628 # Average number of references to valid blocks. +system.cpu.icache.replacements 165 # number of replacements +system.cpu.icache.tagsinuse 1040.317886 # Cycle average of tags in use +system.cpu.icache.total_refs 176101137 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1300 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 135462.413077 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1043.489653 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.509516 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 177552476 # number of ReadReq hits -system.cpu.icache.demand_hits 177552476 # number of demand (read+write) hits -system.cpu.icache.overall_hits 177552476 # number of overall hits -system.cpu.icache.ReadReq_misses 1780 # number of ReadReq misses -system.cpu.icache.demand_misses 1780 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1780 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 62084000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 62084000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 62084000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 177554256 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 177554256 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 177554256 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1040.317886 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.507968 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 176101137 # number of ReadReq hits +system.cpu.icache.demand_hits 176101137 # number of demand (read+write) hits +system.cpu.icache.overall_hits 176101137 # number of overall hits +system.cpu.icache.ReadReq_misses 1770 # number of ReadReq misses +system.cpu.icache.demand_misses 1770 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1770 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 61911500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 61911500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 61911500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 176102907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 176102907 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 176102907 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34878.651685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34878.651685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34878.651685 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34978.248588 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34978.248588 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34978.248588 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,140 +308,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 482 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 482 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 469 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 469 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 469 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1301 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1301 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1301 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45208500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45208500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45208500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45277500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45277500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45277500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34829.352851 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34802.075327 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34802.075327 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34802.075327 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 475456 # number of replacements -system.cpu.dcache.tagsinuse 4095.394464 # Cycle average of tags in use -system.cpu.dcache.total_refs 446158150 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 479552 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 930.364486 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 131008000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.394464 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999852 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 281189388 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 164967443 # number of WriteReq hits +system.cpu.dcache.replacements 475458 # number of replacements +system.cpu.dcache.tagsinuse 4095.400143 # Cycle average of tags in use +system.cpu.dcache.total_refs 447983825 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479554 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 934.167633 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131001000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.400143 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999854 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 282962670 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 165019836 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 446156831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 446156831 # number of overall hits -system.cpu.dcache.ReadReq_misses 816269 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1879373 # number of WriteReq misses +system.cpu.dcache.demand_hits 447982506 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 447982506 # number of overall hits +system.cpu.dcache.ReadReq_misses 815560 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1826980 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2695642 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2695642 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11972698500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28858348258 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 40831046758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 40831046758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 282005657 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 2642540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2642540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 10724956500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26607670410 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency 37332626910 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 37332626910 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 283778230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 448852473 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 448852473 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002895 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.011264 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 450625046 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 450625046 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002874 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010950 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.006006 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.006006 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14667.589361 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15355.306402 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15147.058385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15147.058385 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.005864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.005864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13150.419957 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14563.744765 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency 14127.554137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 14127.554137 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2375 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 426829 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 604140 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1611957 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2216097 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2216097 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 212129 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 267416 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426814 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 603466 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1559527 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2162993 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2162993 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212094 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267453 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 479545 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 479545 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479547 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1590330500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3553768773 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5144099273 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5144099273 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1622799000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3442234519 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5065033519 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5065033519 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000752 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000747 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001603 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001068 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001068 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.997110 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13289.289994 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001064 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001064 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7651.319698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12870.427772 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10562.121166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10562.121166 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75860 # number of replacements -system.cpu.l2cache.tagsinuse 17695.918496 # Cycle average of tags in use -system.cpu.l2cache.total_refs 464712 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91372 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.085934 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75848 # number of replacements +system.cpu.l2cache.tagsinuse 17699.311990 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464479 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91359 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.084108 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1941.337449 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15754.581047 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.059245 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.480792 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 179775 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 426829 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 206986 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 386761 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 386761 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33652 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60437 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94089 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94089 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1145407000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2080656500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3226063500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3226063500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 213427 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 426829 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 267423 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 480850 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 480850 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.157675 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.225998 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.195672 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.195672 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.818020 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34426.865993 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34287.360903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34287.360903 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1967.262312 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15732.049678 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.060036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480104 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179745 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426814 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 207036 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386781 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386781 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33650 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60424 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94074 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94074 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1149817000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2071878000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3221695000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3221695000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426814 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267460 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480855 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480855 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157689 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.225918 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195639 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195639 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34169.895988 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.991129 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34246.391139 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34246.391139 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,27 +450,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59276 # number of writebacks +system.cpu.l2cache.writebacks 59264 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33652 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60437 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94089 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94089 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33650 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60424 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94074 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94074 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043368500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893759500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2937128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2937128000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1044115000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1884920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2929035000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2929035000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157675 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225998 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.195672 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.195672 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.650541 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31334.439168 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157689 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225918 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195639 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195639 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31028.677563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31194.889448 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31135.435933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31135.435933 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 621f09656..a4b9477d1 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:18:15 -gem5 started Jul 8 2011 19:12:13 +gem5 compiled Jul 15 2011 18:01:24 +gem5 started Jul 15 2011 20:50:21 gem5 executing on u200439-lin.austin.arm.com command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1062,4 +1062,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 746999805000 because target called exit() +Exiting @ tick 749294021000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index b33faa135..06ad1be7c 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.747000 # Number of seconds simulated -sim_ticks 746999805000 # Number of ticks simulated +sim_seconds 0.749294 # Number of seconds simulated +sim_ticks 749294021000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52755 # Simulator instruction rate (inst/s) -host_tick_rate 24303440 # Simulator tick rate (ticks/s) -host_mem_usage 253604 # Number of bytes of host memory used -host_seconds 30736.38 # Real time elapsed on the host +host_inst_rate 60097 # Simulator instruction rate (inst/s) +host_tick_rate 27771108 # Simulator tick rate (ticks/s) +host_mem_usage 253640 # Number of bytes of host memory used +host_seconds 26981.06 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1493999611 # number of cpu cycles simulated +system.cpu.numCycles 1498588043 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 183981284 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 183981284 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7273832 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 175979129 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 174823422 # Number of BTB hits +system.cpu.BPredUnit.lookups 174353147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 174353147 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 8954437 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 165220115 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 164182726 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 199101325 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1418187336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 183981284 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174823422 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 411931747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 120581871 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 775842898 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 439 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 187933146 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1412014 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1493732032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.734289 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.070436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 197081055 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1427085390 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174353147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 164182726 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 405643185 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 122961003 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 787624963 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 296 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 184521623 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1125658 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1498287760 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.715646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.067557 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1084944891 72.63% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27695152 1.85% 74.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18612240 1.25% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 16931022 1.13% 76.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 30747713 2.06% 78.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 17254642 1.16% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38005540 2.54% 82.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38774045 2.60% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220766787 14.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1095772488 73.13% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26898081 1.80% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18204566 1.22% 76.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 17325497 1.16% 77.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23844032 1.59% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 17164690 1.15% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40138916 2.68% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38301790 2.56% 85.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220637700 14.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1493732032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123147 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.949255 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 299784199 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 683008972 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 314849688 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 89233622 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 106855551 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2563435147 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 106855551 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 360599256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 188215169 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3353 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 328972953 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 509085750 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2506842740 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 353300714 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 135977984 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2507364398 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6062894034 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6062889786 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4248 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1498287760 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116345 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952287 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 300082946 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 691709075 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 302993844 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 95563685 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 107938210 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2548886917 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 107938210 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 357219052 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 188499779 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3288 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 326836039 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 517791392 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2482037348 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3801 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 365556322 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 131873603 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2483397127 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6018409804 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6018402452 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7352 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 889369748 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 162 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 162 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 860776772 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 644217579 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 260359160 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 564219162 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 219825369 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2437807916 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 95 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1879814445 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 473311 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 816283522 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1731057121 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1493732032 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.258468 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.208875 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 865402477 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 169 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 866525950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 641640659 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 260570368 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 562700768 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 217406187 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2410485981 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 96 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1860645622 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 297905 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 788955121 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1689446934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1498287760 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.241848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.192555 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 432191127 28.93% 28.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 591005322 39.57% 68.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 246823296 16.52% 85.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 135579868 9.08% 94.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 59328852 3.97% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 22913004 1.53% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4862881 0.33% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 856243 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 171439 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 431380009 28.79% 28.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 604501817 40.35% 69.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252266719 16.84% 85.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 123988851 8.28% 94.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 58817201 3.93% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20817096 1.39% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5535754 0.37% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 767498 0.05% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 212815 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1493732032 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1498287760 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 145103 3.04% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3853337 80.69% 83.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 777052 16.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 150800 3.27% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3625649 78.65% 81.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 833140 18.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26397138 1.40% 1.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212079345 64.48% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 449002654 23.89% 89.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192335308 10.23% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28076414 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1193303219 64.13% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 446918343 24.02% 89.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192347646 10.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1879814445 # Type of FU issued -system.cpu.iq.rate 1.258243 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4775492 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002540 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5258609690 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3260533161 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1853774167 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1274 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1860645622 # Type of FU issued +system.cpu.iq.rate 1.241599 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4609589 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5224486461 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3205506305 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1835062624 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 37 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2036 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1858192780 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 120571651 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 1837178777 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 118533940 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 225175454 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6636 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6448917 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 72173103 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 222598534 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4428 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6067505 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 72384311 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 67 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30868 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30883 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 106855551 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4276997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 154006 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2437808011 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3809571 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 644217579 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 260359160 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 95 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 92996 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6448917 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4522013 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2931532 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7453545 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1858657499 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 444749829 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21156946 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 107938210 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4267962 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 121894 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2410486077 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 630348 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 641640659 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 260570368 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 96 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66625 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6067505 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4521579 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4614873 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9136452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1840276566 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 443019520 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 20369056 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 636612361 # number of memory reference insts executed -system.cpu.iew.exec_branches 111987428 # Number of branches executed -system.cpu.iew.exec_stores 191862532 # Number of stores executed -system.cpu.iew.exec_rate 1.244082 # Inst execution rate -system.cpu.iew.wb_sent 1856615108 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1853774179 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1441885120 # num instructions producing a value -system.cpu.iew.wb_consumers 2107634936 # num instructions consuming a value +system.cpu.iew.exec_refs 634826939 # number of memory reference insts executed +system.cpu.iew.exec_branches 111934330 # Number of branches executed +system.cpu.iew.exec_stores 191807419 # Number of stores executed +system.cpu.iew.exec_rate 1.228007 # Inst execution rate +system.cpu.iew.wb_sent 1838313315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1835062636 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1427807499 # num instructions producing a value +system.cpu.iew.wb_consumers 2086812885 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.240813 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.684125 # average fanout of values written-back +system.cpu.iew.wb_rate 1.224528 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.684205 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 816323432 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 789002361 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7273892 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1386876481 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.169170 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394530 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8954478 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1390349550 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.166249 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.425241 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 510181205 36.79% 36.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 529583219 38.19% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 122943422 8.86% 83.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 138376651 9.98% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 42654329 3.08% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24144434 1.74% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5177613 0.37% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2036062 0.15% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11779546 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 517686759 37.23% 37.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 532094045 38.27% 75.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 126340876 9.09% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122997225 8.85% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 42691092 3.07% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23602651 1.70% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4988906 0.36% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10568517 0.76% 99.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 9379479 0.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1386876481 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1390349550 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11779546 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 9379479 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3812914349 # The number of ROB reads -system.cpu.rob.rob_writes 4982493999 # The number of ROB writes -system.cpu.timesIdled 44138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 267579 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3791466414 # The number of ROB reads +system.cpu.rob.rob_writes 4929477020 # The number of ROB writes +system.cpu.timesIdled 44919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 300283 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.921372 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.921372 # CPI: Total CPI of All Threads -system.cpu.ipc 1.085338 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.085338 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3240601354 # number of integer regfile reads -system.cpu.int_regfile_writes 1846777221 # number of integer regfile writes +system.cpu.cpi 0.924202 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.924202 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082014 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082014 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3236351438 # number of integer regfile reads +system.cpu.int_regfile_writes 1827281055 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 936479302 # number of misc regfile reads +system.cpu.misc_regfile_reads 926454727 # number of misc regfile reads system.cpu.icache.replacements 14 # number of replacements -system.cpu.icache.tagsinuse 820.004984 # Cycle average of tags in use -system.cpu.icache.total_refs 187931883 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 206973.439427 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 821.249711 # Cycle average of tags in use +system.cpu.icache.total_refs 184520340 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 203664.834437 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 820.004984 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.400393 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 187931883 # number of ReadReq hits -system.cpu.icache.demand_hits 187931883 # number of demand (read+write) hits -system.cpu.icache.overall_hits 187931883 # number of overall hits -system.cpu.icache.ReadReq_misses 1263 # number of ReadReq misses -system.cpu.icache.demand_misses 1263 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1263 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44191500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44191500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44191500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 187933146 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 187933146 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 187933146 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 821.249711 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.401001 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 184520379 # number of ReadReq hits +system.cpu.icache.demand_hits 184520379 # number of demand (read+write) hits +system.cpu.icache.overall_hits 184520379 # number of overall hits +system.cpu.icache.ReadReq_misses 1244 # number of ReadReq misses +system.cpu.icache.demand_misses 1244 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43837000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43837000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43837000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 184521623 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 184521623 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 184521623 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34989.311164 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34989.311164 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34989.311164 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35238.745981 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35238.745981 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35238.745981 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,159 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 355 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 355 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 355 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32070500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32070500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32070500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 32023000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32023000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32023000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35319.933921 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35267.621145 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35267.621145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35267.621145 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459464 # number of replacements -system.cpu.dcache.tagsinuse 4095.142322 # Cycle average of tags in use -system.cpu.dcache.total_refs 510865684 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463560 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1102.048675 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317747000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.142322 # Average occupied blocks per context +system.cpu.dcache.replacements 459267 # number of replacements +system.cpu.dcache.tagsinuse 4095.145013 # Cycle average of tags in use +system.cpu.dcache.total_refs 511187603 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463363 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1103.211959 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317737000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.145013 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 323944700 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186920984 # number of WriteReq hits -system.cpu.dcache.demand_hits 510865684 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 510865684 # number of overall hits -system.cpu.dcache.ReadReq_misses 217118 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1265073 # number of WriteReq misses -system.cpu.dcache.demand_misses 1482191 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1482191 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2201155000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24662905498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 26864060498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 26864060498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 324161818 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 324252389 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186935214 # number of WriteReq hits +system.cpu.dcache.demand_hits 511187603 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 511187603 # number of overall hits +system.cpu.dcache.ReadReq_misses 216893 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1250843 # number of WriteReq misses +system.cpu.dcache.demand_misses 1467736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1467736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2202140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24456528497 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 26658668497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 26658668497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 324469282 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 512347875 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 512347875 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006722 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002893 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002893 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10138.058567 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19495.242961 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18124.560531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18124.560531 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1608500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 471924500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 447 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29514 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3598.434004 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15989.852273 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses 512655339 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 512655339 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000668 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006647 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.002863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002863 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10153.116975 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19552.036904 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18163.122317 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18163.122317 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1683000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 471232500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 455 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29502 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3698.901099 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15972.900142 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 410359 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3236 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1015395 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1018631 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1018631 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213882 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249678 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463560 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463560 # number of overall MSHR misses +system.cpu.dcache.writebacks 410236 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3187 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1001186 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1004373 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1004373 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213706 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249657 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463363 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463363 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1535369000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2499634500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4035003500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4035003500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1537618500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2504912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4042530500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4042530500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.579778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10011.432725 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7195.017922 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10033.413844 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8724.327363 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8724.327363 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73641 # number of replacements -system.cpu.l2cache.tagsinuse 18052.437933 # Cycle average of tags in use -system.cpu.l2cache.total_refs 453217 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89251 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.078005 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73626 # number of replacements +system.cpu.l2cache.tagsinuse 18020.121122 # Cycle average of tags in use +system.cpu.l2cache.total_refs 453087 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89234 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.077515 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1921.052649 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16131.385284 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058626 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.492291 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181658 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410359 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190902 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 372560 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 372560 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33126 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58782 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91908 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91908 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130437500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2022399000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3152836500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3152836500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214784 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410359 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249684 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464468 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464468 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154229 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235426 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197878 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197878 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34125.384894 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.072982 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34304.266223 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34304.266223 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1915.061823 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16105.059300 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058443 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.491487 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181487 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410236 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190884 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372371 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372371 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33119 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58779 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91898 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91898 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130363000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2022275000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3152638000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3152638000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214606 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410236 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249663 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464269 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464269 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154325 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235433 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197941 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197941 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34130.348139 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.719373 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34305.839082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34305.839082 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 116500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 95 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1076.388889 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1226.315789 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58527 # number of writebacks +system.cpu.l2cache.writebacks 58523 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33126 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58782 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91908 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91908 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33119 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58779 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91898 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91898 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1027129500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1831638000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2858767500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2858767500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026905500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1830910000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2857815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2857815500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154229 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235426 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197878 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197878 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.746966 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31159.844850 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154325 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235433 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197941 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197941 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.537033 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.049831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31097.689830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31097.689830 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |