diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:13 -0800 |
| commit | 0851580aada37c8e1b1d2b695100fbcfaf4e0946 (patch) | |
| tree | 96eea53d6309ddb9f4bfac61767e53bfcdb44037 /tests/long/00.gzip | |
| parent | 1b64bfa933745294667158d0ce22180780b2a22e (diff) | |
| download | gem5-0851580aada37c8e1b1d2b695100fbcfaf4e0946.tar.xz | |
Stats: Re update stats.
Diffstat (limited to 'tests/long/00.gzip')
39 files changed, 464 insertions, 133 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index ed1344dd3..41c6a83e0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index a359bdb55..5ab603e64 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 16:24:53 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 16:40:29 -M5 executing on zizzer +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:50 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 240486239..9ddf470e4 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 207877 # Simulator instruction rate (inst/s) -host_mem_usage 206352 # Number of bytes of host memory used -host_seconds 2720.61 # Real time elapsed on the host -host_tick_rate 59832123 # Simulator tick rate (ticks/s) +host_inst_rate 121046 # Simulator instruction rate (inst/s) +host_mem_usage 226784 # Number of bytes of host memory used +host_seconds 4672.20 # Real time elapsed on the host +host_tick_rate 34840083 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162780 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed +system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed. +system.cpu.commit.COM:int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.COM:loads 114514042 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 153965363 # Number of memory references committed @@ -171,6 +174,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 265 # number of floating regfile reads +system.cpu.fp_regfile_writes 58 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency @@ -270,6 +275,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 3177577 # system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 844691087 # number of integer regfile reads +system.cpu.int_regfile_writes 489153092 # number of integer regfile writes system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +368,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1679 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3330 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1605 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 1800 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 612363224 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1543136462 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 595804344 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 671661588 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ @@ -457,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 17165638 # Nu system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.numCycles 325559560 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full @@ -471,10 +490,14 @@ system.cpu.rename.RENAME:RunCycles 115552585 # Nu system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1958 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 894826947 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 958179178 # The number of ROB reads +system.cpu.rob.rob_writes 1334457472 # The number of ROB writes system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index d0f6032a2..355960d42 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout index 635701ab6..b96d561c3 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:31:02 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:37 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 739ca9c21..4dfa82a45 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6224890 # Simulator instruction rate (inst/s) -host_mem_usage 232016 # Number of bytes of host memory used -host_seconds 96.69 # Real time elapsed on the host -host_tick_rate 3112463113 # Simulator tick rate (ticks/s) +host_inst_rate 1697811 # Simulator instruction rate (inst/s) +host_mem_usage 218112 # Number of bytes of host memory used +host_seconds 354.49 # Real time elapsed on the host +host_tick_rate 848911876 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 601861917 # Number of busy cycles +system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses +system.cpu.num_fp_insts 1520 # number of float instructions +system.cpu.num_fp_register_reads 169 # number of times the floating registers were read +system.cpu.num_fp_register_writes 42 # number of times the floating registers were written +system.cpu.num_func_calls 2395217 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 153970296 # Number of memory references +system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses +system.cpu.num_int_insts 563959696 # number of integer instructions +system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read +system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written +system.cpu.num_load_insts 114516673 # Number of load instructions +system.cpu.num_mem_refs 153970296 # number of memory refs +system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 6ed9b214f..5dbdc6426 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -157,7 +166,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 15443bcd3..5133de4f2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:44:32 -M5 executing on aus-bc2-b15 +M5 compiled Feb 7 2011 01:47:18 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:47:36 +M5 executing on burrito command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index d095a4f5f..0f44a109b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2723974 # Simulator instruction rate (inst/s) -host_mem_usage 239668 # Number of bytes of host memory used -host_seconds 220.95 # Real time elapsed on the host -host_tick_rate 3465167347 # Simulator tick rate (ticks/s) +host_inst_rate 591495 # Simulator instruction rate (inst/s) +host_mem_usage 225828 # Number of bytes of host memory used +host_seconds 1017.52 # Real time elapsed on the host +host_tick_rate 752441266 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.765623 # Number of seconds simulated @@ -232,8 +232,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 59341 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1531246064 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1531246064 # Number of busy cycles +system.cpu.num_conditional_control_insts 58554292 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses +system.cpu.num_fp_insts 1520 # number of float instructions +system.cpu.num_fp_register_reads 169 # number of times the floating registers were read +system.cpu.num_fp_register_writes 42 # number of times the floating registers were written +system.cpu.num_func_calls 2395217 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 153970296 # Number of memory references +system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses +system.cpu.num_int_insts 563959696 # number of integer instructions +system.cpu.num_int_register_reads 801088993 # number of times the integer registers were read +system.cpu.num_int_register_writes 463854847 # number of times the integer registers were written +system.cpu.num_load_insts 114516673 # Number of load instructions +system.cpu.num_mem_refs 153970296 # number of memory refs +system.cpu.num_store_insts 39453623 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 1ca0fc2d1..b2393d69d 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -484,7 +493,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 913163576..c00731590 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 11 2011 18:16:01 -M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip -M5 started Jan 12 2011 02:01:01 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:59:50 +M5 executing on burrito command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index c8f41239c..3c92d3925 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117336 # Simulator instruction rate (inst/s) -host_mem_usage 251760 # Number of bytes of host memory used -host_seconds 5118.46 # Real time elapsed on the host -host_tick_rate 42393313 # Simulator tick rate (ticks/s) +host_inst_rate 115233 # Simulator instruction rate (inst/s) +host_mem_usage 238284 # Number of bytes of host memory used +host_seconds 5211.87 # Real time elapsed on the host +host_tick_rate 41633525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600581394 # Number of instructions simulated sim_seconds 0.216988 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle system.cpu.commit.COM:count 600581394 # Number of instructions committed +system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 531746837 # Number of committed integer instructions. system.cpu.commit.COM:loads 148953025 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 219174038 # Number of memory references committed @@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency @@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 18357789 # system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1741733302 # number of integer regfile reads +system.cpu.int_regfile_writes 500762065 # number of integer regfile writes system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate +system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 661113885 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1748261718 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 638555076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 843800706 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ @@ -470,7 +484,11 @@ system.cpu.memDep0.conflictingLoads 56143840 # Nu system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 960863166 # number of misc regfile reads +system.cpu.misc_regfile_writes 9367 # number of misc regfile writes system.cpu.numCycles 433976628 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full @@ -484,10 +502,14 @@ system.cpu.rename.RENAME:RunCycles 140765492 # Nu system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2146132242 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1130322956 # The number of ROB reads +system.cpu.rob.rob_writes 1461347493 # The number of ROB writes system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini index 04cb6159a..17d38a039 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -52,12 +61,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout index dea298989..f425b3c91 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 19:16:15 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:00:03 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 6361eb760..fb68d0899 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2821771 # Simulator instruction rate (inst/s) -host_mem_usage 253968 # Number of bytes of host memory used -host_seconds 212.84 # Real time elapsed on the host -host_tick_rate 1410937507 # Simulator tick rate (ticks/s) +host_inst_rate 1026292 # Simulator instruction rate (inst/s) +host_mem_usage 229344 # Number of bytes of host memory used +host_seconds 585.20 # Real time elapsed on the host +host_tick_rate 513165203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 600581394 # Number of instructions simulated sim_seconds 0.300302 # Number of seconds simulated @@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 600604284 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 600604284 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 600581394 # Number of instructions executed -system.cpu.num_refs 219174038 # Number of memory references +system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses +system.cpu.num_int_insts 531746837 # number of integer instructions +system.cpu.num_int_register_reads 1690709529 # number of times the integer registers were read +system.cpu.num_int_register_writes 456307392 # number of times the integer registers were written +system.cpu.num_load_insts 148953025 # Number of load instructions +system.cpu.num_mem_refs 219174038 # number of memory refs +system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index 36e9f985b..de769cd56 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr index eabe42249..c1c8fcec5 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,7 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index 38b916fc4..70559ac7d 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 11 2010 18:37:23 -M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip -M5 started Oct 11 2010 18:44:50 -M5 executing on aus-bc3-b4 -command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing +M5 compiled Feb 7 2011 01:56:16 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 01:56:25 +M5 executing on burrito +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index 8e10bdbf4..2b5fb88ae 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 652561 # Simulator instruction rate (inst/s) -host_mem_usage 261720 # Number of bytes of host memory used -host_seconds 917.34 # Real time elapsed on the host -host_tick_rate 868554806 # Simulator tick rate (ticks/s) +host_inst_rate 452045 # Simulator instruction rate (inst/s) +host_mem_usage 237056 # Number of bytes of host memory used +host_seconds 1324.25 # Real time elapsed on the host +host_tick_rate 601669731 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated sim_seconds 0.796760 # Number of seconds simulated @@ -242,8 +242,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 57886 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1593519872 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1593519872 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 598619824 # Number of instructions executed -system.cpu.num_refs 219174038 # Number of memory references +system.cpu.num_int_alu_accesses 531746837 # Number of integer alu accesses +system.cpu.num_int_insts 531746837 # number of integer instructions +system.cpu.num_int_register_reads 1837343724 # number of times the integer registers were read +system.cpu.num_int_register_writes 456308029 # number of times the integer registers were written +system.cpu.num_load_insts 148953025 # Number of load instructions +system.cpu.num_mem_refs 219174038 # number of memory refs +system.cpu.num_store_insts 70221013 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 02ce84b2d..239140dc5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index df93e233e..44a2a20b1 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 17 2011 21:17:52 -M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase -M5 started Jan 17 2011 21:17:55 -M5 executing on zizzer +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index c2bc04472..2fc2b1f97 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 144426 # Simulator instruction rate (inst/s) -host_mem_usage 207996 # Number of bytes of host memory used -host_seconds 9732.45 # Real time elapsed on the host -host_tick_rate 61799305 # Simulator tick rate (ticks/s) +host_inst_rate 165526 # Simulator instruction rate (inst/s) +host_mem_usage 228372 # Number of bytes of host memory used +host_seconds 8491.76 # Real time elapsed on the host +host_tick_rate 70828550 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.601459 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle system.cpu.commit.COM:count 1489523295 # Number of instructions committed +system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569360986 # Number of memory references committed @@ -160,6 +163,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads +system.cpu.fp_regfile_writes 10422320 # number of floating regfile writes system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency @@ -259,6 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 21427986 # system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1994642284 # number of integer regfile reads +system.cpu.int_regfile_writes 1296237136 # number of integer regfile writes system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -350,6 +357,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate +system.cpu.iq.fp_alu_accesses 9139758 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 17716192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 8503894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9202883 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1476034706 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4152007639 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1463994823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1798910142 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ @@ -430,7 +445,11 @@ system.cpu.memDep0.conflictingLoads 406523724 # Nu system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 596285867 # number of misc regfile reads +system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes system.cpu.numCycles 1202917849 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers @@ -445,10 +464,14 @@ system.cpu.rename.RENAME:RunCycles 329588798 # Nu system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 33734828 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2890766205 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 2859629611 # The number of ROB reads +system.cpu.rob.rob_writes 3448202738 # The number of ROB writes system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 25252561e..0b3b6266f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -57,7 +66,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout index c99734c27..4748a164d 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:19:07 -M5 executing on SC2B0619 +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:14:57 +M5 executing on burrito command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index d04149323..16c920737 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1748575 # Simulator instruction rate (inst/s) -host_mem_usage 185740 # Number of bytes of host memory used -host_seconds 851.85 # Real time elapsed on the host -host_tick_rate 874289976 # Simulator tick rate (ticks/s) +host_inst_rate 1524596 # Simulator instruction rate (inst/s) +host_mem_usage 219684 # Number of bytes of host memory used +host_seconds 977.00 # Real time elapsed on the host +host_tick_rate 762300416 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 0.744764 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 744764119000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1489528239 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1489528239 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234411208 # number of times the integer registers were written +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 9772b8626..9789f7d05 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -152,12 +161,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 78e3d8264..f2b4b3e16 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:28:00 -M5 executing on phenom -command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +M5 compiled Feb 7 2011 02:13:30 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:13:36 +M5 executing on burrito +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 04e7c144d..8bc8178fc 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1333935 # Simulator instruction rate (inst/s) -host_mem_usage 197236 # Number of bytes of host memory used -host_seconds 1116.64 # Real time elapsed on the host -host_tick_rate 1848636408 # Simulator tick rate (ticks/s) +host_inst_rate 594721 # Simulator instruction rate (inst/s) +host_mem_usage 227400 # Number of bytes of host memory used +host_seconds 2504.58 # Real time elapsed on the host +host_tick_rate 824195004 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.064259 # Number of seconds simulated @@ -210,8 +210,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 59035 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1489523295 # Number of instructions executed -system.cpu.num_refs 569365767 # Number of memory references +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234411207 # number of times the integer registers were written +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_store_insts 166850421 # Number of store instructions system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index f7f0c46d4..503c61f1c 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=DerivO3CPU @@ -481,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f9fa6a62e..3dbb4b0b4 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 16:34:44 -M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch -M5 started Jan 31 2011 16:34:46 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:13 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 6441cfabc..05b37528b 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136188 # Simulator instruction rate (inst/s) -host_mem_usage 231788 # Number of bytes of host memory used -host_seconds 11906.26 # Real time elapsed on the host -host_tick_rate 64872637 # Simulator tick rate (ticks/s) +host_inst_rate 168346 # Simulator instruction rate (inst/s) +host_mem_usage 232444 # Number of bytes of host memory used +host_seconds 9631.89 # Real time elapsed on the host +host_tick_rate 80190939 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated sim_seconds 0.772390 # Number of seconds simulated @@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed +system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.COM:function_calls 0 # Number of function calls committed. +system.cpu.commit.COM:int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.COM:loads 419042125 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed @@ -150,6 +153,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 2 # number of floating regfile reads system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency @@ -249,6 +253,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 22026294 # system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads +system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued @@ -340,6 +346,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ @@ -420,7 +434,10 @@ system.cpu.memDep0.conflictingLoads 289036318 # Nu system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads system.cpu.numCycles 1544781000 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full @@ -434,10 +451,14 @@ system.cpu.rename.RENAME:RunCycles 968560202 # Nu system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3357159543 # The number of ROB reads +system.cpu.rob.rob_writes 3732197477 # The number of ROB writes system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini index 5a8f812f4..6c9d60230 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=AtomicSimpleCPU @@ -54,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 2cf82dff0..1dd3bb0d2 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:38:48 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index c7162281a..ce8635d17 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1409865 # Simulator instruction rate (inst/s) -host_mem_usage 219780 # Number of bytes of host memory used -host_seconds 1150.11 # Real time elapsed on the host -host_tick_rate 838177430 # Simulator tick rate (ticks/s) +host_inst_rate 1066510 # Simulator instruction rate (inst/s) +host_mem_usage 223440 # Number of bytes of host memory used +host_seconds 1520.37 # Real time elapsed on the host +host_tick_rate 634049597 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -11,8 +11,24 @@ sim_ticks 963992704000 # Nu system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1927985409 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 1927985409 # Number of busy cycles +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_refs 607228182 # Number of memory references +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 56899b979..967d3d328 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -10,6 +10,13 @@ type=System children=cpu membus physmem mem_mode=atomic physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -154,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index c71548d66..889c6868b 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 31 2011 14:03:49 -M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip -M5 started Jan 31 2011 14:03:51 +M5 compiled Feb 7 2011 02:32:07 +M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip +M5 started Feb 7 2011 02:32:35 M5 executing on burrito -command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 8adfcec1a..46400c920 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1099985 # Simulator instruction rate (inst/s) -host_mem_usage 227480 # Number of bytes of host memory used -host_seconds 1474.11 # Real time elapsed on the host -host_tick_rate 1223290364 # Simulator tick rate (ticks/s) +host_inst_rate 685934 # Simulator instruction rate (inst/s) +host_mem_usage 231240 # Number of bytes of host memory used +host_seconds 2363.92 # Real time elapsed on the host +host_tick_rate 762824620 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -200,8 +200,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 3606517174 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 3606517174 # Number of busy cycles +system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 1621493983 # Number of instructions executed -system.cpu.num_refs 607228182 # Number of memory references +system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses +system.cpu.num_int_insts 1621354493 # number of integer instructions +system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written +system.cpu.num_load_insts 419042125 # Number of load instructions +system.cpu.num_mem_refs 607228182 # number of memory refs +system.cpu.num_store_insts 188186057 # Number of store instructions system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- |