diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests/long/00.gzip | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests/long/00.gzip')
16 files changed, 1737 insertions, 1741 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 23a53cd4f..b6c1d1a1d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index 52e5d9fa3..9da502021 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:12:22 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 279017416500 because target called exit() +Exiting @ tick 274500333500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index a0423dfde..ec1428295 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279017 # Number of seconds simulated -sim_ticks 279017416500 # Number of ticks simulated +sim_seconds 0.274500 # Number of seconds simulated +sim_ticks 274500333500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128000 # Simulator instruction rate (inst/s) -host_tick_rate 59339940 # Simulator tick rate (ticks/s) -host_mem_usage 192984 # Number of bytes of host memory used -host_seconds 4702.02 # Real time elapsed on the host +host_inst_rate 56944 # Simulator instruction rate (inst/s) +host_tick_rate 25971361 # Simulator tick rate (ticks/s) +host_mem_usage 245756 # Number of bytes of host memory used +host_seconds 10569.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517555 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520186 # DTB read accesses -system.cpu.dtb.write_hits 39666604 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39666597 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668906 # DTB write accesses -system.cpu.dtb.data_hits 154184159 # DTB hits +system.cpu.dtb.write_accesses 39668899 # DTB write accesses +system.cpu.dtb.data_hits 154184165 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189092 # DTB accesses -system.cpu.itb.fetch_hits 29078095 # ITB hits +system.cpu.dtb.data_accesses 154189098 # DTB accesses +system.cpu.itb.fetch_hits 27986226 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 29078117 # ITB accesses +system.cpu.itb.fetch_accesses 27986248 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 558034834 # number of cpu cycles simulated +system.cpu.numCycles 549000668 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 547808694 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412073 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61249901 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 496784933 # Number of cycles cpu stages are processed. -system.cpu.activity 89.024000 # Percentage of cycles cpu is active +system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. +system.cpu.activity 89.164571 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 24 # Nu system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.927188 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.927188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.078529 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads +system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.078529 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 90037625 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 84897563 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 39773148 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 49497029 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 39091844 # Number of BTB hits +system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.978163 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 41686827 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48350798 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541420411 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005275257 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 257533113 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154627572 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 38276366 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1491795 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 39768161 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 22779717 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 63.580352 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411890550 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154582342 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 210144173 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 347890661 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.342105 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 246346046 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 311688788 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 55.854719 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 214904658 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 343130176 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 61.489025 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 446207500 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111827334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.039490 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 210384695 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347650139 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 62.299003 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 726.393228 # Cycle average of tags in use -system.cpu.icache.total_refs 29077078 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 852 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 34128.025822 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use +system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 726.393228 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.354684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 29077078 # number of ReadReq hits -system.cpu.icache.demand_hits 29077078 # number of demand (read+write) hits -system.cpu.icache.overall_hits 29077078 # number of overall hits -system.cpu.icache.ReadReq_misses 1015 # number of ReadReq misses -system.cpu.icache.demand_misses 1015 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1015 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 56421500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 56421500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 56421500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 29078093 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 29078093 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 29078093 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55587.684729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55587.684729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55587.684729 # average overall miss latency +system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits +system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits +system.cpu.icache.overall_hits 27985205 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,159 +143,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets 21750 system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 163 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 163 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 163 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 852 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 852 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 852 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45615500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45615500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45615500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.156589 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394384 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.642199 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267634000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.156589 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999550 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114120508 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38273876 # number of WriteReq hits -system.cpu.dcache.demand_hits 152394384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 152394384 # number of overall hits -system.cpu.dcache.ReadReq_misses 393534 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1177445 # number of WriteReq misses -system.cpu.dcache.demand_misses 1570979 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1570979 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8150455500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25241828500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 33392284000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 33392284000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits +system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 152394244 # number of overall hits +system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses +system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1571119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029846 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20710.930949 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 21437.798369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 21255.716340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 21255.716340 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12054000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3423892000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2783 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216217 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4331.297161 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15835.443097 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408187 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 192302 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 923282 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1115584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1115584 # number of overall MSHR hits +system.cpu.dcache.writebacks 408188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3562178000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5466807000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9028985000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9028985000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.846625 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21509.059147 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73794 # number of replacements -system.cpu.l2cache.tagsinuse 17696.077368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445682 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89681 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.969637 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73797 # number of replacements +system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1642.043968 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16054.033399 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.050111 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.489930 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170050 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408187 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364155 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364155 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32017 # number of ReadReq misses +system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 364156 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92092 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92092 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1674832000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3134450000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4809282000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4809282000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202067 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408187 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92094 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456247 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456247 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158447 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201847 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201847 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52310.709935 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.613816 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52222.581766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52222.581766 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1314000 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10346.456693 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59344 # number of writebacks +system.cpu.l2cache.writebacks 59345 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32017 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92092 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92092 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1280946000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406895000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3687841000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3687841000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201847 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201847 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.308086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.835622 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2c97093b4..55c96d241 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 8c9b1bbab..ac32dbe3f 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:20:02 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 162342217500 because target called exit() +Exiting @ tick 145300717500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 9bb344c89..339674edd 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.162342 # Number of seconds simulated -sim_ticks 162342217500 # Number of ticks simulated +sim_seconds 0.145301 # Number of seconds simulated +sim_ticks 145300717500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248957 # Simulator instruction rate (inst/s) -host_tick_rate 71463217 # Simulator tick rate (ticks/s) -host_mem_usage 193608 # Number of bytes of host memory used -host_seconds 2271.69 # Real time elapsed on the host +host_inst_rate 109615 # Simulator instruction rate (inst/s) +host_tick_rate 28162171 # Simulator tick rate (ticks/s) +host_mem_usage 246532 # Number of bytes of host memory used +host_seconds 5159.43 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122220880 # DTB read hits -system.cpu.dtb.read_misses 24742 # DTB read misses +system.cpu.dtb.read_hits 125840781 # DTB read hits +system.cpu.dtb.read_misses 26740 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122245622 # DTB read accesses -system.cpu.dtb.write_hits 40876425 # DTB write hits -system.cpu.dtb.write_misses 28211 # DTB write misses +system.cpu.dtb.read_accesses 125867521 # DTB read accesses +system.cpu.dtb.write_hits 41455603 # DTB write hits +system.cpu.dtb.write_misses 32148 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40904636 # DTB write accesses -system.cpu.dtb.data_hits 163097305 # DTB hits -system.cpu.dtb.data_misses 52953 # DTB misses +system.cpu.dtb.write_accesses 41487751 # DTB write accesses +system.cpu.dtb.data_hits 167296384 # DTB hits +system.cpu.dtb.data_misses 58888 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163150258 # DTB accesses -system.cpu.itb.fetch_hits 65447834 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.dtb.data_accesses 167355272 # DTB accesses +system.cpu.itb.fetch_hits 71694847 # ITB hits +system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65447871 # ITB accesses +system.cpu.itb.fetch_accesses 71694887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 324684436 # number of cpu cycles simulated +system.cpu.numCycles 290601436 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits +system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed +system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194873658 60.03% 60.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10240367 3.15% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15840170 4.88% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13915379 4.29% 72.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11968140 3.69% 76.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13832570 4.26% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5877215 1.81% 82.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3421155 1.05% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54648682 16.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451150539 72.57% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7830 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 128375845 20.65% 93.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42115665 6.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued -system.cpu.iq.rate 1.865224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 621649928 # Type of FU issued +system.cpu.iq.rate 2.139184 # Inst issue rate +system.cpu.iq.fu_busy_cnt 5190490 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008350 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1539391263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 723910400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 609602063 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3418 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1948 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 626838696 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11620337 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17312357 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 134964 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 365628 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4436658 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5886 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50751 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13016656 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1515186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 690779591 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2446688 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 131826399 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43887979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41001 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 365628 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4028203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 602481 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4630684 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613929253 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125867602 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7720675 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43212719 # number of nop insts executed -system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed -system.cpu.iew.exec_branches 67449018 # Number of branches executed -system.cpu.iew.exec_stores 40932468 # Number of stores executed -system.cpu.iew.exec_rate 1.845435 # Inst execution rate -system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395837342 # num instructions producing a value -system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value +system.cpu.iew.exec_nop 45600120 # number of nop insts executed +system.cpu.iew.exec_refs 167374804 # number of memory reference insts executed +system.cpu.iew.exec_branches 68499674 # Number of branches executed +system.cpu.iew.exec_stores 41507202 # Number of stores executed +system.cpu.iew.exec_rate 2.112616 # Inst execution rate +system.cpu.iew.wb_sent 611080780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 609603660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419952220 # num instructions producing a value +system.cpu.iew.wb_consumers 531843575 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back +system.cpu.iew.wb_rate 2.097731 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 88769206 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4122409 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 277515436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.168733 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.607930 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91720629 33.05% 33.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75337959 27.15% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31629889 11.40% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9762168 3.52% 75.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10089201 3.64% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21364718 7.70% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5897222 2.13% 88.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2300204 0.83% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29413446 10.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 277515436 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29413446 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 956313792 # The number of ROB reads -system.cpu.rob.rob_writes 1333072216 # The number of ROB writes -system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 938663770 # The number of ROB reads +system.cpu.rob.rob_writes 1394275800 # The number of ROB writes +system.cpu.timesIdled 2250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads -system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844972523 # number of integer regfile reads -system.cpu.int_regfile_writes 489243634 # number of integer regfile writes -system.cpu.fp_regfile_reads 253 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cpi 0.513836 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.513836 # CPI: Total CPI of All Threads +system.cpu.ipc 1.946145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.946145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 864545189 # number of integer regfile reads +system.cpu.int_regfile_writes 501712619 # number of integer regfile writes +system.cpu.fp_regfile_reads 277 # number of floating regfile reads +system.cpu.fp_regfile_writes 57 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 32 # number of replacements -system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use -system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 798.939045 # Cycle average of tags in use +system.cpu.icache.total_refs 71693570 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 940 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 76269.755319 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits -system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits -system.cpu.icache.overall_hits 65446683 # number of overall hits -system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses -system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 798.939045 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.390107 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 71693570 # number of ReadReq hits +system.cpu.icache.demand_hits 71693570 # number of demand (read+write) hits +system.cpu.icache.overall_hits 71693570 # number of overall hits +system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses +system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1277 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46025000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46025000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46025000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 71694847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 71694847 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 71694847 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36041.503524 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36041.503524 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36041.503524 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 940 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 940 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 940 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33513000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33513000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33513000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660 # 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Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits +system.cpu.dcache.replacements 470805 # number of replacements +system.cpu.dcache.tagsinuse 4093.951768 # Cycle average of tags in use +system.cpu.dcache.total_refs 151630549 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474901 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 319.288755 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126064000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4093.951768 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 113482808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147738 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 149582203 # number of overall hits -system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses -system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2073649 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 151630546 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151630546 # number of overall hits +system.cpu.dcache.ReadReq_misses 730789 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303583 # number of WriteReq misses +system.cpu.dcache.demand_misses 2034372 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2034372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11799719000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19632109224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31431828224 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31431828224 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 114213597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 153664918 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153664918 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033043 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013239 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15450.383816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15450.383816 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 917496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 119 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7710.050420 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423176 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses +system.cpu.dcache.writebacks 423137 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 511918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047553 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1559471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1559471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218871 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474901 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474901 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3027783994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4668295494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4668295494 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7495.335152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74455 # number of replacements -system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use -system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74456 # number of replacements +system.cpu.l2cache.tagsinuse 17669.602101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478138 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.291713 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383286 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92757 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1747.606056 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15921.996045 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053333 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485901 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186860 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423137 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196226 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 383086 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 383086 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32951 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92755 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92755 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133426500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2066052500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3199479000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3199479000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423137 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475841 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475841 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.149906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233582 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194929 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194929 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34493.870950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34493.870950 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 468000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 80 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5850 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59322 # number of writebacks +system.cpu.l2cache.writebacks 59325 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32951 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92755 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022116000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877697000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2899813000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2899813000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 07f2d92be..485873d05 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 7084f92e2..f34e7fb17 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 16:32:58 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 00:29:29 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 189745250000 because target called exit() +Exiting @ tick 182546630500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 1e34e6b02..79eb9dffa 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.189745 # Number of seconds simulated -sim_ticks 189745250000 # Number of ticks simulated +sim_seconds 0.182547 # Number of seconds simulated +sim_ticks 182546630500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57706 # Simulator instruction rate (inst/s) -host_tick_rate 18177630 # Simulator tick rate (ticks/s) -host_mem_usage 255472 # Number of bytes of host memory used -host_seconds 10438.39 # Real time elapsed on the host -sim_insts 602359840 # Number of instructions simulated +host_inst_rate 66837 # Simulator instruction rate (inst/s) +host_tick_rate 20255145 # Simulator tick rate (ticks/s) +host_mem_usage 257744 # Number of bytes of host memory used +host_seconds 9012.36 # Real time elapsed on the host +sim_insts 602359825 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 379490501 # number of cpu cycles simulated +system.cpu.numCycles 365093262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86928352 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80528545 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3884028 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 80092626 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 74490175 # Number of BTB hits +system.cpu.BPredUnit.lookups 94055134 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86414920 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3979081 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 88956702 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 82512166 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1400314 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1695 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 70199329 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 678993278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86928352 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 75890489 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 151223447 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473449 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 70199329 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 924096 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 378585601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.910199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.920341 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1838122 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1832 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 80667890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 724099412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94055134 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84350288 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163986224 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21484785 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102787887 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 614 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 78002853 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1602878 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 364227401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.127111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.977166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 227362317 60.06% 60.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25157685 6.65% 66.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17486331 4.62% 71.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 21712752 5.74% 77.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11244311 2.97% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11955687 3.16% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4446495 1.17% 84.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7289466 1.93% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 51930557 13.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 200241339 54.98% 54.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25976483 7.13% 62.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20067114 5.51% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25160816 6.91% 74.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12370660 3.40% 77.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13978922 3.84% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4846811 1.33% 83.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7981089 2.19% 85.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53604167 14.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 378585601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.229066 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.789223 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 160153181 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 58093543 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 140600980 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8092430 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11645467 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 5860940 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1284 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 711110342 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4730 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11645467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 169808793 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7731895 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 102804 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 138994558 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50302084 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 699378515 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 44454073 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4930432 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723286205 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3254558347 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3254558219 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 364227401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257619 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.983327 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 103328819 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 82990379 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 141956916 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19169051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16782236 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6955768 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2559 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 762233872 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7095 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 16782236 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 116716310 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10162193 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109463 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 147645122 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72812077 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 747464015 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 176 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 58909213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10051058 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 590 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 771173910 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3477020106 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3477019978 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 95868750 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6063 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6060 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 83251971 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172882787 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80813690 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15992884 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23084405 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 678074240 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7046 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 648954836 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 321485 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 74818706 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 185294154 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 741 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 378585601 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.714156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.635088 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417426 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 143756479 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6432 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6428 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 129949589 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 185066010 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85818254 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 23013256 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30486769 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 718960040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 670280843 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 854799 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 116155760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 288576013 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 364227401 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.840281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.715695 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99002495 26.15% 26.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 107489876 28.39% 54.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 72418873 19.13% 73.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 48797355 12.89% 86.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22456398 5.93% 92.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 17049752 4.50% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6015477 1.59% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3775065 1.00% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1580310 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 91766913 25.19% 25.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93871528 25.77% 50.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74118513 20.35% 71.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 44924126 12.33% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26194132 7.19% 90.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19078510 5.24% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7890026 2.17% 98.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5178547 1.42% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1205106 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 378585601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 364227401 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164864 5.19% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2380738 74.98% 80.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 629773 19.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 168001 4.86% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2622016 75.82% 80.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 668303 19.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 405017368 62.41% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6545 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 167786137 25.85% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76144783 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 415768758 62.03% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 175425484 26.17% 88.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79080039 11.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 648954836 # Type of FU issued -system.cpu.iq.rate 1.710069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3175375 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004893 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1679992097 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 753424475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 636613588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 670280843 # Type of FU issued +system.cpu.iq.rate 1.835917 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3458320 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005160 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1709102170 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 835787693 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 655814402 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 652130191 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 673739143 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 25625639 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28975081 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23930184 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271058 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 524844 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10592669 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36113410 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 665732 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 15597236 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15888 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16028 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12631 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11645467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 694588 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 678142321 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3267373 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172882787 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80813690 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5710 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7359 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3854 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 524844 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3752039 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 638545 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4390584 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642328929 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 165615332 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6625907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16782236 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 788804 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 51690 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 719036936 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2011497 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 185066010 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85818254 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13145 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5072 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 665732 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4120759 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 486329 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4607088 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 662401467 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171983852 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7879376 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 61035 # number of nop insts executed -system.cpu.iew.exec_refs 240294143 # number of memory reference insts executed -system.cpu.iew.exec_branches 74636278 # Number of branches executed -system.cpu.iew.exec_stores 74678811 # Number of stores executed -system.cpu.iew.exec_rate 1.692609 # Inst execution rate -system.cpu.iew.wb_sent 637663585 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 636613604 # cumulative count of insts written-back -system.cpu.iew.wb_producers 410591202 # num instructions producing a value -system.cpu.iew.wb_consumers 620919251 # num instructions consuming a value +system.cpu.iew.exec_nop 69492 # number of nop insts executed +system.cpu.iew.exec_refs 249361026 # number of memory reference insts executed +system.cpu.iew.exec_branches 77022435 # Number of branches executed +system.cpu.iew.exec_stores 77377174 # Number of stores executed +system.cpu.iew.exec_rate 1.814335 # Inst execution rate +system.cpu.iew.wb_sent 657949131 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 655814418 # cumulative count of insts written-back +system.cpu.iew.wb_producers 425644511 # num instructions producing a value +system.cpu.iew.wb_consumers 661906658 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.677548 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661263 # average fanout of values written-back +system.cpu.iew.wb_rate 1.796293 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643058 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359891 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 75781554 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6305 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3943142 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366940135 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.641575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.021399 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359876 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 116686609 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4038424 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 347445166 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.733683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.123903 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118738354 32.36% 32.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 123466865 33.65% 66.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52180899 14.22% 80.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12560554 3.42% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20975428 5.72% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13806386 3.76% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7633759 2.08% 95.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2509750 0.68% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15068140 4.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113764130 32.74% 32.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 109130175 31.41% 64.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49680788 14.30% 78.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10344875 2.98% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23361064 6.72% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14153772 4.07% 92.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8154815 2.35% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1152882 0.33% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17702665 5.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366940135 # Number of insts commited each cycle -system.cpu.commit.count 602359891 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 347445166 # Number of insts commited each cycle +system.cpu.commit.count 602359876 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173623 # Number of memory references committed -system.cpu.commit.loads 148952602 # Number of loads committed +system.cpu.commit.refs 219173617 # Number of memory references committed +system.cpu.commit.loads 148952599 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828609 # Number of branches committed +system.cpu.commit.branches 70828606 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522671 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522659 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15068140 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 17702665 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1030012828 # The number of ROB reads -system.cpu.rob.rob_writes 1367937117 # The number of ROB writes -system.cpu.timesIdled 36799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 904900 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359840 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359840 # Number of Instructions Simulated -system.cpu.cpi 0.630006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.587286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.587286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3206207435 # number of integer regfile reads -system.cpu.int_regfile_writes 661050575 # number of integer regfile writes +system.cpu.rob.rob_reads 1048788374 # The number of ROB reads +system.cpu.rob.rob_writes 1454922610 # The number of ROB writes +system.cpu.timesIdled 36904 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 865861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359825 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359825 # Number of Instructions Simulated +system.cpu.cpi 0.606105 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.606105 # CPI: Total CPI of All Threads +system.cpu.ipc 1.649879 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.649879 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3307885763 # number of integer regfile reads +system.cpu.int_regfile_writes 680907350 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 912573919 # number of misc regfile reads -system.cpu.misc_regfile_writes 2672 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 627.011637 # Cycle average of tags in use -system.cpu.icache.total_refs 70198409 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 96294.113855 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 966917605 # number of misc regfile reads +system.cpu.misc_regfile_writes 2666 # number of misc regfile writes +system.cpu.icache.replacements 48 # number of replacements +system.cpu.icache.tagsinuse 654.116997 # Cycle average of tags in use +system.cpu.icache.total_refs 78001834 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 767 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 101697.306389 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 627.011637 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.306158 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 70198409 # number of ReadReq hits -system.cpu.icache.demand_hits 70198409 # number of demand (read+write) hits -system.cpu.icache.overall_hits 70198409 # number of overall hits -system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses -system.cpu.icache.demand_misses 920 # number of demand (read+write) misses -system.cpu.icache.overall_misses 920 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32585000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32585000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32585000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 70199329 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 70199329 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 70199329 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 654.116997 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.319393 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 78001834 # number of ReadReq hits +system.cpu.icache.demand_hits 78001834 # number of demand (read+write) hits +system.cpu.icache.overall_hits 78001834 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35576500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35576500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35576500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 78002853 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 78002853 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 78002853 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35418.478261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35418.478261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35418.478261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34913.150147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34913.150147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34913.150147 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,143 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 731 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 252 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 252 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 252 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 767 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 767 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 767 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25045500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25045500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25045500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26271000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26271000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26271000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34261.969904 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34251.629726 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440236 # number of replacements -system.cpu.dcache.tagsinuse 4094.816019 # Cycle average of tags in use -system.cpu.dcache.total_refs 206409236 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444332 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 464.538309 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88952000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.816019 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 138485254 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67921309 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1329 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1335 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 206406563 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 206406563 # number of overall hits -system.cpu.dcache.ReadReq_misses 243961 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1496222 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1740183 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1740183 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3253587000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26715936018 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 29969523018 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 29969523018 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 138729215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 440983 # number of replacements +system.cpu.dcache.tagsinuse 4094.790768 # Cycle average of tags in use +system.cpu.dcache.total_refs 209375241 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445079 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 470.422646 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87857000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.790768 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 141476381 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67896188 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1340 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1332 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 209372569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 209372569 # number of overall hits +system.cpu.dcache.ReadReq_misses 248779 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1521343 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 10 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1770122 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1770122 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3280245000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26835404025 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 198500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30115649025 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30115649025 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 141725160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1335 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 208146746 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 208146746 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001759 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.021554 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.011161 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13336.504605 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17855.596307 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17222.052519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17222.052519 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 1350 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1332 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 211142691 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 211142691 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001755 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.021916 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.007407 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008384 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008384 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13185.377383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17639.285832 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 19850 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17013.318305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17013.318305 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 394716 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 46944 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1248905 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1295849 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1295849 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247317 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 444334 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 444334 # number of overall MSHR misses +system.cpu.dcache.writebacks 395060 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51069 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1273974 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 10 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1325043 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1325043 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197710 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445079 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445079 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1620169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2562065527 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4182234527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4182234527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1624301000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2561171527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4185472527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4185472527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001395 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8223.498480 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.439614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.002108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8215.573314 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.647898 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72895 # number of replacements -system.cpu.l2cache.tagsinuse 17837.050931 # Cycle average of tags in use -system.cpu.l2cache.total_refs 420745 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88410 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.759020 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72980 # number of replacements +system.cpu.l2cache.tagsinuse 17828.973663 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421802 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88512 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.765478 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1909.078024 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15927.972907 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486083 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165017 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 394716 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 188953 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 353970 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 353970 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32728 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91091 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91091 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1124545500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2003459500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3128005000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3128005000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 197745 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 394716 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247316 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165506 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235986 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204671 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34360.348937 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34327.561983 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34339.341977 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34339.341977 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1911.988295 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15916.985368 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058349 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485748 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165669 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395060 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 188996 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354665 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354665 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32802 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58379 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91181 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91181 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126009000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2004629500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130638500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130638500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247375 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445846 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445846 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235994 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204512 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204512 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.449546 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34338.195241 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34334.329520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34334.329520 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -496,32 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58107 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32722 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91085 # number of overall MSHR misses +system.cpu.l2cache.writebacks 58140 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32793 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58379 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91172 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91172 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1018131500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823239000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2841370500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2841370500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1019413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823005500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2842419000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2842419000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.586517 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31239.638127 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235994 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204492 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204492 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31086.314152 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31227.076517 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index d070843b4..d391b02a1 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index e45361957..589c8ec4c 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:18:15 -gem5 executing on zizzer +gem5 compiled Jul 8 2011 15:08:13 +gem5 started Jul 8 2011 18:26:23 +gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 573907140000 because target called exit() +Exiting @ tick 563588156500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 783dcd8cf..d52982e26 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,250 +1,252 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.573907 # Number of seconds simulated -sim_ticks 573907140000 # Number of ticks simulated +sim_seconds 0.563588 # Number of seconds simulated +sim_ticks 563588156500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108575 # Simulator instruction rate (inst/s) -host_tick_rate 44331146 # Simulator tick rate (ticks/s) -host_mem_usage 230156 # Number of bytes of host memory used -host_seconds 12945.91 # Real time elapsed on the host +host_inst_rate 64765 # Simulator instruction rate (inst/s) +host_tick_rate 25968064 # Simulator tick rate (ticks/s) +host_mem_usage 251156 # Number of bytes of host memory used +host_seconds 21703.13 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1147814281 # number of cpu cycles simulated +system.cpu.numCycles 1127176314 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103831607 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92935748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5327690 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 99212201 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 97835702 # Number of BTB hits +system.cpu.BPredUnit.lookups 108002078 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 96458356 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5419443 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 104845979 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 103526655 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1143 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 1233 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 171000623 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1733021012 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103831607 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 97836845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371038275 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5780781 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 171000623 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1213723 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1147443356 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.514308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.728632 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 182291160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1787208152 # Number of instructions fetch has processed +system.cpu.fetch.Branches 108002078 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103527888 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 384452467 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 39306331 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 526780202 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 13 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1622 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 177554256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1007248 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1126809005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.590132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.768689 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 776405081 67.66% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82050380 7.15% 74.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44983062 3.92% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23090909 2.01% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33504477 2.92% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 33278378 2.90% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14847881 1.29% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7468781 0.65% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 131814407 11.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 742356538 65.88% 65.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 85341479 7.57% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 46929286 4.16% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24554385 2.18% 79.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 34670829 3.08% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 34912206 3.10% 85.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 15372705 1.36% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7941055 0.70% 88.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 134730522 11.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1147443356 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090460 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.509844 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 395037433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 355619175 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 349843694 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18917144 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 28025910 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1728452454 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 28025910 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 431217240 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 109925159 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53352046 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 328971918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 195951083 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1711590764 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 114289761 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41137293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28197975 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1428307054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2890539960 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2856856842 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33683118 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1126809005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.095816 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.585562 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 243483307 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 469211226 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 329903735 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50927196 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 33283541 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1773785354 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 33283541 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 303199519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 121005551 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66378557 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 319425533 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 283516304 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1755376544 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 158155356 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 64460520 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 40367810 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1464774447 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2963679380 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2929648556 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34030824 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 183536602 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3097987 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3097933 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 355739263 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 461589654 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 187242454 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 391441071 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 159185807 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1587145158 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3113475 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1482560203 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270761 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 184202886 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 243216207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 869804 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1147443356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.292055 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.157896 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 220003995 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3335169 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3335909 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 507197291 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 473956598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 190918944 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 402921595 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 162419763 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1626020867 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3211854 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1494042135 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 206172 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 223169277 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 302404283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 968183 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1126809005 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.325905 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.154571 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 300845237 26.22% 26.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 453630203 39.53% 65.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 228516175 19.92% 85.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 106998909 9.32% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 42740064 3.72% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8913516 0.78% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5375020 0.47% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 270889 0.02% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 153343 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 292007700 25.91% 25.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 411780858 36.54% 62.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 263168713 23.36% 85.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 101528512 9.01% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43990451 3.90% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 11374555 1.01% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2356617 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 448758 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152841 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1147443356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1126809005 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 201164 6.38% 6.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 172993 5.49% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2493416 79.12% 90.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 283893 9.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 276548 8.36% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 151088 4.56% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2447279 73.94% 86.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 434986 13.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 884414368 59.65% 59.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2630713 0.18% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 423843345 28.59% 88.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171671777 11.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 893364457 59.80% 59.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2623126 0.18% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 426278234 28.53% 88.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171776318 11.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1482560203 # Type of FU issued -system.cpu.iq.rate 1.291638 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3151466 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002126 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4098230852 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1765766096 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1465086286 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17755137 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9173728 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8521133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1476573323 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9138346 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 135220708 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1494042135 # Type of FU issued +system.cpu.iq.rate 1.325473 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3309901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002215 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4100596899 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1843738328 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1474876541 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17812449 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9274219 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8514769 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1488163197 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9188839 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 140932048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 59076810 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33855 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 480180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20394312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 71443754 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20242 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 695476 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24070802 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 40283 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 267 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39866 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 28025910 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2504854 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 128582 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1690773630 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4528845 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 461589654 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 187242454 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3013900 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66564 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8476 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 480180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5013682 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 651351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5665033 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1476197681 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 421021999 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6362522 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 33283541 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2642816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 166342 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1732819113 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4184603 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 473956598 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 190918944 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3110022 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 73740 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9229 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 695476 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5255230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 461002 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5716232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1486789752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 422968775 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7252383 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 100514997 # number of nop insts executed -system.cpu.iew.exec_refs 591171698 # number of memory reference insts executed -system.cpu.iew.exec_branches 89599986 # Number of branches executed -system.cpu.iew.exec_stores 170149699 # Number of stores executed -system.cpu.iew.exec_rate 1.286095 # Inst execution rate -system.cpu.iew.wb_sent 1474639839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1473607419 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1163432060 # num instructions producing a value -system.cpu.iew.wb_consumers 1211671971 # num instructions consuming a value +system.cpu.iew.exec_nop 103586392 # number of nop insts executed +system.cpu.iew.exec_refs 593427321 # number of memory reference insts executed +system.cpu.iew.exec_branches 90250072 # Number of branches executed +system.cpu.iew.exec_stores 170458546 # Number of stores executed +system.cpu.iew.exec_rate 1.319039 # Inst execution rate +system.cpu.iew.wb_sent 1484841678 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1483391310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1170940676 # num instructions producing a value +system.cpu.iew.wb_consumers 1222219030 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.283838 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.960187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.316024 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.958045 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 201157053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 243200723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5327690 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1119418057 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.330623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.777335 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5419443 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1093526075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.362129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.820328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 396150099 35.39% 35.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 467476114 41.76% 77.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 53942653 4.82% 81.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96590276 8.63% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 32582647 2.91% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8533715 0.76% 94.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 26013211 2.32% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9722118 0.87% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 28407224 2.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 386645364 35.36% 35.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 450467032 41.19% 76.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52266567 4.78% 81.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 95504499 8.73% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 32424023 2.97% 93.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8856558 0.81% 93.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 27482733 2.51% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9900040 0.91% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29979259 2.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1119418057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1093526075 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -254,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 28407224 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29979259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2781626311 # The number of ROB reads -system.cpu.rob.rob_writes 3409421269 # The number of ROB writes -system.cpu.timesIdled 11496 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 370925 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2796205964 # The number of ROB reads +system.cpu.rob.rob_writes 3498772696 # The number of ROB writes +system.cpu.timesIdled 11331 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 367309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.816599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.816599 # CPI: Total CPI of All Threads -system.cpu.ipc 1.224592 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.224592 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1997677714 # number of integer regfile reads -system.cpu.int_regfile_writes 1296953173 # number of integer regfile writes -system.cpu.fp_regfile_reads 16960308 # number of floating regfile reads -system.cpu.fp_regfile_writes 10460736 # number of floating regfile writes -system.cpu.misc_regfile_reads 596972028 # number of misc regfile reads +system.cpu.cpi 0.801916 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801916 # CPI: Total CPI of All Threads +system.cpu.ipc 1.247014 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.247014 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2006108330 # number of integer regfile reads +system.cpu.int_regfile_writes 1306606440 # number of integer regfile writes +system.cpu.fp_regfile_reads 16974388 # number of floating regfile reads +system.cpu.fp_regfile_writes 10441040 # number of floating regfile writes +system.cpu.misc_regfile_reads 599300610 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.icache.replacements 152 # number of replacements -system.cpu.icache.tagsinuse 1026.516875 # Cycle average of tags in use -system.cpu.icache.total_refs 170998889 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1268 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 134857.167981 # Average number of references to valid blocks. +system.cpu.icache.replacements 162 # number of replacements +system.cpu.icache.tagsinuse 1043.489653 # Cycle average of tags in use +system.cpu.icache.total_refs 177552476 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 136894.738628 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1026.516875 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.501229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 170998889 # number of ReadReq hits -system.cpu.icache.demand_hits 170998889 # number of demand (read+write) hits -system.cpu.icache.overall_hits 170998889 # number of overall hits -system.cpu.icache.ReadReq_misses 1734 # number of ReadReq misses -system.cpu.icache.demand_misses 1734 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1734 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 61087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 61087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 61087500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 171000623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 171000623 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 171000623 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1043.489653 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.509516 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 177552476 # number of ReadReq hits +system.cpu.icache.demand_hits 177552476 # number of demand (read+write) hits +system.cpu.icache.overall_hits 177552476 # number of overall hits +system.cpu.icache.ReadReq_misses 1780 # number of ReadReq misses +system.cpu.icache.demand_misses 1780 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62084000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62084000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62084000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 177554256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 177554256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 177554256 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35229.238754 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35229.238754 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35229.238754 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34878.651685 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34878.651685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34878.651685 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 465 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1269 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1269 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1269 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 482 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 482 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 44480000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 44480000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 44480000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45208500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45208500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45208500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35051.221434 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35051.221434 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35051.221434 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34829.352851 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 477525 # number of replacements -system.cpu.dcache.tagsinuse 4095.396718 # Cycle average of tags in use -system.cpu.dcache.total_refs 449986913 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 481621 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 934.317467 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 132284000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.396718 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999853 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 284949611 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 165035983 # number of WriteReq hits +system.cpu.dcache.replacements 475456 # number of replacements +system.cpu.dcache.tagsinuse 4095.394464 # Cycle average of tags in use +system.cpu.dcache.total_refs 446158150 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479552 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 930.364486 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131008000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.394464 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999852 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 281189388 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 164967443 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 449985594 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 449985594 # number of overall hits -system.cpu.dcache.ReadReq_misses 816129 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1810833 # number of WriteReq misses +system.cpu.dcache.demand_hits 446156831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 446156831 # number of overall hits +system.cpu.dcache.ReadReq_misses 816269 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1879373 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2626962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2626962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11967941500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27822628145 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2695642 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2695642 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11972698500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28858348258 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 39790569645 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39790569645 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 285765740 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 40831046758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 40831046758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 282005657 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 452612556 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 452612556 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002856 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010853 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 448852473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 448852473 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002895 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011264 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.005804 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005804 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14664.276726 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15364.546673 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.006006 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.006006 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14667.589361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15355.306402 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15146.990952 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15146.990952 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 15147.058385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15147.058385 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 428389 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 602603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1542745 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2145348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2145348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213526 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 268088 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426829 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 604140 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1611957 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2216097 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2216097 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212129 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267416 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 481614 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 481614 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479545 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479545 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1594631500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3466876734 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1590330500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3553768773 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5061508234 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5061508234 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5144099273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5144099273 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000747 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000752 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001603 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001064 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001064 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7468.090537 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12931.860934 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001068 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001068 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.997110 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13289.289994 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10509.470726 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10509.470726 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75907 # number of replacements -system.cpu.l2cache.tagsinuse 17672.498181 # Cycle average of tags in use -system.cpu.l2cache.total_refs 467533 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91416 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.114345 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75860 # number of replacements +system.cpu.l2cache.tagsinuse 17695.918496 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464712 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91372 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.085934 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1962.738670 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15709.759511 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.059898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.479424 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181118 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 428389 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 207636 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 388754 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 388754 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33668 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94136 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94136 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1145944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2080516000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3226460000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3226460000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 428389 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 268104 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 482890 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 482890 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.156751 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.225539 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194943 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194943 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.592610 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34406.892902 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34274.453981 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34274.453981 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1941.337449 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15754.581047 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.059245 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480792 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179775 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426829 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 206986 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386761 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386761 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33652 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60437 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94089 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94089 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1145407000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2080656500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3226063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3226063500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213427 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426829 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480850 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480850 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157675 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.225998 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195672 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195672 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.818020 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34426.865993 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34287.360903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34287.360903 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59288 # number of writebacks +system.cpu.l2cache.writebacks 59276 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33668 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60468 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94136 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94136 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33652 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60437 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94089 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94089 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043871500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893875000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2937746500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2937746500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1043368500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893759500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2937128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2937128000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156751 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225539 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194943 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194943 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.856243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.285109 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.471106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.471106 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225998 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195672 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195672 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.650541 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31334.439168 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 21fe896ca..29b391479 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f693063ef..621f09656 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 19:12:13 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1062,4 +1062,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 750278436000 because target called exit() +Exiting @ tick 746999805000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 8f8873cca..b33faa135 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.750278 # Number of seconds simulated -sim_ticks 750278436000 # Number of ticks simulated +sim_seconds 0.747000 # Number of seconds simulated +sim_ticks 746999805000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214715 # Simulator instruction rate (inst/s) -host_tick_rate 99350353 # Simulator tick rate (ticks/s) -host_mem_usage 230596 # Number of bytes of host memory used -host_seconds 7551.84 # Real time elapsed on the host +host_inst_rate 52755 # Simulator instruction rate (inst/s) +host_tick_rate 24303440 # Simulator tick rate (ticks/s) +host_mem_usage 253604 # Number of bytes of host memory used +host_seconds 30736.38 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1500556873 # number of cpu cycles simulated +system.cpu.numCycles 1493999611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 179206646 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 179206646 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 8463551 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 169776881 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 168588435 # Number of BTB hits +system.cpu.BPredUnit.lookups 183981284 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 183981284 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7273832 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 175979129 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 174823422 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 168643185 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1398775423 # Number of instructions fetch has processed -system.cpu.fetch.Branches 179206646 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 168588435 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 401459368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14868125 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 168643185 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 821564 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1500265844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.692515 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.050179 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 199101325 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1418187336 # Number of instructions fetch has processed +system.cpu.fetch.Branches 183981284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174823422 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 411931747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 120581871 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 775842898 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 439 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 187933146 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1412014 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1493732032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.070436 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1101846908 73.44% 73.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25629201 1.71% 75.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17503252 1.17% 76.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17259352 1.15% 77.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 30203070 2.01% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16882652 1.13% 80.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34105222 2.27% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37737433 2.52% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 219098754 14.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1084944891 72.63% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27695152 1.85% 74.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18612240 1.25% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16931022 1.13% 76.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30747713 2.06% 78.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 17254642 1.16% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38005540 2.54% 82.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38774045 2.60% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220766787 14.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1500265844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119427 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 426619882 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 588582259 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 331774062 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 54890410 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 98399231 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2463603655 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 98399231 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 490140995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 167797271 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 309381141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 434544169 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2390094348 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 298397694 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 109374277 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2388910462 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5790943512 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5790943448 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1493732032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123147 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.949255 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 299784199 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 683008972 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 314849688 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 89233622 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 106855551 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2563435147 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 106855551 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 360599256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 188215169 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3353 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 328972953 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 509085750 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2506842740 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 353300714 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 135977984 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2507364398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6062894034 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6062889786 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4248 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 770915812 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 87 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 713558954 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 613723437 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250366407 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 539421468 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 206415389 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2337617045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1854722734 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196953 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 715983429 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1505792864 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1500265844 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.236263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.216770 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 889369748 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 162 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 860776772 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 644217579 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 260359160 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 564219162 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 219825369 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2437807916 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 95 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1879814445 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 473311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 816283522 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1731057121 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1493732032 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.258468 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.208875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 461494018 30.76% 30.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 582014055 38.79% 69.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 214930558 14.33% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153972669 10.26% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 64799231 4.32% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 17691341 1.18% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4397619 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 840611 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125742 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 432191127 28.93% 28.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 591005322 39.57% 68.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 246823296 16.52% 85.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 135579868 9.08% 94.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 59328852 3.97% 98.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 22913004 1.53% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4862881 0.33% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 856243 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 171439 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1500265844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1493732032 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 159647 3.75% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3486871 81.91% 85.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 610438 14.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 145103 3.04% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3853337 80.69% 83.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 777052 16.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 27575645 1.49% 1.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1184540758 63.87% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 450487645 24.29% 89.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192118686 10.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26397138 1.40% 1.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212079345 64.48% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 449002654 23.89% 89.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192335308 10.23% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1854722734 # Type of FU issued -system.cpu.iq.rate 1.236023 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4256956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002295 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5214165186 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3059990835 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1837811563 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1879814445 # Type of FU issued +system.cpu.iq.rate 1.258243 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4775492 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002540 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5258609690 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3260533161 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1853774167 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 1274 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1831404026 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1858192780 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 117971084 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 120571651 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 194681312 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6391116 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 62180350 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 225175454 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6448917 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 72173103 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30252 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 67 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30868 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 98399231 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1363305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 110880 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2337617123 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338195 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 613723437 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250366407 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56702 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6391116 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4450206 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4153743 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8603949 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1842187665 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 444314021 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12535069 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 106855551 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4276997 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 154006 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2437808011 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3809571 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 644217579 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 260359160 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 95 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 92996 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6448917 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4522013 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2931532 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7453545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1858657499 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 444749829 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21156946 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 636013673 # number of memory reference insts executed -system.cpu.iew.exec_branches 111427506 # Number of branches executed -system.cpu.iew.exec_stores 191699652 # Number of stores executed -system.cpu.iew.exec_rate 1.227669 # Inst execution rate -system.cpu.iew.wb_sent 1840965230 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1837811575 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1424401809 # num instructions producing a value -system.cpu.iew.wb_consumers 2083960582 # num instructions consuming a value +system.cpu.iew.exec_refs 636612361 # number of memory reference insts executed +system.cpu.iew.exec_branches 111987428 # Number of branches executed +system.cpu.iew.exec_stores 191862532 # Number of stores executed +system.cpu.iew.exec_rate 1.244082 # Inst execution rate +system.cpu.iew.wb_sent 1856615108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1853774179 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1441885120 # num instructions producing a value +system.cpu.iew.wb_consumers 2107634936 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.224753 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683507 # average fanout of values written-back +system.cpu.iew.wb_rate 1.240813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.684125 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 716132515 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 816323432 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8463578 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1401866613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.156668 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.378442 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7273892 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1386876481 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.169170 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.394530 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 520031376 37.10% 37.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 533018726 38.02% 75.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 125308330 8.94% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 139235246 9.93% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 43288203 3.09% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23453801 1.67% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4331063 0.31% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1854281 0.13% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11345587 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 510181205 36.79% 36.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 529583219 38.19% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122943422 8.86% 83.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 138376651 9.98% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 42654329 3.08% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24144434 1.74% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5177613 0.37% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2036062 0.15% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11779546 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1401866613 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1386876481 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -253,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11345587 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11779546 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3728147523 # The number of ROB reads -system.cpu.rob.rob_writes 4773653528 # The number of ROB writes -system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 291029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3812914349 # The number of ROB reads +system.cpu.rob.rob_writes 4982493999 # The number of ROB writes +system.cpu.timesIdled 44138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 267579 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.925416 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.925416 # CPI: Total CPI of All Threads -system.cpu.ipc 1.080595 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.080595 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3235784294 # number of integer regfile reads -system.cpu.int_regfile_writes 1830729236 # number of integer regfile writes +system.cpu.cpi 0.921372 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.921372 # CPI: Total CPI of All Threads +system.cpu.ipc 1.085338 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.085338 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3240601354 # number of integer regfile reads +system.cpu.int_regfile_writes 1846777221 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 930213220 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 793.330591 # Cycle average of tags in use -system.cpu.icache.total_refs 168641986 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 875 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 192733.698286 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 936479302 # number of misc regfile reads +system.cpu.icache.replacements 14 # number of replacements +system.cpu.icache.tagsinuse 820.004984 # Cycle average of tags in use +system.cpu.icache.total_refs 187931883 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 908 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 206973.439427 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 793.330591 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.387368 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 168641986 # number of ReadReq hits -system.cpu.icache.demand_hits 168641986 # number of demand (read+write) hits -system.cpu.icache.overall_hits 168641986 # number of overall hits -system.cpu.icache.ReadReq_misses 1199 # number of ReadReq misses -system.cpu.icache.demand_misses 1199 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1199 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 42201000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 42201000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 42201000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 168643185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 168643185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 168643185 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 820.004984 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.400393 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 187931883 # number of ReadReq hits +system.cpu.icache.demand_hits 187931883 # number of demand (read+write) hits +system.cpu.icache.overall_hits 187931883 # number of overall hits +system.cpu.icache.ReadReq_misses 1263 # number of ReadReq misses +system.cpu.icache.demand_misses 1263 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1263 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 44191500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 44191500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 44191500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 187933146 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 187933146 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 187933146 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35196.830692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35196.830692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35196.830692 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34989.311164 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34989.311164 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34989.311164 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,159 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 324 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 324 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 875 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 875 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 875 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 355 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 355 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 355 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 30921000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 30921000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 30921000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 32070500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32070500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32070500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35338.285714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35319.933921 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460957 # number of replacements -system.cpu.dcache.tagsinuse 4095.145869 # Cycle average of tags in use -system.cpu.dcache.total_refs 513034277 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465053 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1103.173782 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317696000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.145869 # Average occupied blocks per context +system.cpu.dcache.replacements 459464 # number of replacements +system.cpu.dcache.tagsinuse 4095.142322 # Cycle average of tags in use +system.cpu.dcache.total_refs 510865684 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463560 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1102.048675 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317747000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.142322 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 326108931 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186925346 # number of WriteReq hits -system.cpu.dcache.demand_hits 513034277 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 513034277 # number of overall hits -system.cpu.dcache.ReadReq_misses 218266 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1260711 # number of WriteReq misses -system.cpu.dcache.demand_misses 1478977 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1478977 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2205272500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24390827496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 26596099996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 26596099996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 326327197 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 323944700 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186920984 # number of WriteReq hits +system.cpu.dcache.demand_hits 510865684 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 510865684 # number of overall hits +system.cpu.dcache.ReadReq_misses 217118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1265073 # number of WriteReq misses +system.cpu.dcache.demand_misses 1482191 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1482191 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2201155000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24662905498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 26864060498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 26864060498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 324161818 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 514513254 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 514513254 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000669 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006699 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002875 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002875 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10103.600652 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19346.882431 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17982.767816 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17982.767816 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 474736000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29560 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16060.081191 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses 512347875 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 512347875 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000670 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006722 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.002893 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002893 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10138.058567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19495.242961 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18124.560531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18124.560531 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1608500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 471924500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 447 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29514 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3598.434004 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15989.852273 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 411400 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3331 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1010593 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1013924 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1013924 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 214935 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 250118 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 465053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 465053 # number of overall MSHR misses +system.cpu.dcache.writebacks 410359 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3236 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1015395 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1018631 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1018631 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213882 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249678 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463560 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463560 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1536673000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2518183497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4054856497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4054856497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1535369000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2499634500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4035003500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4035003500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7149.477749 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10067.981901 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.579778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10011.432725 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73679 # number of replacements -system.cpu.l2cache.tagsinuse 18021.980204 # Cycle average of tags in use -system.cpu.l2cache.total_refs 455469 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.101465 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73641 # number of replacements +system.cpu.l2cache.tagsinuse 18052.437933 # Cycle average of tags in use +system.cpu.l2cache.total_refs 453217 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89251 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.078005 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1918.737195 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16103.243009 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058555 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491432 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 182682 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 411400 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 191297 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 373979 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 373979 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33118 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58831 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91949 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91949 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130130500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2026415500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3156546000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3156546000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 215800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 411400 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 250128 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 465928 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 465928 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.153466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235204 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197346 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197346 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34124.358355 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34444.689024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34329.312989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34329.312989 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1921.052649 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16131.385284 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.492291 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181658 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410359 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190902 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372560 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372560 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33126 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58782 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91908 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91908 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130437500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2022399000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3152836500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3152836500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214784 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410359 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249684 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464468 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464468 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154229 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235426 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197878 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197878 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34125.384894 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.072982 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34304.266223 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34304.266223 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1076.388889 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58539 # number of writebacks +system.cpu.l2cache.writebacks 58527 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33118 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58831 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91949 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33126 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58782 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91908 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91908 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026873000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832918500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2859791500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2859791500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1027129500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1831638000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2858767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2858767500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235204 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197346 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197346 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.491938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.657731 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154229 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235426 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197878 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.746966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31159.844850 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |