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authorAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-08-12 19:43:55 -0400
commitd114e5fae6ffb83a1145208532def7654cc9dd75 (patch)
treed54b53635428baefbb0ef25715e1059a2bad1185 /tests/long/00.gzip
parent02353a60ee6ce831302067aae38bc31b739f14e5 (diff)
downloadgem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz
Regression: Update stats for cache changes.
--HG-- extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/long/00.gzip')
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini38
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt193
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini51
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt578
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout8
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini38
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt215
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout8
8 files changed, 588 insertions, 541 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index f82815f7b..16b6c6fda 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
@@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
index 9d4ab211d..eaccc0729 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 494073 # Simulator instruction rate (inst/s)
-host_mem_usage 153964 # Number of bytes of host memory used
-host_seconds 1218.16 # Real time elapsed on the host
-host_tick_rate 624626994 # Simulator tick rate (ticks/s)
+host_inst_rate 1799420 # Simulator instruction rate (inst/s)
+host_mem_usage 199568 # Number of bytes of host memory used
+host_seconds 334.47 # Real time elapsed on the host
+host_tick_rate 2297009943 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856965 # Number of instructions simulated
-sim_seconds 0.760893 # Number of seconds simulated
-sim_ticks 760892614000 # Number of ticks simulated
+sim_seconds 0.768288 # Number of seconds simulated
+sim_ticks 768287940000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4754380000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 4351916000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8222275000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7564493000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
@@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 24478.573840 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 12976655000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 11916409000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24478.573840 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22478.573840 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 153509968 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 455395 # number of overall misses
+system.cpu.dcache.overall_hits 153435240 # number of overall hits
+system.cpu.dcache.overall_miss_latency 12976655000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 530123 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 11916409000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4094.970134 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 342925000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks
system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 18285000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 18285000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 601856171 # number of overall hits
-system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 795 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 18285000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,57 +138,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 673.685789 # Cycle average of tags in use
system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5591586000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2795793000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 23035 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3937824000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.885981 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 178992 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1968912000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885981 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 178992 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 1644016000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 325723 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 325723 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.500034 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 23035 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9529410000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.949506 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 433155 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4764705000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.949506 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 433155 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 755815 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 26098 # number of overall misses
+system.cpu.l2cache.overall_hits 23035 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9529410000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.949506 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 433155 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4764705000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.949506 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 433155 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -200,15 +221,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 903 # number of replacements
-system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 13394 # number of replacements
+system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 8423.446687 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 883 # number of writebacks
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 760892614000 # number of cpu cycles simulated
+system.cpu.numCycles 768287940000 # number of cpu cycles simulated
system.cpu.num_insts 601856965 # Number of instructions executed
system.cpu.num_refs 154862034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 585239418..1ce1e7585 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
+children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -86,6 +86,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
+tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@@ -95,16 +96,15 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -118,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -139,11 +137,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
-children=opList0
+children=opList
count=6
-opList=system.cpu.fuPool.FUList0.opList0
+opList=system.cpu.fuPool.FUList0.opList
-[system.cpu.fuPool.FUList0.opList0]
+[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@@ -217,11 +215,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList4.opList0
+opList=system.cpu.fuPool.FUList4.opList
-[system.cpu.fuPool.FUList4.opList0]
+[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@@ -229,11 +227,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
-children=opList0
+children=opList
count=0
-opList=system.cpu.fuPool.FUList5.opList0
+opList=system.cpu.fuPool.FUList5.opList
-[system.cpu.fuPool.FUList5.opList0]
+[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@@ -259,11 +257,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0
+children=opList
count=1
-opList=system.cpu.fuPool.FUList7.opList0
+opList=system.cpu.fuPool.FUList7.opList
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -271,16 +269,15 @@ opLat=3
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -294,12 +291,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@@ -310,16 +305,15 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
@@ -333,12 +327,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -356,6 +348,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
index 929354b82..47c1d93f0 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt
@@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 155497873 # Number of BTB hits
-global.BPredUnit.BTBLookups 176569029 # Number of BTB lookups
+global.BPredUnit.BTBHits 183168209 # Number of BTB hits
+global.BPredUnit.BTBLookups 207693172 # Number of BTB lookups
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 90327270 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 223339092 # Number of conditional branches predicted
-global.BPredUnit.lookups 223339092 # Number of BP lookups
+global.BPredUnit.condIncorrect 83686538 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 256168234 # Number of conditional branches predicted
+global.BPredUnit.lookups 256168234 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 54106 # Simulator instruction rate (inst/s)
-host_mem_usage 156124 # Number of bytes of host memory used
-host_seconds 27529.37 # Real time elapsed on the host
-host_tick_rate 45674334 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 464625781 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 155659586 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 751805606 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 305482201 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 108517 # Simulator instruction rate (inst/s)
+host_mem_usage 202532 # Number of bytes of host memory used
+host_seconds 13726.13 # Real time elapsed on the host
+host_tick_rate 80131991 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 457134527 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 154100032 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 745124340 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 301027499 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1489514762 # Number of instructions simulated
-sim_seconds 1.257386 # Number of seconds simulated
-sim_ticks 1257385552000 # Number of ticks simulated
+sim_insts 1489514761 # Number of instructions simulated
+sim_seconds 1.099902 # Number of seconds simulated
+sim_ticks 1099901861500 # Number of ticks simulated
system.cpu.commit.COM:branches 86246390 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 9313657 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 9028629 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 2273477268
+system.cpu.commit.COM:committed_per_cycle.samples 1956850179
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 1413600532 6217.79%
- 1 557883273 2453.88%
- 2 123364539 542.62%
- 3 120963543 532.06%
- 4 18884040 83.06%
- 5 12171132 53.54%
- 6 9965158 43.83%
- 7 7331394 32.25%
- 8 9313657 40.97%
+ 0 1082285235 5530.75%
+ 1 575067444 2938.74%
+ 2 119112331 608.69%
+ 3 121687931 621.86%
+ 4 26918285 137.56%
+ 5 9398970 48.03%
+ 6 9197638 47.00%
+ 7 4153716 21.23%
+ 8 9028629 46.14%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 1489514762 # Number of instructions committed
-system.cpu.commit.COM:loads 402511689 # Number of loads committed
+system.cpu.commit.COM:count 1489514761 # Number of instructions committed
+system.cpu.commit.COM:loads 402511688 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
-system.cpu.commit.COM:refs 569359657 # Number of memory references committed
+system.cpu.commit.COM:refs 569359656 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 90327270 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 1489514762 # The number of committed instructions
+system.cpu.commit.branchMispredicts 83686538 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1489514761 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243499 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1399513618 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1489514762 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1489514762 # Number of Instructions Simulated
-system.cpu.cpi 1.688316 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.688316 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 431095835 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 2842.252413 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2392.500580 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 430168385 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2636047000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.002151 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 927450 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 694672 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 556921500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000540 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 232778 # number of ReadReq MSHR misses
+system.cpu.commit.commitSquashedInsts 1386494932 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1489514761 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1489514761 # Number of Instructions Simulated
+system.cpu.cpi 1.476859 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.476859 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 432423106 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 21577.217813 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4456.675710 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 432175035 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5352682000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 248071 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 707847 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1105572000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000574 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 248071 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 24500 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 17500 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3889.592412 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3171.120393 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 165155866 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6576429500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010134 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1690776 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1420478 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 857147500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001620 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 270298 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency 7012.500000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5012.500000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 280500 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 200500 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 165036365 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 45516.173877 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5913.886312 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 164687129 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 15895886500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.002116 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 349236 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1810277 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2065342000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002116 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 349236 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1183.354576 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1139.085750 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 597942477 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3518.594842 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2810.845677 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 595324251 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 9212476500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.004379 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2618226 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2115150 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1414069000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000841 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 503076 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 597459471 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35573.948573 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 596862164 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 21248568500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.001000 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 597307 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2518124 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3170914000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.001000 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 597307 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 597942477 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3518.594842 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2810.845677 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 597459471 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35573.948573 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 595324251 # number of overall hits
-system.cpu.dcache.overall_miss_latency 9212476500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.004379 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2618226 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2115150 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1414069000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000841 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 503076 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 596862164 # number of overall hits
+system.cpu.dcache.overall_miss_latency 21248568500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.001000 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 597307 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2518124 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3170914000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.001000 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 597307 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 498987 # number of replacements
-system.cpu.dcache.sampled_refs 503083 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 519953 # number of replacements
+system.cpu.dcache.sampled_refs 524049 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.797134 # Cycle average of tags in use
-system.cpu.dcache.total_refs 595325570 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 77974000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 335737 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 435745843 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3276032607 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 1073744654 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 761619600 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 241293837 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 2367171 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 223339092 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 355860305 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1166695920 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 14770227 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3591774268 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 93734364 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.088811 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 355860305 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 155497873 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.428271 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4095.788106 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596936748 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 72857000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 346070 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 407153301 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3453639261 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 763587746 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 783418811 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 242953531 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 2690321 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 256168234 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 355186488 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1201174807 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 10202313 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3743631874 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 91259594 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.116450 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 355186488 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 183168209 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.701803 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 2514771105
+system.cpu.fetch.rateDist.samples 2199803710
system.cpu.fetch.rateDist.min_value 0
- 0 1703935491 6775.71%
- 1 252157679 1002.71%
- 2 75632424 300.75%
- 3 38096592 151.49%
- 4 76680653 304.92%
- 5 30840750 122.64%
- 6 33076966 131.53%
- 7 20130593 80.05%
- 8 284219957 1130.20%
+ 0 1353815392 6154.26%
+ 1 255570605 1161.79%
+ 2 82946121 377.06%
+ 3 38413739 174.62%
+ 4 83998079 381.84%
+ 5 40983172 186.30%
+ 6 33041033 150.20%
+ 7 20511116 93.24%
+ 8 290524453 1320.68%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 355860305 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5111.111111 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4198.640483 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 355858946 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6946000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 355186427 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 7448.556625 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5296.447076 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 355185076 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 10063000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1359 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 5559000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 1351 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 7155500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 1324 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 1351 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 268775.638973 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 262905.311621 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 355860305 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5111.111111 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4198.640483 # average overall mshr miss latency
-system.cpu.icache.demand_hits 355858946 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6946000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 355186427 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 7448.556625 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency
+system.cpu.icache.demand_hits 355185076 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 10063000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1359 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 5559000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 1351 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 61 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 7155500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 1324 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 1351 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 355860305 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5111.111111 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4198.640483 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 355186427 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 7448.556625 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 355858946 # number of overall hits
-system.cpu.icache.overall_miss_latency 6946000 # number of overall miss cycles
+system.cpu.icache.overall_hits 355185076 # number of overall hits
+system.cpu.icache.overall_miss_latency 10063000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1359 # number of overall misses
-system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 5559000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 1351 # number of overall misses
+system.cpu.icache.overall_mshr_hits 61 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 7155500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 1324 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 1351 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -222,166 +222,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 198 # number of replacements
-system.cpu.icache.sampled_refs 1324 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 207 # number of replacements
+system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1026.431065 # Cycle average of tags in use
-system.cpu.icache.total_refs 355858946 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1040.211796 # Cycle average of tags in use
+system.cpu.icache.total_refs 355185076 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1497 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 128998684 # Number of branches executed
+system.cpu.idleCycles 8497 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 126707080 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.879999 # Inst execution rate
-system.cpu.iew.EXEC:refs 756340485 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 208683785 # Number of stores executed
+system.cpu.iew.EXEC:rate 1.003361 # Inst execution rate
+system.cpu.iew.EXEC:refs 760962527 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 208093186 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1511846593 # num instructions consuming a value
-system.cpu.iew.WB:count 2184193190 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.964010 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1493645383 # num instructions consuming a value
+system.cpu.iew.WB:count 2165444744 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.962819 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1457435157 # num instructions producing a value
-system.cpu.iew.WB:rate 0.868546 # insts written-back per cycle
-system.cpu.iew.WB:sent 2194556483 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 93921260 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 242324 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 751805606 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21112863 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 6967923 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 305482201 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2889028359 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 547656700 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 155922171 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2212995141 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1438109572 # num instructions producing a value
+system.cpu.iew.WB:rate 0.984381 # insts written-back per cycle
+system.cpu.iew.WB:sent 2178310152 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 91514542 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 458290 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 745124340 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21362312 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 17090675 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 301027499 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2876000922 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 552869341 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 140121943 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2207196457 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 56098 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 241293837 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 1173 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 8365 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 242953531 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 87287 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 116560202 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 586068 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 119737756 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 85786 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3827981 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 59 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 349293917 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 138634233 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3827981 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1127857 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 92793403 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.592306 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.592306 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 2368917312 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 10100571 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 31 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 342612652 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 134179531 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 10100571 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1514083 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 90000459 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.677113 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.677113 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 2347318400 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
- No_OpClass 351375247 14.83% # Type of FU issued
- IntAlu 1188705257 50.18% # Type of FU issued
+ No_OpClass 351441317 14.97% # Type of FU issued
+ IntAlu 1181231771 50.32% # Type of FU issued
IntMult 0 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2951238 0.12% # Type of FU issued
+ FloatAdd 3000185 0.13% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 592531661 25.01% # Type of FU issued
- MemWrite 233353909 9.85% # Type of FU issued
+ MemRead 586473179 24.98% # Type of FU issued
+ MemWrite 225171948 9.59% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 6622922 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.002796 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 3997880 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.001703 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
- IntAlu 3150287 47.57% # attempts to use FU when none available
+ IntAlu 155579 3.89% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 202242 3.05% # attempts to use FU when none available
+ FloatAdd 244024 6.10% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 2975364 44.93% # attempts to use FU when none available
- MemWrite 295029 4.45% # attempts to use FU when none available
+ MemRead 3267233 81.72% # attempts to use FU when none available
+ MemWrite 331044 8.28% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 2514771105
+system.cpu.iq.ISSUE:issued_per_cycle.samples 2199803710
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 1264571415 5028.57%
- 1 618163663 2458.13%
- 2 318214573 1265.38%
- 3 195947630 779.19%
- 4 78232851 311.09%
- 5 28085074 111.68%
- 6 8167595 32.48%
- 7 2987163 11.88%
- 8 401141 1.60%
+ 0 993478594 4516.21%
+ 1 570157916 2591.86%
+ 2 321116547 1459.75%
+ 3 178901320 813.26%
+ 4 92584833 420.88%
+ 5 34984610 159.04%
+ 6 7286511 33.12%
+ 7 1105050 5.02%
+ 8 188329 0.86%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.942001 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2867645475 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2368917312 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21382884 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1368214032 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 461256 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 19139385 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 1296493196 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 504406 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4393.799833 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2267.430007 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 476939 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 120684500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.054454 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 27467 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 62279500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054454 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 27467 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 335737 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 335720 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.000051 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 17 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.000051 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 17 # number of Writeback MSHR misses
+system.cpu.iq.ISSUE:rate 1.067058 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2854330173 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2347318400 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21670749 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1311892803 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 993660 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 19427250 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1293606933 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 275979 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 4897.575540 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2897.575540 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1351628000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 275979 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 799670000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 275979 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 249421 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4201.208939 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2201.208939 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 64300 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 777732000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.742203 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 185121 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 407490000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.742203 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 185121 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 73301 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 4221.136137 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2221.136137 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 309413500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 73301 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 162811500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 73301 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 346070 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 346070 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 346070 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 29.586740 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.935065 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 504406 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4393.799833 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2267.430007 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 476939 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 120684500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.054454 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 27467 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 525400 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4618.000434 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 64300 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 2129360000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.877617 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 461100 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 62279500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.054454 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 27467 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 1207160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.877617 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 461100 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 840143 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4391.082084 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2267.430007 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 525400 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4618.000434 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 812659 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 120684500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.032713 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 27484 # number of overall misses
+system.cpu.l2cache.overall_hits 64300 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 2129360000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.877617 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 461100 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 62279500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.032693 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 27467 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 1207160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.877617 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 461100 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -393,30 +410,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2692 # number of replacements
-system.cpu.l2cache.sampled_refs 27467 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 19390 # number of replacements
+system.cpu.l2cache.sampled_refs 20790 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 24466.224839 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 812659 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 8555.838166 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 102600 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 2555 # number of writebacks
-system.cpu.numCycles 2514771105 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 14153952 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1244762263 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 845 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 1122858502 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 18964355 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 4974059876 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3105364972 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2435580679 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 713636177 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 241293837 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 24303898 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1190818416 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 398524739 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 21495577 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 149561373 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21338548 # count of temporary serializing insts renamed
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 2199803710 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 12980165 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1244762261 # Number of HB maps that are committed
+system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers
+system.cpu.rename.RENAME:IQFullEvents 40711 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 826156851 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 20049545 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 4942866473 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3108910588 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2431469653 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 720639508 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 242953531 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 28416809 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1186707392 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 368656846 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 21929426 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 159084902 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21683995 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
index c0d965c7b..0785768bd 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout
@@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jun 21 2007 21:15:48
-M5 started Fri Jun 22 01:01:27 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 12:23:15
+M5 started Sun Aug 12 12:23:18 2007
+M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1257385552000 because target called exit()
+Exiting @ tick 1099901861500 because target called exit()
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index ad1db1010..8f0821576 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
+children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@@ -24,27 +24,28 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
+tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -52,12 +53,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=262144
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -68,21 +67,21 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=1000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -90,12 +89,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=131072
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -106,21 +103,21 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
-adaptive_compression=false
+addr_range=0:18446744073709551615
assoc=2
block_size=64
-compressed_bus=false
-compression_latency=0
+cpu_side_filter_ranges=
hash_delay=1
latency=10000
lifo=false
max_miss_count=0
+mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
-prefetch_latency=10
+prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@@ -128,12 +125,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
-protocol=Null
repl=Null
size=2097152
split=false
split_size=0
-store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@@ -151,6 +146,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+[system.cpu.tracer]
+type=ExeTracer
+
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
@@ -174,7 +172,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
index fc8b89b1e..e732be59f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
@@ -1,43 +1,43 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 529254 # Simulator instruction rate (inst/s)
-host_mem_usage 154916 # Number of bytes of host memory used
-host_seconds 2814.36 # Real time elapsed on the host
-host_tick_rate 733354350 # Simulator tick rate (ticks/s)
+host_inst_rate 1190065 # Simulator instruction rate (inst/s)
+host_mem_usage 201788 # Number of bytes of host memory used
+host_seconds 1251.63 # Real time elapsed on the host
+host_tick_rate 1654548560 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated
-sim_seconds 2.063927 # Number of seconds simulated
-sim_ticks 2063926516000 # Number of ticks simulated
+sim_seconds 2.070875 # Number of seconds simulated
+sim_ticks 2070875212000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks.
@@ -47,31 +47,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 568905105 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 453225 # number of overall misses
+system.cpu.dcache.overall_hits 568845227 # number of overall hits
+system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 513103 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.520244 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 358125000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 25230000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 25230000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1489513763 # number of overall hits
-system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 1098 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 25230000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -148,61 +148,78 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 891.566276 # Cycle average of tags in use
system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 316438 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.000028 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 9 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.000028 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 9 # number of Writeback MSHR misses
+system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 27.352695 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency
+system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 743583 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 27194 # number of overall misses
+system.cpu.l2cache.overall_hits 28424 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 425906 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@@ -214,15 +231,15 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2632 # number of replacements
-system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 18201 # number of replacements
+system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 8449.172652 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 2531 # number of writebacks
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 2063926516000 # number of cpu cycles simulated
+system.cpu.numCycles 2070875212000 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
index 3741c6499..6d07eec7c 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
@@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled May 15 2007 13:02:31
-M5 started Tue May 15 13:36:53 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 12 2007 12:23:15
+M5 started Sun Aug 12 16:24:16 2007
+M5 executing on zeep
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 2063926516000 because target called exit()
+Exiting @ tick 2070875212000 because target called exit()