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authorGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-28 07:24:01 -0800
commitc3d41a2def15cdaf2ac3984315f452dacc6a0884 (patch)
tree5324ebec3add54b934a841eee901983ac3463a7f /tests/long/00.gzip
parentda2a4acc26ba264c3c4a12495776fd6a1c4fb133 (diff)
parent4acca8a0536d4445ed25b67edf571ae460446ab9 (diff)
downloadgem5-c3d41a2def15cdaf2ac3984315f452dacc6a0884.tar.xz
Merge with the main repo.
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'tests/long/00.gzip')
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini8
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini13
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini11
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/simple-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini13
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-atomic/simout16
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt109
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini11
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/00.gzip/ref/arm/linux/simple-timing/simout16
-rw-r--r--tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt475
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt19
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini10
-rwxr-xr-xtests/long/00.gzip/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt19
41 files changed, 599 insertions, 444 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index b6c1d1a1d..6c1c0e974 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
@@ -182,7 +184,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -205,7 +207,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -224,7 +226,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -234,5 +236,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 9da502021..30b31a527 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 8 2011 15:00:53
-gem5 started Jul 8 2011 16:09:24
-gem5 executing on u200439-lin.austin.arm.com
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index ec1428295..b5662ac02 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.274500 # Number of seconds simulated
sim_ticks 274500333500 # Number of ticks simulated
+final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56944 # Simulator instruction rate (inst/s)
-host_tick_rate 25971361 # Simulator tick rate (ticks/s)
-host_mem_usage 245756 # Number of bytes of host memory used
-host_seconds 10569.35 # Real time elapsed on the host
+host_inst_rate 113367 # Simulator instruction rate (inst/s)
+host_tick_rate 51705325 # Simulator tick rate (ticks/s)
+host_mem_usage 207980 # Number of bytes of host memory used
+host_seconds 5308.94 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+system.physmem.bytes_read 5894016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3798080 # Number of bytes written to this memory
+system.physmem.num_reads 92094 # Number of read requests responded to by this memory
+system.physmem.num_writes 59345 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index b11fadb7f..cc9b0c683 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index 9acd0ed7e..ad1c408b1 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 16:10:02
-gem5 started Aug 20 2011 16:10:09
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
gem5 executing on zizzer
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index bcb696265..8681db468 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.144450 # Number of seconds simulated
sim_ticks 144450185500 # Number of ticks simulated
+final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 180758 # Simulator instruction rate (inst/s)
-host_tick_rate 46168195 # Simulator tick rate (ticks/s)
-host_mem_usage 205240 # Number of bytes of host memory used
-host_seconds 3128.78 # Real time elapsed on the host
+host_inst_rate 205040 # Simulator instruction rate (inst/s)
+host_tick_rate 52370107 # Simulator tick rate (ticks/s)
+host_mem_usage 208620 # Number of bytes of host memory used
+host_seconds 2758.26 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
+system.physmem.bytes_read 5936768 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3797120 # Number of bytes written to this memory
+system.physmem.num_reads 92762 # Number of read requests responded to by this memory
+system.physmem.num_writes 59330 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 355960d42..282141772 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 7ce6e1e9f..1dc402141 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:20:39
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index b2d2b0068..ad4f39b85 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.300931 # Number of seconds simulated
sim_ticks 300930958000 # Number of ticks simulated
+final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3663682 # Simulator instruction rate (inst/s)
-host_tick_rate 1831855621 # Simulator tick rate (ticks/s)
-host_mem_usage 184012 # Number of bytes of host memory used
-host_seconds 164.28 # Real time elapsed on the host
+host_inst_rate 4527143 # Simulator instruction rate (inst/s)
+host_tick_rate 2263589972 # Simulator tick rate (ticks/s)
+host_mem_usage 198960 # Number of bytes of host memory used
+host_seconds 132.94 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 152669504 # Number of bytes written to this memory
+system.physmem.num_reads 716375939 # Number of read requests responded to by this memory
+system.physmem.num_writes 39451321 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 50ef6266f..0bc5277c7 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
index 26ae974dd..36bd68fb7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 19 2011 06:59:13
-gem5 started Jun 20 2011 12:47:45
-gem5 executing on m60-009.pool
-command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 05:24:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 9bcf790a8..4d7850adf 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.765623 # Number of seconds simulated
sim_ticks 765623032000 # Number of ticks simulated
+final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1640067 # Simulator instruction rate (inst/s)
-host_tick_rate 2086331180 # Simulator tick rate (ticks/s)
-host_mem_usage 192652 # Number of bytes of host memory used
-host_seconds 366.97 # Real time elapsed on the host
+host_inst_rate 2199350 # Simulator instruction rate (inst/s)
+host_tick_rate 2797795440 # Simulator tick rate (ticks/s)
+host_mem_usage 207676 # Number of bytes of host memory used
+host_seconds 273.65 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+system.physmem.bytes_read 5889984 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3797824 # Number of bytes written to this memory
+system.physmem.num_reads 92031 # Number of read requests responded to by this memory
+system.physmem.num_writes 59341 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
index 158bcba97..9f24d0367 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
index c90a30371..d3786fda6 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 21 2011 16:28:02
-gem5 started Nov 22 2011 16:59:04
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:31:06
+gem5 executing on zizzer
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 7a98c6c82..5022d17a1 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.177099 # Number of seconds simulated
sim_ticks 177098873000 # Number of ticks simulated
+final_tick 177098873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166594 # Simulator instruction rate (inst/s)
-host_tick_rate 48979898 # Simulator tick rate (ticks/s)
-host_mem_usage 214636 # Number of bytes of host memory used
-host_seconds 3615.75 # Real time elapsed on the host
+host_inst_rate 154897 # Simulator instruction rate (inst/s)
+host_tick_rate 45541130 # Simulator tick rate (ticks/s)
+host_mem_usage 220436 # Number of bytes of host memory used
+host_seconds 3888.77 # Real time elapsed on the host
sim_insts 602359805 # Number of instructions simulated
+system.physmem.bytes_read 5833856 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3720192 # Number of bytes written to this memory
+system.physmem.num_reads 91154 # Number of read requests responded to by this memory
+system.physmem.num_writes 58128 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 32941237 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 265253 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 21006300 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 53947537 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 17d38a039..8c7671d34 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -44,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=ArmTLB
@@ -61,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -85,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -95,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
index ceb1053f2..95da0efca 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:47:58
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:36:54
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index 2dd995d75..f48dc3640 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
@@ -1,76 +1,87 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 2791643 # Simulator instruction rate (inst/s)
-host_mem_usage 253504 # Number of bytes of host memory used
-host_seconds 215.77 # Real time elapsed on the host
-host_tick_rate 1395873441 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 602359851 # Number of instructions simulated
sim_seconds 0.301191 # Number of seconds simulated
sim_ticks 301191370000 # Number of ticks simulated
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 2998309 # Simulator instruction rate (inst/s)
+host_tick_rate 1499211130 # Simulator tick rate (ticks/s)
+host_mem_usage 210136 # Number of bytes of host memory used
+host_seconds 200.90 # Real time elapsed on the host
+sim_insts 602359851 # Number of instructions simulated
+system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 236359611 # Number of bytes written to this memory
+system.physmem.num_reads 717867713 # Number of read requests responded to by this memory
+system.physmem.num_writes 69418858 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 8898529055 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7570927866 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 784748949 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 9683278004 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 602382741 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 602382741 # Number of busy cycles
-system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 1993546 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 602359851 # Number of instructions executed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 1993546 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
system.cpu.num_int_insts 533522639 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
-system.cpu.num_load_insts 148952594 # Number of load instructions
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 219173607 # number of memory refs
+system.cpu.num_load_insts 148952594 # Number of load instructions
system.cpu.num_store_insts 70221013 # Number of store instructions
-system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 602382741 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
index f2a118cfd..6a1e2b970 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -146,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -164,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
@@ -188,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -198,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
index eabe42249..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
index 99cb1ccc7..589b03862 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,14 +1,10 @@
-M5 Simulator System
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Apr 19 2011 12:47:10
-M5 started Apr 19 2011 12:48:29
-M5 executing on maize
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 08:40:26
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
index ba03a3195..3846f97fb 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,269 +1,280 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1298278 # Simulator instruction rate (inst/s)
-host_mem_usage 260992 # Number of bytes of host memory used
-host_seconds 462.46 # Real time elapsed on the host
-host_tick_rate 1722888732 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 600398281 # Number of instructions simulated
sim_seconds 0.796763 # Number of seconds simulated
sim_ticks 796762926000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
-system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 216771819 # number of overall hits
-system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 437564 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 433468 # number of replacements
-system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
-system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 392392 # number of writebacks
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 1450316 # Simulator instruction rate (inst/s)
+host_tick_rate 1924652930 # Simulator tick rate (ticks/s)
+host_mem_usage 219100 # Number of bytes of host memory used
+host_seconds 413.98 # Real time elapsed on the host
+sim_insts 600398281 # Number of instructions simulated
+system.physmem.bytes_read 5759488 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3704704 # Number of bytes written to this memory
+system.physmem.num_reads 89992 # Number of read requests responded to by this memory
+system.physmem.num_writes 57886 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.numCycles 1593525852 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 600398281 # Number of instructions executed
+system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
+system.cpu.num_func_calls 1993546 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
+system.cpu.num_int_insts 533522639 # number of integer instructions
+system.cpu.num_fp_insts 16 # number of float instructions
+system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
+system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 219173607 # number of memory refs
+system.cpu.num_load_insts 148952594 # Number of load instructions
+system.cpu.num_store_insts 70221013 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.icache.replacements 12 # number of replacements
+system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
+system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
+system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits
+system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
+system.cpu.icache.overall_hits 570073892 # number of overall hits
+system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
+system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
+system.cpu.icache.overall_misses 643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
-system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
-system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
+system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 570073892 # number of overall hits
-system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.overall_misses 643 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 12 # number of replacements
-system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
-system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 433468 # number of replacements
+system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
+system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits 216771819 # number of overall hits
+system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
+system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses 437564 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks 392392 # number of writebacks
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 71804 # number of replacements
+system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits 348215 # number of overall hits
+system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
+system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses 89992 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
+system.cpu.l2cache.writebacks 57886 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
-system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 348215 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 89992 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 71804 # number of replacements
-system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 57886 # number of writebacks
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1593525852 # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
-system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_func_calls 1993546 # number of times a function call or return occured
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 600398281 # Number of instructions executed
-system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
-system.cpu.num_int_insts 533522639 # number of integer instructions
-system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
-system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
-system.cpu.num_load_insts 148952594 # Number of load instructions
-system.cpu.num_mem_refs 219173607 # number of memory refs
-system.cpu.num_store_insts 70221013 # Number of store instructions
-system.cpu.workload.num_syscalls 48 # Number of system calls
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
index f1874f64f..dcba73ec2 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -495,7 +497,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index df0fa130a..a835cbd79 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:17:40
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 8c5bfcb3c..e4d9fca07 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.408816 # Number of seconds simulated
sim_ticks 408816360000 # Number of ticks simulated
+final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 252046 # Simulator instruction rate (inst/s)
-host_tick_rate 73306837 # Simulator tick rate (ticks/s)
-host_mem_usage 206388 # Number of bytes of host memory used
-host_seconds 5576.78 # Real time elapsed on the host
+host_inst_rate 175830 # Simulator instruction rate (inst/s)
+host_tick_rate 51139829 # Simulator tick rate (ticks/s)
+host_mem_usage 215728 # Number of bytes of host memory used
+host_seconds 7994.10 # Real time elapsed on the host
sim_insts 1405604152 # Number of instructions simulated
+system.physmem.bytes_read 6021376 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3792448 # Number of bytes written to this memory
+system.physmem.num_reads 94084 # Number of read requests responded to by this memory
+system.physmem.num_writes 59257 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 14728804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 200070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 9276654 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 24005458 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 817632721 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index 864c2771b..b52495d06 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=SparcTLB
@@ -62,7 +64,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
index 3eb09159b..d2df5cc09 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:18:03
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
index ae12e23e4..afe2bae4f 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.744764 # Number of seconds simulated
sim_ticks 744764119000 # Number of ticks simulated
+final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4241689 # Simulator instruction rate (inst/s)
-host_tick_rate 2120851440 # Simulator tick rate (ticks/s)
-host_mem_usage 196528 # Number of bytes of host memory used
-host_seconds 351.16 # Real time elapsed on the host
+host_inst_rate 3773289 # Simulator instruction rate (inst/s)
+host_tick_rate 1886650577 # Simulator tick rate (ticks/s)
+host_mem_usage 205844 # Number of bytes of host memory used
+host_seconds 394.75 # Real time elapsed on the host
sim_insts 1489523295 # Number of instructions simulated
+system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 614672063 # Number of bytes written to this memory
+system.physmem.num_reads 1887625855 # Number of read requests responded to by this memory
+system.physmem.num_writes 166846816 # Number of write requests responded to by this memory
+system.physmem.num_other 1326 # Number of other requests responded to by this memory
+system.physmem.bw_read 9837033566 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7976286575 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 825324485 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10662358051 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
index 6dbddf888..ea98a23a1 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -165,7 +167,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
index 4a77ef60d..b26fb3f41 100755
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2011 17:14:16
-gem5 started Nov 30 2011 17:16:48
+gem5 compiled Jan 23 2012 04:02:00
+gem5 started Jan 23 2012 06:19:05
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index d75fccee8..059312926 100644
--- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.064259 # Number of seconds simulated
sim_ticks 2064258667000 # Number of ticks simulated
+final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2284016 # Simulator instruction rate (inst/s)
-host_tick_rate 3165307188 # Simulator tick rate (ticks/s)
-host_mem_usage 205232 # Number of bytes of host memory used
-host_seconds 652.15 # Real time elapsed on the host
+host_inst_rate 1766930 # Simulator instruction rate (inst/s)
+host_tick_rate 2448703239 # Simulator tick rate (ticks/s)
+host_mem_usage 214556 # Number of bytes of host memory used
+host_seconds 843.00 # Real time elapsed on the host
sim_insts 1489523295 # Number of instructions simulated
+system.physmem.bytes_read 5909952 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3778240 # Number of bytes written to this memory
+system.physmem.num_reads 92343 # Number of read requests responded to by this memory
+system.physmem.num_writes 59035 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
index c626036a3..42f7aa66f 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
@@ -477,7 +479,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +502,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -519,7 +521,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -529,5 +531,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
index d3f649818..48ae315a0 100755
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:28:24
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 9655899ee..802bd6f5d 100644
--- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.586294 # Number of seconds simulated
sim_ticks 586294224000 # Number of ticks simulated
+final_tick 586294224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 115446 # Simulator instruction rate (inst/s)
-host_tick_rate 41742717 # Simulator tick rate (ticks/s)
-host_mem_usage 244900 # Number of bytes of host memory used
-host_seconds 14045.43 # Real time elapsed on the host
+host_inst_rate 145094 # Simulator instruction rate (inst/s)
+host_tick_rate 52462700 # Simulator tick rate (ticks/s)
+host_mem_usage 215548 # Number of bytes of host memory used
+host_seconds 11175.48 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated
+system.physmem.bytes_read 5880640 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 56960 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3744192 # Number of bytes written to this memory
+system.physmem.num_reads 91885 # Number of read requests responded to by this memory
+system.physmem.num_writes 58503 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 10030186 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 97153 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 6386200 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 16416386 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1172588449 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
index dd4d7f0aa..393d71365 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -45,8 +47,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=X86TLB
@@ -67,7 +69,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -86,7 +88,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
@@ -96,5 +98,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
index 510b69206..3da3c7641 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:33:19
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
index a5e9437b0..3a54bb2c8 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992704000 # Number of ticks simulated
+final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1220339 # Simulator instruction rate (inst/s)
-host_tick_rate 725502264 # Simulator tick rate (ticks/s)
-host_mem_usage 234168 # Number of bytes of host memory used
-host_seconds 1328.72 # Real time elapsed on the host
+host_inst_rate 2202720 # Simulator instruction rate (inst/s)
+host_tick_rate 1309536712 # Simulator tick rate (ticks/s)
+host_mem_usage 204800 # Number of bytes of host memory used
+host_seconds 736.13 # Real time elapsed on the host
sim_insts 1621493983 # Number of instructions simulated
+system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 864451000 # Number of bytes written to this memory
+system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory
+system.physmem.num_writes 188186057 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
index 129642a98..f841786ec 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
+num_work_ids=16
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
+system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -147,7 +149,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
+mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
type=Bus
@@ -170,7 +172,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
@@ -189,7 +191,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -199,5 +201,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[0]
+port=system.membus.port[1]
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
index 613f79639..c3d33da65 100755
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 9 2012 14:18:02
-gem5 started Jan 9 2012 14:29:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Jan 23 2012 04:08:34
+gem5 started Jan 23 2012 06:37:10
+gem5 executing on zizzer
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
index 5aedfb687..8e512b7b9 100644
--- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -2,12 +2,23 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.803259 # Number of seconds simulated
sim_ticks 1803258587000 # Number of ticks simulated
+final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 760773 # Simulator instruction rate (inst/s)
-host_tick_rate 846053445 # Simulator tick rate (ticks/s)
-host_mem_usage 242892 # Number of bytes of host memory used
-host_seconds 2131.38 # Real time elapsed on the host
+host_inst_rate 1279975 # Simulator instruction rate (inst/s)
+host_tick_rate 1423455894 # Simulator tick rate (ticks/s)
+host_mem_usage 213784 # Number of bytes of host memory used
+host_seconds 1266.82 # Real time elapsed on the host
sim_insts 1621493983 # Number of instructions simulated
+system.physmem.bytes_read 5725952 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 3712448 # Number of bytes written to this memory
+system.physmem.num_reads 89468 # Number of read requests responded to by this memory
+system.physmem.num_writes 58007 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started