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authorNathan Binkert <nate@binkert.org>2009-03-07 14:30:55 -0800
committerNathan Binkert <nate@binkert.org>2009-03-07 14:30:55 -0800
commit5cf060576623f3681b497c46934fb4fe6f8853a6 (patch)
treee9b005046f2118e537528178da5f935dc55dc5c1 /tests/long/00.gzip
parentac7bda0212a22d86d9e24665998f294b96869680 (diff)
downloadgem5-5cf060576623f3681b497c46934fb4fe6f8853a6.tar.xz
tests: update tests because of changes in stat names and in the stats package
Diffstat (limited to 'tests/long/00.gzip')
-rwxr-xr-xtests/long/00.gzip/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt64
-rwxr-xr-xtests/long/00.gzip/ref/sparc/linux/o3-timing/simout10
-rw-r--r--tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt64
4 files changed, 76 insertions, 72 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
index e459fc4f1..0988daaa5 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
+M5 compiled Mar 6 2009 18:15:46
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar 6 2009 18:15:58
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index c5506c5e0..b3f903358 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,25 +1,21 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 65718859 # Number of BTB hits
-global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
-global.BPredUnit.lookups 76039018 # Number of BP lookups
-global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
-host_inst_rate 244512 # Simulator instruction rate (inst/s)
-host_mem_usage 204148 # Number of bytes of host memory used
-host_seconds 2312.99 # Real time elapsed on the host
-host_tick_rate 72234766 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 309694 # Simulator instruction rate (inst/s)
+host_mem_usage 206028 # Number of bytes of host memory used
+host_seconds 1826.17 # Real time elapsed on the host
+host_tick_rate 91491135 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.167078 # Number of seconds simulated
sim_ticks 167078146500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 65718859 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 73181368 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 76039018 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
@@ -298,21 +294,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 332581112
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 92203773 2772.37%
- 1 67051353 2016.09%
- 2 80133780 2409.45%
- 3 36043478 1083.75%
- 4 30084945 904.59%
- 5 14579095 438.36%
- 6 10850493 326.25%
- 7 1143008 34.37%
- 8 491187 14.77%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72%
+system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16%
+system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09%
+system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84%
+system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05%
+system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38%
+system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26%
+system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34%
+system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15%
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::total 332581112
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645
system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate
system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued
@@ -398,6 +396,10 @@ system.cpu.l2cache.tagsinuse 16333.162457 # Cy
system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 63236 # number of writebacks
+system.cpu.memDep0.conflictingLoads 19292303 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 14732751 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 334156294 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
index 4fc3f25f8..b7b45d62c 100755
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 16 2009 00:17:12
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:45:29
-M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing
+M5 compiled Mar 6 2009 18:29:06
+M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
+M5 started Mar 6 2009 18:38:25
+M5 executing on maize
+command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d /n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index 1bd86bd33..a8a069318 100644
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,25 +1,21 @@
---------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 182414509 # Number of BTB hits
-global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
-global.BPredUnit.lookups 254458067 # Number of BP lookups
-global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-host_inst_rate 104414 # Simulator instruction rate (inst/s)
-host_mem_usage 206176 # Number of bytes of host memory used
-host_seconds 13461.92 # Real time elapsed on the host
-host_tick_rate 81909485 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit.
+host_inst_rate 148318 # Simulator instruction rate (inst/s)
+host_mem_usage 208044 # Number of bytes of host memory used
+host_seconds 9477.08 # Real time elapsed on the host
+host_tick_rate 116350072 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618365 # Number of instructions simulated
sim_seconds 1.102659 # Number of seconds simulated
sim_ticks 1102659164000 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 203429504 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 254458067 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
@@ -291,21 +287,23 @@ system.cpu.iq.ISSUE:fu_full.start_dist
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 1083882017 4918.21%
- 1 586425796 2660.96%
- 2 298714416 1355.44%
- 3 164995052 748.68%
- 4 47215795 214.25%
- 5 14943133 67.81%
- 6 6716024 30.47%
- 7 790185 3.59%
- 8 132701 0.60%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
+system.cpu.iq.ISSUE:issued_per_cycle::samples 2203815119
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083882017 49.18%
+system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425796 26.61%
+system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714416 13.55%
+system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995052 7.49%
+system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215795 2.14%
+system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943133 0.68%
+system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716024 0.30%
+system.cpu.iq.ISSUE:issued_per_cycle::7-8 790185 0.04%
+system.cpu.iq.ISSUE:issued_per_cycle::8 132701 0.01%
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::total 2203815119
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866
system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate
system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued
@@ -387,6 +385,10 @@ system.cpu.l2cache.tagsinuse 16402.911294 # Cy
system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 61945 # number of writebacks
+system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 141106006 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 301399355 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 2205318329 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed