diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:25 -0500 |
| commit | 1114be4b78c0855d96004b9f71c61d4b6a050d3a (patch) | |
| tree | eb1e2047d27bd31626530cae97cd9224e1dbbb11 /tests/long/00.gzip | |
| parent | 7dde557fdc51140988092962137e1006d1609bea (diff) | |
| download | gem5-1114be4b78c0855d96004b9f71c61d4b6a050d3a.tar.xz | |
O3: Update stats for memory order violation checking patch.
Diffstat (limited to 'tests/long/00.gzip')
12 files changed, 1515 insertions, 1518 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 41c6a83e0..8d44452f2 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 5ab603e64..6c138b362 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:50 -M5 executing on burrito +M5 compiled Mar 17 2011 21:44:37 +M5 started Mar 17 2011 22:44:08 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 162779779500 because target called exit() +Exiting @ tick 162342217500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 9ddf470e4..93acfbb63 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 121046 # Simulator instruction rate (inst/s) -host_mem_usage 226784 # Number of bytes of host memory used -host_seconds 4672.20 # Real time elapsed on the host -host_tick_rate 34840083 # Simulator tick rate (ticks/s) +host_inst_rate 243015 # Simulator instruction rate (inst/s) +host_mem_usage 208616 # Number of bytes of host memory used +host_seconds 2327.23 # Real time elapsed on the host +host_tick_rate 69757618 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.162780 # Number of seconds simulated -sim_ticks 162779779500 # Number of ticks simulated +sim_seconds 0.162342 # Number of seconds simulated +sim_ticks 162342217500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 63926991 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 71320793 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 193 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4120736 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70355271 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76295210 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1675650 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 19927815 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 20370282 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 315794082 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.905853 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.338192 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 315015358 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.910564 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 102454006 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 100543040 31.84% 64.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 36844526 11.67% 75.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 9307171 2.95% 78.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 10247874 3.25% 82.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21736977 6.88% 89.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 12524254 3.97% 92.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2208419 0.70% 93.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 19927815 6.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 315015358 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 1197610 # Number of function calls committed. @@ -44,352 +44,352 @@ system.cpu.commit.COM:loads 114514042 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 153965363 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4119890 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 60520337 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.575649 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.575649 # CPI: Total CPI of All Threads +system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 112312480 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 15160.742892 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7367.811163 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 111525313 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11934036500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 787167 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 569138 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1606396500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001941 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 218029 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 14279.189894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11300.460826 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38165820 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 18355912888 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.032584 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1285501 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1028584 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2903280494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256917 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.150943 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 315.175064 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 314.821095 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 773498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 151763801 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14613.989982 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149691133 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 30289949388 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.013657 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2072668 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1597722 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4509676994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003130 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 474946 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999550 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.156298 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 151763801 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14613.989982 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999549 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149691133 # number of overall hits -system.cpu.dcache.overall_miss_latency 30289949388 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.013657 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2072668 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1597722 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4509676994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003130 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 474946 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149582203 # number of overall hits +system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2073649 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 470850 # number of replacements -system.cpu.dcache.sampled_refs 474946 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 471038 # number of replacements +system.cpu.dcache.sampled_refs 475134 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.156298 # Cycle average of tags in use -system.cpu.dcache.total_refs 149691136 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126698000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 423042 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 45000094 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 877 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4176202 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 688674202 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 142513181 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122905016 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9698747 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3338 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5375791 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163053496 # DTB accesses +system.cpu.dcache.tagsinuse 4094.151824 # Cycle average of tags in use +system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 423176 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 44833716 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 844 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4163323 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 687863087 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 142213399 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 122593858 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9601978 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3402 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5374385 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163150258 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163001268 # DTB hits -system.cpu.dtb.data_misses 52228 # DTB misses +system.cpu.dtb.data_hits 163097305 # DTB hits +system.cpu.dtb.data_misses 52953 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122206073 # DTB read accesses +system.cpu.dtb.read_accesses 122245622 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122181392 # DTB read hits -system.cpu.dtb.read_misses 24681 # DTB read misses -system.cpu.dtb.write_accesses 40847423 # DTB write accesses +system.cpu.dtb.read_hits 122220880 # DTB read hits +system.cpu.dtb.read_misses 24742 # DTB read misses +system.cpu.dtb.write_accesses 40904636 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40819876 # DTB write hits -system.cpu.dtb.write_misses 27547 # DTB write misses -system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched -system.cpu.fetch.Cycles 130078631 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed +system.cpu.dtb.write_hits 40876425 # DTB write hits +system.cpu.dtb.write_misses 28211 # DTB write misses +system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched +system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 65602641 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.143680 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 325492829 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.144120 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.095910 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 195414198 60.04% 60.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10425646 3.20% 63.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15856104 4.87% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13952359 4.29% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12095872 3.72% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13761061 4.23% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5876732 1.81% 82.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3435361 1.06% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54675496 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 194873658 60.03% 60.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10240367 3.15% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15840170 4.88% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13915379 4.29% 72.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11968140 3.69% 76.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13832570 4.26% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5877215 1.81% 82.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3421155 1.05% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 54648682 16.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 265 # number of floating regfile reads -system.cpu.fp_regfile_writes 58 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65559135 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42777500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 253 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1180 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32318500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 72043.005495 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65560315 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36252.118644 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency -system.cpu.icache.demand_hits 65559135 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42777500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency +system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1180 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32318500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.378389 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 774.939822 # Average occupied blocks per context -system.cpu.icache.overall_accesses 65560315 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36252.118644 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.378270 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context +system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65559135 # number of overall hits -system.cpu.icache.overall_miss_latency 42777500 # number of overall miss cycles +system.cpu.icache.overall_hits 65446683 # number of overall hits +system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1180 # number of overall misses -system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32318500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1151 # number of overall misses +system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 774.939822 # Cycle average of tags in use -system.cpu.icache.total_refs 65559135 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use +system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 66731 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67424273 # Number of branches executed -system.cpu.iew.EXEC:nop 43222760 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.839913 # Inst execution rate -system.cpu.iew.EXEC:refs 163081324 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 40875188 # Number of stores executed +system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67449018 # Number of branches executed +system.cpu.iew.EXEC:nop 43212719 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.845435 # Inst execution rate +system.cpu.iew.EXEC:refs 163178153 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 40932468 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487722865 # num instructions consuming a value -system.cpu.iew.WB:count 595805949 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811742 # average fanout of values written-back +system.cpu.iew.WB:consumers 486897348 # num instructions consuming a value +system.cpu.iew.WB:count 595948678 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.812979 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395904949 # num instructions producing a value -system.cpu.iew.WB:rate 1.830098 # insts written-back per cycle -system.cpu.iew.WB:sent 596918670 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4602797 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1364972 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126095826 # Number of dispatched load instructions +system.cpu.iew.WB:producers 395837342 # num instructions producing a value +system.cpu.iew.WB:rate 1.835470 # insts written-back per cycle +system.cpu.iew.WB:sent 597097102 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3115345 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 42628898 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 662516409 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122206136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6268247 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599001166 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 43958 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 13859 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9698747 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 63343 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 729 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9862373 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10156 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 70243 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11581784 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3177577 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 844691087 # number of integer regfile reads -system.cpu.int_regfile_writes 489153092 # number of integer regfile writes -system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 24101 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6020 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11448147 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 844972523 # number of integer regfile reads +system.cpu.int_regfile_writes 489243634 # number of integer regfile writes +system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 439513912 72.61% 72.61% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124151932 20.51% 93.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 41596836 6.87% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605269413 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7095490 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011723 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 605609121 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 5929666 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5209273 73.42% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 47 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 73.42% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1541723 21.73% 95.15% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 344447 4.85% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 325492829 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.859548 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.691188 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 324617336 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.865609 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 87236535 26.80% 26.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 66508902 20.43% 47.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 78677146 24.17% 71.41% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 34244703 10.52% 81.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 30387182 9.34% 91.26% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 15745565 4.84% 96.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 11042338 3.39% 99.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1062135 0.33% 99.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 588323 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate -system.cpu.iq.fp_alu_accesses 1679 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 3330 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 1605 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 1800 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 612363224 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1543136462 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 595804344 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 671661588 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 324617336 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.865224 # Inst issue rate +system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 52323110 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12647 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28040159 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 65560352 # ITB accesses +system.cpu.itb.fetch_accesses 65447871 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 65560315 # ITB hits +system.cpu.itb.fetch_hits 65447834 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -399,106 +399,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 256917 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.809098 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.738523 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 197080 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2063108500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.232904 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876353000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232904 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 218939 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34396.642358 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.006381 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 186029 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1131993500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.150316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32910 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020835500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32910 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 423042 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 423042 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5257.142857 # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.281796 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 368000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 475856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34449.653358 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 383109 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3195102000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.194906 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 92747 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2897188500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.194906 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 92747 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052860 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.487907 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1732.123670 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15987.736166 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 475856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34449.653358 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.052925 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.487884 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 383109 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3195102000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.194906 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 92747 # number of overall misses +system.cpu.l2cache.overall_hits 383286 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 92757 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2897188500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.194906 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 92747 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 74441 # number of replacements -system.cpu.l2cache.sampled_refs 90342 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 74455 # number of replacements +system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17719.859836 # Cycle average of tags in use -system.cpu.l2cache.total_refs 477168 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use +system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 59318 # number of writebacks -system.cpu.memDep0.conflictingLoads 17165638 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit. +system.cpu.l2cache.writebacks 59322 # number of writebacks +system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 325559560 # number of cpu cycles simulated +system.cpu.numCycles 324684436 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 12564419 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 149957875 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 662477 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 118 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 894828905 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 679288968 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 518109497 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115552585 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 1958 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 894826947 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 958179178 # The number of ROB reads -system.cpu.rob.rob_writes 1334457472 # The number of ROB writes -system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31522766 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 149604933 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 101 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 894089158 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 678776451 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 517767610 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115293181 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9601978 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 37552130 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 53912721 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 1965 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 894087193 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 695 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 73444449 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 30 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 956313792 # The number of ROB reads +system.cpu.rob.rob_writes 1333072216 # The number of ROB writes +system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index d33b7fe91..4ad2150c8 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -496,7 +496,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 7c98f6fbe..0f161f8aa 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:13 -M5 executing on u200439-lin.austin.arm.com +M5 compiled Mar 18 2011 20:12:03 +M5 started Mar 18 2011 21:36:19 +M5 executing on zizzer command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 212151683000 because target called exit() +Exiting @ tick 196536810500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index c117cacbc..69e8f3745 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 130169 # Simulator instruction rate (inst/s) -host_mem_usage 255152 # Number of bytes of host memory used -host_seconds 4627.51 # Real time elapsed on the host -host_tick_rate 45845717 # Simulator tick rate (ticks/s) +host_inst_rate 157384 # Simulator instruction rate (inst/s) +host_mem_usage 221236 # Number of bytes of host memory used +host_seconds 3827.32 # Real time elapsed on the host +host_tick_rate 51350965 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 602359950 # Number of instructions simulated -sim_seconds 0.212152 # Number of seconds simulated -sim_ticks 212151683000 # Number of ticks simulated +sim_insts 602359870 # Number of instructions simulated +sim_seconds 0.196537 # Number of seconds simulated +sim_ticks 196536810500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 77353146 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 83702663 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1593 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3826409 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 84369915 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 91120892 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1482138 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 70826872 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7259535 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 75961485 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 82107435 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1596 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 3833895 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 81873360 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 88392158 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1389747 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 70826856 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 7927801 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 408127750 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.475910 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.811076 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 379302454 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.588073 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.904864 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 143768271 35.23% 35.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 130628056 32.01% 67.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 60243177 14.76% 81.99% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 18962619 4.65% 86.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 17622510 4.32% 90.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 14296756 3.50% 94.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 13120148 3.21% 97.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2226678 0.55% 98.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7259535 1.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 123535993 32.57% 32.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 123034003 32.44% 65.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 59238565 15.62% 80.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 18407109 4.85% 85.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 17194886 4.53% 90.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 14352047 3.78% 93.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 7619076 2.01% 95.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 7992974 2.11% 97.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7927801 2.09% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 408127750 # Number of insts commited each cycle -system.cpu.commit.COM:count 602360001 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 379302454 # Number of insts commited each cycle +system.cpu.commit.COM:count 602359921 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 997573 # Number of function calls committed. -system.cpu.commit.COM:int_insts 533522759 # Number of committed integer instructions. -system.cpu.commit.COM:loads 148952624 # Number of loads committed +system.cpu.commit.COM:int_insts 533522695 # Number of committed integer instructions. +system.cpu.commit.COM:loads 148952608 # Number of loads committed system.cpu.commit.COM:membars 1328 # Number of memory barriers committed -system.cpu.commit.COM:refs 219173667 # Number of memory references committed +system.cpu.commit.COM:refs 219173635 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3887306 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 602360001 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 6327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 105586113 # The number of squashed insts skipped by commit -system.cpu.committedInsts 602359950 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359950 # Number of Instructions Simulated -system.cpu.cpi 0.704402 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.704402 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1392 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10807.692308 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_hits 1379 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 140500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.009339 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 13 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 13 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 139573989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 13187.861272 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7875.361074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 139338017 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3111966000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001691 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 235972 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 40375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1540397000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001401 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 195597 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses 1357 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 1357 # number of StoreCondReq hits +system.cpu.commit.branchMispredicts 3894768 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 602359921 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 6311 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 86755718 # The number of squashed insts skipped by commit +system.cpu.committedInsts 602359870 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359870 # Number of Instructions Simulated +system.cpu.cpi 0.652556 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.652556 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1359 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency 10642.857143 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_hits 1345 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 149000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate 0.010302 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses 14 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.ReadReq_accesses 139417902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13041.209813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7899.689585 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 139176030 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3154303500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 241872 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 46005 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1547288500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195867 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 1341 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 1341 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19453.548688 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10358.949737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 68088613 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25852171016 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019144 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1328918 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1081042 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2567735025 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 247876 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4395.291476 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 17903.398328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10349.195917 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 67926226 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 26699427444 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.021483 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1491305 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1243450 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2565099954 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 247855 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4339.606397 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 467.742670 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 2182 # number of cycles access was blocked +system.cpu.dcache.avg_refs 466.744813 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 2251 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 9590526 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 9768454 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 208991520 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18508.736727 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency -system.cpu.dcache.demand_hits 207426630 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 28964137016 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.007488 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1564890 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1121417 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4108132025 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002122 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 443473 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 208835433 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 17224.859864 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9267.939056 # average overall mshr miss latency +system.cpu.dcache.demand_hits 207102256 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29853730944 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008299 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1733177 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1289455 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4112388454 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002125 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 443722 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.932917 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 208991520 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18508.736727 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9263.544849 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999720 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.852027 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 208835433 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 17224.859864 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9267.939056 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 207426630 # number of overall hits -system.cpu.dcache.overall_miss_latency 28964137016 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.007488 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1564890 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1121417 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4108132025 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002122 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 443473 # number of overall MSHR misses +system.cpu.dcache.overall_hits 207102256 # number of overall hits +system.cpu.dcache.overall_miss_latency 29853730944 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008299 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1733177 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1289455 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4112388454 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002125 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 443722 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 439373 # number of replacements -system.cpu.dcache.sampled_refs 443469 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 439626 # number of replacements +system.cpu.dcache.sampled_refs 443722 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.932917 # Cycle average of tags in use -system.cpu.dcache.total_refs 207429374 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 89412000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 394062 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 84592597 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 1269 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 6208796 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 740088879 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 168706146 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 141255851 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15304229 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 4703 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 13573155 # Number of cycles decode is unblocking +system.cpu.dcache.tagsinuse 4094.852027 # Cycle average of tags in use +system.cpu.dcache.total_refs 207104942 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 89209000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 394231 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 63976815 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 1279 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 5983185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 722294449 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 163843845 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 138493802 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 12857426 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 4707 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 12987991 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 91120892 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 73409824 # Number of cache lines fetched -system.cpu.fetch.Cycles 157341177 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 853332 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 706778220 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2056 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4584124 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.214754 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 73409824 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 78835284 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.665738 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 423431978 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.775923 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.853239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 88392158 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 71392458 # Number of cache lines fetched +system.cpu.fetch.Cycles 153990332 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 937286 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 689759462 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1876 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4453848 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.224874 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 71392458 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 77351232 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.754784 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 392159879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.871937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.898017 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 266090925 62.84% 62.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25382675 5.99% 68.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18707202 4.42% 73.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23120734 5.46% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11518747 2.72% 81.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12813304 3.03% 84.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4581816 1.08% 85.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7541689 1.78% 87.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53674886 12.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 238169672 60.73% 60.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25123756 6.41% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18408287 4.69% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22743537 5.80% 77.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11348841 2.89% 80.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12044698 3.07% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4472652 1.14% 84.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7314673 1.87% 86.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52533763 13.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 423431978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 392159879 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 73409824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35098.824786 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34224.447514 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 73408888 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32852500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 71392458 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35440.133038 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34413.407821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 71391556 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 31967000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 936 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 212 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 24778500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 186 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 24640000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 724 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 716 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 101956.788889 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 99708.877095 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 73409824 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35098.824786 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency -system.cpu.icache.demand_hits 73408888 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32852500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 71392458 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35440.133038 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34413.407821 # average overall mshr miss latency +system.cpu.icache.demand_hits 71391556 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 31967000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 936 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 212 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 24778500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 902 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 186 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 24640000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 724 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 716 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.307623 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 630.012478 # Average occupied blocks per context -system.cpu.icache.overall_accesses 73409824 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35098.824786 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34224.447514 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.304966 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 624.569528 # Average occupied blocks per context +system.cpu.icache.overall_accesses 71392458 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35440.133038 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34413.407821 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 73408888 # number of overall hits -system.cpu.icache.overall_miss_latency 32852500 # number of overall miss cycles +system.cpu.icache.overall_hits 71391556 # number of overall hits +system.cpu.icache.overall_miss_latency 31967000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 936 # number of overall misses -system.cpu.icache.overall_mshr_hits 212 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 24778500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 902 # number of overall misses +system.cpu.icache.overall_mshr_hits 186 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 24640000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 724 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 716 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 33 # number of replacements -system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 716 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 630.012478 # Cycle average of tags in use -system.cpu.icache.total_refs 73408888 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 624.569528 # Cycle average of tags in use +system.cpu.icache.total_refs 71391556 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 871389 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 73892971 # Number of branches executed -system.cpu.iew.EXEC:nop 61798 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.506493 # Inst execution rate -system.cpu.iew.EXEC:refs 238982736 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 73900874 # Number of stores executed +system.cpu.idleCycles 913743 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 73697015 # Number of branches executed +system.cpu.iew.EXEC:nop 61594 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.622192 # Inst execution rate +system.cpu.iew.EXEC:refs 239145114 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 73370419 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 738975685 # num instructions consuming a value -system.cpu.iew.WB:count 633750064 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.595052 # average fanout of values written-back +system.cpu.iew.WB:consumers 736423030 # num instructions consuming a value +system.cpu.iew.WB:count 631861927 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.594969 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 439728869 # num instructions producing a value -system.cpu.iew.WB:rate 1.493625 # insts written-back per cycle -system.cpu.iew.WB:sent 634774515 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4294677 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 946102 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 181732576 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5902 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2934920 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 84682953 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 707943366 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 165081862 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6085968 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 639209952 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 15519 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 438148553 # num instructions producing a value +system.cpu.iew.WB:rate 1.607490 # insts written-back per cycle +system.cpu.iew.WB:sent 632828783 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4309187 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 803250 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 176095139 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2962571 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 82148484 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 689113035 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 165774695 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6093175 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 637640921 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 25921 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15304229 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 50818 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 3894 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 12857426 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 66942 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8944 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 24296735 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 57403 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8942 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 25088282 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 91350 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 930118 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15159 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 32779951 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 14461910 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 930118 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 636408 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3658269 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 1727320002 # number of integer regfile reads -system.cpu.int_regfile_writes 496802288 # number of integer regfile writes -system.cpu.ipc 1.419645 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.419645 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 610036 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 15544 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 27142530 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 11927457 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 610036 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 629916 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3679271 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1724659056 # number of integer regfile reads +system.cpu.int_regfile_writes 495413856 # number of integer regfile writes +system.cpu.ipc 1.532435 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.532435 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 402470959 62.37% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6564 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 167645097 25.98% 88.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 75173297 11.65% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 400825580 62.27% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 168279108 26.14% 88.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 74622820 11.59% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 645295920 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7755028 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012018 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 643734096 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 3962863 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006156 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 198697 2.56% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 7348141 94.75% 97.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 208190 2.68% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 103447 2.61% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3410396 86.06% 88.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 449020 11.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 423431978 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.523966 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.473546 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 392159879 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641509 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.552773 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 124767045 29.47% 29.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 123576315 29.18% 58.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 78343969 18.50% 77.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 46750040 11.04% 88.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 32770284 7.74% 95.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 12193598 2.88% 98.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 3344839 0.79% 99.60% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 823717 0.19% 99.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 862171 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 108979156 27.79% 27.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 107509921 27.41% 55.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 76161777 19.42% 74.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 48539013 12.38% 87.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 26829140 6.84% 93.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 16734433 4.27% 98.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5468015 1.39% 99.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1020625 0.26% 99.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 917799 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 423431978 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.520836 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 392159879 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.637693 # Inst issue rate system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 653050928 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1722505687 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 633750048 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 814020305 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 707874308 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 645295920 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7260 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 105229644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 726877 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 933 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 212022368 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.int_alu_accesses 647696939 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 1683941472 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 631861911 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 776045363 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 689044280 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 643734096 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7161 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 86384301 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 350574 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 162192952 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -415,114 +415,106 @@ system.cpu.itb.read_misses 0 # DT system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 247874 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.539920 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.130694 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 189432 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2008274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235773 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58442 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1826963000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235773 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58442 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 196316 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34255.152982 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31104.089447 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 163665 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1118465000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.166319 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32651 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_accesses 247857 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.314168 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31234.317248 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 189417 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2006322000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235781 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58440 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825333500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58440 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 196581 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34342.701958 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31091.800820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 163901 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1122319500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.166242 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32680 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 1015393000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166288 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32645 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_rate 0.333333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.333333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 394062 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 394062 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5824.362606 # average number of cycles each access was blocked +system.cpu.l2cache.ReadReq_mshr_miss_latency 1015893500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32674 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 394231 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 394231 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5401.428571 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.737794 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 4.739445 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 350 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 2056000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 1890500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 444190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34324.690152 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 353097 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3126739000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.205077 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91093 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 444438 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34335.398376 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31183.210045 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 353318 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3128641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.205023 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91120 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2842356000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.205063 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91087 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2841227000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.205009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91114 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.056232 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.489259 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1842.604757 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16032.025879 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 444190 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34324.690152 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.848112 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.057195 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.487171 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1874.172488 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15963.624075 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 444438 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34335.398376 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31183.210045 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 353097 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3126739000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.205077 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91093 # number of overall misses +system.cpu.l2cache.overall_hits 353318 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3128641500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.205023 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91120 # number of overall misses system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2842356000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.205063 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91087 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2841227000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.205009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91114 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72891 # number of replacements -system.cpu.l2cache.sampled_refs 88396 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 72928 # number of replacements +system.cpu.l2cache.sampled_refs 88438 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17874.630636 # Cycle average of tags in use -system.cpu.l2cache.total_refs 418802 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17837.796563 # Cycle average of tags in use +system.cpu.l2cache.total_refs 419147 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58120 # number of writebacks -system.cpu.memDep0.conflictingLoads 59394757 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28028248 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 181732576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84682953 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 939363465 # number of misc regfile reads +system.cpu.l2cache.writebacks 58125 # number of writebacks +system.cpu.memDep0.conflictingLoads 25818022 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23076545 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 176095139 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 82148484 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 922030590 # number of misc regfile reads system.cpu.misc_regfile_writes 9368 # number of misc regfile writes -system.cpu.numCycles 424303367 # number of cpu cycles simulated +system.cpu.numCycles 393073622 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 12681660 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 471025546 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 63633162 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 186161185 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2954668 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 2083466922 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 728669573 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 566468470 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 137330990 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15304229 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 71846492 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 95442921 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:BlockCycles 9403650 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 471025466 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 50023577 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 176787767 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1922723 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 2034086698 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 711204835 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 553151366 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 138512795 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 12857426 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 54492155 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 82125897 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2083466826 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 107422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 6263 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 128424972 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6268 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 1108813717 # The number of ROB reads -system.cpu.rob.rob_writes 1431196844 # The number of ROB writes -system.cpu.timesIdled 36620 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 2034086602 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 106086 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 6114 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 91032587 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 6112 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 1060489680 # The number of ROB reads +system.cpu.rob.rob_writes 1391088840 # The number of ROB writes +system.cpu.timesIdled 36977 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 239140dc5..2c96b363d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 44a2a20b1..bc6585d4f 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:13:30 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:13:36 -M5 executing on burrito +M5 compiled Mar 17 2011 23:04:27 +M5 started Mar 17 2011 23:11:57 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +42,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 601458924000 because target called exit() +Exiting @ tick 582418059000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 2fc2b1f97..0f4eafb7d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165526 # Simulator instruction rate (inst/s) -host_mem_usage 228372 # Number of bytes of host memory used -host_seconds 8491.76 # Real time elapsed on the host -host_tick_rate 70828550 # Simulator tick rate (ticks/s) +host_inst_rate 165963 # Simulator instruction rate (inst/s) +host_mem_usage 210376 # Number of bytes of host memory used +host_seconds 8469.40 # Real time elapsed on the host +host_tick_rate 68767363 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated -sim_seconds 0.601459 # Number of seconds simulated -sim_ticks 601458924000 # Number of ticks simulated +sim_seconds 0.582418 # Number of seconds simulated +sim_ticks 582418059000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 98804590 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 100538418 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 97659749 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 99018650 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5348296 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 105813144 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 105813144 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 5339067 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 103713551 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 103713551 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 21328117 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 26710610 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1172142071 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1136580592 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.310530 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.747403 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 418029830 35.66% 35.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 498322942 42.51% 78.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 52997650 4.52% 82.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 103674512 8.84% 91.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 32914783 2.81% 94.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 8294110 0.71% 95.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 25633990 2.19% 97.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 10946137 0.93% 98.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 21328117 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 402922453 35.45% 35.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 477569543 42.02% 77.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 55697713 4.90% 82.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 97088718 8.54% 90.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 32658945 2.87% 93.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8438570 0.74% 94.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 25679618 2.26% 96.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 9814422 0.86% 97.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 26710610 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1136580592 # Number of insts commited each cycle system.cpu.commit.COM:count 1489523295 # Number of instructions committed system.cpu.commit.COM:fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,435 +44,434 @@ system.cpu.commit.COM:loads 402512844 # Nu system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569360986 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5348296 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5339067 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 219357232 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 199490556 # The number of squashed insts skipped by commit system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.855801 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.855801 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 295701881 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14657.940821 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.771391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 294883584 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11994549000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 818297 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 604806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1593875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses +system.cpu.cpi 0.828709 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.828709 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 291461478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14664.632652 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7474.067095 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 290645276 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11969302500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002800 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 816202 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 602863 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1594510000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000732 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 213339 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15553.543798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12825.966833 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 165080859 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 27466889545 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010584 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1765957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1497892 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3438192799 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 15381.021476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13048.542893 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 165025455 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28014392657 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010916 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1821361 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1553325 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3497479243 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001606 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 268036 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 955.151791 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 946.591376 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 462548697 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15269.953551 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency -system.cpu.dcache.demand_hits 459964443 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 39461438545 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005587 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2584254 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2102698 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5032067799 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 458308294 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 15159.332747 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency +system.cpu.dcache.demand_hits 455670731 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 39983695157 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005755 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2637563 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2156188 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5091989243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.001050 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 481375 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.424247 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 462548697 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15269.953551 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999855 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.405595 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 458308294 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 15159.332747 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10578.009334 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 459964443 # number of overall hits -system.cpu.dcache.overall_miss_latency 39461438545 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005587 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2584254 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2102698 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5032067799 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses +system.cpu.dcache.overall_hits 455670731 # number of overall hits +system.cpu.dcache.overall_miss_latency 39983695157 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005755 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2637563 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2156188 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5091989243 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.001050 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 481375 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 477467 # number of replacements -system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 477286 # number of replacements +system.cpu.dcache.sampled_refs 481382 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.424247 # Cycle average of tags in use -system.cpu.dcache.total_refs 459965762 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 132304000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 428418 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 393633604 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1750740297 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 405697462 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 351107020 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 30410517 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 21703374 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 105813144 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 173097327 # Number of cache lines fetched -system.cpu.fetch.Cycles 375137003 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1429156 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1755978912 # Number of instructions fetch has processed +system.cpu.dcache.tagsinuse 4095.405595 # Cycle average of tags in use +system.cpu.dcache.total_refs 455672050 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 132278000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 428224 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 373408138 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1727466392 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 394807577 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 348667632 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 27885594 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 19696634 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 103713551 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 170870865 # Number of cache lines fetched +system.cpu.fetch.Cycles 370648133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1257771 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1732289789 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 6170643 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 173097327 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 98804590 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1202551977 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 5787763 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089037 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 170870865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 97659749 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.487153 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1164465575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.491538 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.715145 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 827414974 68.80% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82887161 6.89% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45821959 3.81% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22740624 1.89% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 32823900 2.73% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14990247 1.25% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7935660 0.66% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 134105255 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 793817442 68.17% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 81924135 7.04% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44978693 3.86% 79.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22977276 1.97% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 33360505 2.86% 83.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 33148842 2.85% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14858388 1.28% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7508131 0.64% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 131892163 11.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 16952700 # number of floating regfile reads -system.cpu.fp_regfile_writes 10422320 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 173095532 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 62951000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1164465575 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 16956220 # number of floating regfile reads +system.cpu.fp_regfile_writes 10464632 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 170870865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35272.495756 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.283732 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 170869098 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 62326500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45401500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_misses 1767 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 470 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 45468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1297 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 133767.799073 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 131843.439815 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 173097327 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35070.194986 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency -system.cpu.icache.demand_hits 173095532 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 62951000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 170870865 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35272.495756 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency +system.cpu.icache.demand_hits 170869098 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 62326500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses -system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45401500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_misses 1767 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 470 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 45468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000008 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1297 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.509893 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1044.260820 # Average occupied blocks per context -system.cpu.icache.overall_accesses 173097327 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35070.194986 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.511535 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1047.623620 # Average occupied blocks per context +system.cpu.icache.overall_accesses 170870865 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35272.495756 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35056.283732 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 173095532 # number of overall hits -system.cpu.icache.overall_miss_latency 62951000 # number of overall miss cycles +system.cpu.icache.overall_hits 170869098 # number of overall hits +system.cpu.icache.overall_miss_latency 62326500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.overall_misses 1795 # number of overall misses -system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45401500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses +system.cpu.icache.overall_misses 1767 # number of overall misses +system.cpu.icache.overall_mshr_hits 470 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 45468000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000008 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1297 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 158 # number of replacements -system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks. +system.cpu.icache.replacements 159 # number of replacements +system.cpu.icache.sampled_refs 1296 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1044.260820 # Cycle average of tags in use -system.cpu.icache.total_refs 173095532 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1047.623620 # Cycle average of tags in use +system.cpu.icache.total_refs 170869098 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 365872 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 89387996 # Number of branches executed -system.cpu.iew.EXEC:nop 102270134 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate -system.cpu.iew.EXEC:refs 590482875 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 169844843 # Number of stores executed +system.cpu.idleCycles 370544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 89603944 # Number of branches executed +system.cpu.iew.EXEC:nop 100373819 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate +system.cpu.iew.EXEC:refs 591399205 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 170154785 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1212153101 # num instructions consuming a value -system.cpu.iew.WB:count 1472498717 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.958322 # average fanout of values written-back +system.cpu.iew.WB:consumers 1209973999 # num instructions consuming a value +system.cpu.iew.WB:count 1473173854 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.961076 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1161632680 # num instructions producing a value -system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle -system.cpu.iew.WB:sent 1473870381 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5524543 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2523096 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 468104279 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4542154 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 188276128 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1708972338 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 420638032 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6157621 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1475771230 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 66958 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1162877329 # num instructions producing a value +system.cpu.iew.WB:rate 1.264705 # insts written-back per cycle +system.cpu.iew.WB:sent 1474297623 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 5675287 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2507924 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 461157302 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 2999936 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 4553877 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 187022162 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1689106884 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 421244420 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6318503 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1475928628 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 66196 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9816 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 30410517 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 130917 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 8462 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 27885594 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 128708 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 124904328 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 7473 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 40205 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 129748862 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 35905 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 65591435 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 21427986 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 1994642284 # number of integer regfile reads -system.cpu.int_regfile_writes 1296237136 # number of integer regfile writes -system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 460365 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 237 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 58644458 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 20174020 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 460365 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 670427 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5004860 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 1997794756 # number of integer regfile reads +system.cpu.int_regfile_writes 1296594839 # number of integer regfile writes +system.cpu.ipc 1.206697 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206697 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685423 59.70% 59.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618241 0.18% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 423844959 28.60% 88.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780228 11.52% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 883945189 59.64% 59.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2631981 0.18% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 424001958 28.61% 88.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 171668003 11.58% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1481928851 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3245613 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1482247131 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 3391020 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002288 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 176489 5.44% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 2530154 77.96% 89.96% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 325770 10.04% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 214212 6.32% 6.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 187778 5.54% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 2748667 81.06% 92.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 240363 7.09% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1202551977 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127764 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1164465575 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.272899 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.148641 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 320557298 26.66% 26.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 511598029 42.54% 69.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 219313490 18.24% 87.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 94900060 7.89% 95.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 39948235 3.32% 98.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 10701841 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5167806 0.43% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 227063 0.02% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 138155 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 309298241 26.56% 26.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 465738905 40.00% 66.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 229121985 19.68% 86.23% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 104115000 8.94% 95.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 41467759 3.56% 98.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 8912842 0.77% 99.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5349281 0.46% 99.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 304172 0.03% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 157390 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate -system.cpu.iq.fp_alu_accesses 9139758 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 17716192 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 8503894 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 9202883 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1476034706 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4152007639 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1463994823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 1798910142 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 200593512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 68539 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 832248 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 279087097 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.350752 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31318.935009 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2080612500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893856000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34037.381235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958432 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1146379000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044247000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1164465575 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.272494 # Inst issue rate +system.cpu.iq.fp_alu_accesses 9142959 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 17762219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 8523024 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9165283 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1476495192 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4114870575 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1464650830 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1762732094 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1585633508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1482247131 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3099557 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 182705519 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 281937 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 855886 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 240684944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 268051 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.834444 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.706026 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 207600 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2079988000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.225521 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 60451 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893368000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225521 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 60451 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 214628 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34037.437678 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.970916 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 180932 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1146925500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.156997 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33696 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1044743500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156997 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33696 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 428224 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 428224 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.114449 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.108819 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34275.002655 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3226991500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 482679 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34275.266339 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 388532 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3226913500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.195051 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 94147 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2938103000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2938111500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.195051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 94147 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.060606 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1985.934249 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15675.618246 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34275.002655 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.059800 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.479227 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1959.521413 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15703.307498 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 482679 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34275.266339 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.701786 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 388708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3226991500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 94150 # number of overall misses +system.cpu.l2cache.overall_hits 388532 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3226913500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.195051 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 94147 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2938103000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2938111500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.195051 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 94147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 75917 # number of replacements -system.cpu.l2cache.sampled_refs 91429 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 75916 # number of replacements +system.cpu.l2cache.sampled_refs 91427 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17661.552495 # Cycle average of tags in use -system.cpu.l2cache.total_refs 467609 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17662.828910 # Cycle average of tags in use +system.cpu.l2cache.total_refs 467084 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 59275 # number of writebacks -system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 596285867 # number of misc regfile reads +system.cpu.l2cache.writebacks 59282 # number of writebacks +system.cpu.memDep0.conflictingLoads 386274637 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 159916794 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 461157302 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 187022162 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 597198570 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.numCycles 1202917849 # number of cpu cycles simulated +system.cpu.numCycles 1164836119 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 115497905 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 134234465 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 443700933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 41034559 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2924501033 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1732030714 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1445194568 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 329588798 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 33734828 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 2890766205 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 2859629611 # The number of ROB reads -system.cpu.rob.rob_writes 3448202738 # The number of ROB writes -system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:FullRegisterEvents 28107626 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 128337052 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 433132347 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 40459205 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 2887426636 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1709740875 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1426816340 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 325737783 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 27885594 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 209164686 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 182045888 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 33660518 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 2853766118 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 53047260 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 3085415 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 378977297 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 3085429 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 2798818963 # The number of ROB reads +system.cpu.rob.rob_writes 3405946340 # The number of ROB writes +system.cpu.timesIdled 11499 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 503c61f1c..2af9a6819 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -115,6 +115,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -413,6 +414,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=true latency=1000 max_miss_count=0 mshrs=10 @@ -448,6 +450,7 @@ assoc=2 block_size=64 forward_snoops=true hash_delay=1 +is_top_level=false latency=1000 max_miss_count=0 mshrs=10 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index e2d377ea1..f0ec00748 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 16 2011 15:39:14 -M5 started Mar 16 2011 15:39:15 -M5 executing on burrito +M5 compiled Mar 18 2011 20:12:06 +M5 started Mar 18 2011 20:12:27 +M5 executing on zizzer command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1066,4 +1066,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 766217705000 because target called exit() +Exiting @ tick 751079230500 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 7b745cca5..3726448fa 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 213906 # Simulator instruction rate (inst/s) -host_mem_usage 226116 # Number of bytes of host memory used -host_seconds 7580.41 # Real time elapsed on the host -host_tick_rate 101078599 # Simulator tick rate (ticks/s) +host_inst_rate 151077 # Simulator instruction rate (inst/s) +host_mem_usage 216016 # Number of bytes of host memory used +host_seconds 10732.89 # Real time elapsed on the host +host_tick_rate 69979188 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.766218 # Number of seconds simulated -sim_ticks 766217705000 # Number of ticks simulated +sim_seconds 0.751079 # Number of seconds simulated +sim_ticks 751079230500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 168460210 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 169652659 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 8971423 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 179993455 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 179993455 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 11445860 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1402522347 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.156127 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.381739 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 522037324 37.22% 37.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 531767209 37.92% 75.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 125147036 8.92% 84.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 139348503 9.94% 93.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 42559094 3.03% 97.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 23457685 1.67% 98.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 5021941 0.36% 99.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1737695 0.12% 99.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 11445860 0.82% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1402522347 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 8971450 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 721713449 # The number of squashed insts skipped by commit system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses +system.cpu.cpi 0.926404 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926404 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 325401931 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10107.251018 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7152.951878 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 325183672 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2205998500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 218259 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3345 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1537269500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 214914 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 19574.534314 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10012.304968 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 186952974 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 24137025496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006552 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1233083 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 982981 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2504097497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 250102 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15974.978853 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1101.331236 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 472140500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency -system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 513587988 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18150.803874 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency +system.cpu.dcache.demand_hits 512136646 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26343023996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002826 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1451342 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 986326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4041366997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 465016 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999792 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.146726 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 513587988 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18150.803874 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8690.812783 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 517710070 # number of overall hits -system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1455125 # number of overall misses -system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses +system.cpu.dcache.overall_hits 512136646 # number of overall hits +system.cpu.dcache.overall_miss_latency 26343023996 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002826 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1451342 # number of overall misses +system.cpu.dcache.overall_mshr_hits 986326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4041366997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 465016 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 460779 # number of replacements -system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 460920 # number of replacements +system.cpu.dcache.sampled_refs 465016 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use -system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 411288 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched -system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.146726 # Cycle average of tags in use +system.cpu.dcache.total_refs 512136646 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317706000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 411408 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 587921420 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2472731706 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 429893143 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 331529130 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 99378480 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 53178654 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 179993455 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 170058043 # Number of cache lines fetched +system.cpu.fetch.Cycles 400227143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 625222 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1408639601 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 15384200 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.119823 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 170058043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 168460210 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.937744 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1501900827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.699260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.059388 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1104715792 73.55% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26107791 1.74% 75.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14369087 0.96% 76.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13756932 0.92% 77.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30207594 2.01% 79.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20132707 1.34% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34410865 2.29% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37556252 2.50% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220643807 14.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1501900827 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 170058043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35240.756303 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35321.058688 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 170056853 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 41936500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 321 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 30694000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 869 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 195692.581128 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency -system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 170058043 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35240.756303 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency +system.cpu.icache.demand_hits 170056853 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 41936500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 30694000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 869 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context -system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.387535 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 793.670730 # Average occupied blocks per context +system.cpu.icache.overall_accesses 170058043 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35240.756303 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35321.058688 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 168862206 # number of overall hits -system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles +system.cpu.icache.overall_hits 170056853 # number of overall hits +system.cpu.icache.overall_miss_latency 41936500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1223 # number of overall misses -system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1190 # number of overall misses +system.cpu.icache.overall_mshr_hits 321 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 30694000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 869 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 11 # number of replacements -system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 869 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use -system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 793.670730 # Cycle average of tags in use +system.cpu.icache.total_refs 170056853 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 111314295 # Number of branches executed +system.cpu.idleCycles 257635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 111429178 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate -system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 191312994 # Number of stores executed +system.cpu.iew.EXEC:rate 1.227514 # Inst execution rate +system.cpu.iew.EXEC:refs 636597814 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 191695864 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2089450314 # num instructions consuming a value -system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back +system.cpu.iew.WB:consumers 2082700302 # num instructions consuming a value +system.cpu.iew.WB:count 1838995466 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.683970 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1430463260 # num instructions producing a value -system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle -system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1424504384 # num instructions producing a value +system.cpu.iew.WB:rate 1.224235 # insts written-back per cycle +system.cpu.iew.WB:sent 1842743630 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 9107858 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1395305 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 615851374 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 312936 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 250798855 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2343198083 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 444901950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13067063 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1843921293 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 56293 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 99378480 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 111986 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 30239 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 119484333 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 15966 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads -system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes -system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6399400 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 47 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 196809249 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 62612798 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6399400 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 4677718 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4430140 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3236941415 # number of integer regfile reads +system.cpu.int_regfile_writes 1831971139 # number of integer regfile writes +system.cpu.ipc 1.079443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079443 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 28079218 1.51% 1.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1185434411 63.84% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 451340139 24.30% 89.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 192134588 10.35% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1856988356 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4273878 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002302 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 161807 3.79% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3493887 81.75% 85.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 618184 14.46% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1501900827 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.236425 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.221094 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 463034659 30.83% 30.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 580779168 38.67% 69.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 218589752 14.55% 84.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 151066938 10.06% 94.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 63504112 4.23% 98.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 18859628 1.26% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5092601 0.34% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 833076 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 140893 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate -system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads +system.cpu.iq.ISSUE:issued_per_cycle::total 1501900827 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.236213 # Inst issue rate +system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 2351086127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 79 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1543114167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.iq.int_alu_accesses 1833182997 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5220358647 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1838995454 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3071160852 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2343198002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1856988356 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 721564206 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 207265 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1518322063 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 250113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.651379 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.730459 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 191287 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2024064500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235198 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58826 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235198 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 215772 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34136.783762 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.222249 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 182665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1130166500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.153435 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33107 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026523000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153435 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33107 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 411408 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 411408 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 5.099879 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 465885 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34310.106273 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 373952 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3154231000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.197330 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91933 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2859290000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.197330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91933 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.058491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491164 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1916.626475 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16094.448281 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 465885 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34310.106273 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.889419 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 373812 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91930 # number of overall misses +system.cpu.l2cache.overall_hits 373952 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3154231000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.197330 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91933 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2859290000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.197330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91933 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 73661 # number of replacements -system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 73660 # number of replacements +system.cpu.l2cache.sampled_refs 89268 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use -system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18011.074755 # Cycle average of tags in use +system.cpu.l2cache.total_refs 455256 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58542 # number of writebacks -system.cpu.memDep0.conflictingLoads 537232403 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads -system.cpu.numCycles 1532435411 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58532 # number of writebacks +system.cpu.memDep0.conflictingLoads 528261825 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 206728085 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 615851374 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250798855 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 931071836 # number of misc regfile reads +system.cpu.numCycles 1502158462 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 169288978 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3775835718 # The number of ROB reads -system.cpu.rob.rob_writes 4802062478 # The number of ROB writes -system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 298516669 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 493321936 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 107168100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5808956116 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2397077126 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2395694665 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 310095488 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 99378480 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 429812969 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 777700015 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 64 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5808956052 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 2976 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 89 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 706930007 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 89 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3734283918 # The number of ROB reads +system.cpu.rob.rob_writes 4785794667 # The number of ROB writes +system.cpu.timesIdled 45615 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- |