diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:27:53 -0700 |
| commit | a51e2fd8bd581d45f8a87874c9a6680f99d11e24 (patch) | |
| tree | 8de4626b115b234de0962cc04d32e15b6eb0fa3a /tests/long/00.gzip | |
| parent | e7e2d5ce9072808d94d5fe399e6c4262d92b7923 (diff) | |
| download | gem5-a51e2fd8bd581d45f8a87874c9a6680f99d11e24.tar.xz | |
Stats: Update the stats.
--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
Diffstat (limited to 'tests/long/00.gzip')
15 files changed, 825 insertions, 678 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 4de44cbb3..7a9d0390d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -21,6 +21,7 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +cachePorts=200 choiceCtrBits=2 choicePredictorSize=8192 clock=500 @@ -35,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -52,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -74,8 +77,18 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 squashWidth=8 system=system +tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 @@ -85,21 +98,21 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -107,12 +120,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=262144 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -121,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -128,11 +143,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu.fuPool.FUList0] type=FUDesc -children=opList0 +children=opList count=6 -opList=system.cpu.fuPool.FUList0.opList0 +opList=system.cpu.fuPool.FUList0.opList -[system.cpu.fuPool.FUList0.opList0] +[system.cpu.fuPool.FUList0.opList] type=OpDesc issueLat=1 opClass=IntAlu @@ -206,11 +221,11 @@ opLat=24 [system.cpu.fuPool.FUList4] type=FUDesc -children=opList0 +children=opList count=0 -opList=system.cpu.fuPool.FUList4.opList0 +opList=system.cpu.fuPool.FUList4.opList -[system.cpu.fuPool.FUList4.opList0] +[system.cpu.fuPool.FUList4.opList] type=OpDesc issueLat=1 opClass=MemRead @@ -218,11 +233,11 @@ opLat=1 [system.cpu.fuPool.FUList5] type=FUDesc -children=opList0 +children=opList count=0 -opList=system.cpu.fuPool.FUList5.opList0 +opList=system.cpu.fuPool.FUList5.opList -[system.cpu.fuPool.FUList5.opList0] +[system.cpu.fuPool.FUList5.opList] type=OpDesc issueLat=1 opClass=MemWrite @@ -248,11 +263,11 @@ opLat=1 [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 +children=opList count=1 -opList=system.cpu.fuPool.FUList7.opList0 +opList=system.cpu.fuPool.FUList7.opList -[system.cpu.fuPool.FUList7.opList0] +[system.cpu.fuPool.FUList7.opList] type=OpDesc issueLat=3 opClass=IprAccess @@ -260,21 +275,21 @@ opLat=3 [system.cpu.icache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -282,12 +297,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=131072 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=20 trace_addr=0 @@ -296,23 +309,27 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache -adaptive_compression=false +addr_range=0:18446744073709551615 assoc=2 block_size=64 -compressed_bus=false -compression_latency=0 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=10 prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -320,12 +337,10 @@ prefetch_serial_squash=false prefetch_use_cpu_id=true prefetcher_size=100 prioritizeRequests=false -protocol=Null repl=Null size=2097152 split=false split_size=0 -store_compressed=false subblock_size=0 tgts_per_mshr=5 trace_addr=0 @@ -343,6 +358,9 @@ responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 @@ -366,7 +384,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 21eca8681..0a81b23fb 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65796417 # Number of BTB hits -global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups -global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted -global.BPredUnit.lookups 75959317 # Number of BP lookups -global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target. -host_inst_rate 95235 # Simulator instruction rate (inst/s) -host_mem_usage 154544 # Number of bytes of host memory used -host_seconds 5938.47 # Real time elapsed on the host -host_tick_rate 31305923 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65676436 # Number of BTB hits +global.BPredUnit.BTBLookups 73156986 # Number of BTB lookups +global.BPredUnit.RASInCorrect 166 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4207318 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70088985 # Number of conditional branches predicted +global.BPredUnit.lookups 76017379 # Number of BP lookups +global.BPredUnit.usedRAS 1692882 # Number of times the RAS was used to get a target. +host_inst_rate 211348 # Simulator instruction rate (inst/s) +host_mem_usage 182448 # Number of bytes of host memory used +host_seconds 2675.93 # Real time elapsed on the host +host_tick_rate 60738573 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 16721732 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 11866335 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 126743752 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 43041597 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.185909 # Number of seconds simulated -sim_ticks 185909249000 # Number of ticks simulated +sim_seconds 0.162532 # Number of seconds simulated +sim_ticks 162531946000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 20242536 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 363164843 +system.cpu.commit.COM:committed_per_cycle.samples 315316083 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 150226418 4136.59% - 1 99566964 2741.65% - 2 34056070 937.76% - 3 10333475 284.54% - 4 20301573 559.02% - 5 15829471 435.88% - 6 8882909 244.60% - 7 2217371 61.06% - 8 21750592 598.92% + 0 101801168 3228.54% + 1 100686280 3193.19% + 2 36605446 1160.91% + 3 9846862 312.29% + 4 9756830 309.43% + 5 22230548 705.02% + 6 12726034 403.60% + 7 1420379 45.05% + 8 20242536 641.98% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4206693 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60367294 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.cpi 0.574772 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.574772 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 111194484 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 32074.811872 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5025.209404 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 110978275 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 6934863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.001944 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 216209 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 901354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1086495500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 216209 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 37821041 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 31690.076841 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5379.514968 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37483812 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10686812923 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.008916 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 337229 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1630280 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1814128453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 337229 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 1750 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 314.126008 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 7000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 149015525 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 31840.379452 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency +system.cpu.dcache.demand_hits 148462087 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17621675923 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003714 # miss rate for demand accesses +system.cpu.dcache.demand_misses 553438 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2531634 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 2900623953 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003714 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 553438 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 149015525 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 31840.379452 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5241.100093 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153786992 # number of overall hits -system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1255876 # number of overall misses -system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses +system.cpu.dcache.overall_hits 148462087 # number of overall hits +system.cpu.dcache.overall_miss_latency 17621675923 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003714 # miss rate for overall accesses +system.cpu.dcache.overall_misses 553438 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2531634 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 2900623953 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003714 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 553438 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 476596 # number of replacements -system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 468780 # number of replacements +system.cpu.dcache.sampled_refs 472876 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use -system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338024 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched -system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.312024 # Cycle average of tags in use +system.cpu.dcache.total_refs 148542650 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 41060000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 334093 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 42961711 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4159669 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 688665550 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 143212697 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123677184 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9747531 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1998 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5464492 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 162979892 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 162933690 # DTB hits +system.cpu.dtb.misses 46202 # DTB misses +system.cpu.dtb.read_accesses 122208199 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 122186821 # DTB read hits +system.cpu.dtb.read_misses 21378 # DTB read misses +system.cpu.dtb.write_accesses 40771693 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 40746869 # DTB write hits +system.cpu.dtb.write_misses 24824 # DTB write misses +system.cpu.fetch.Branches 76017379 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65923007 # Number of cache lines fetched +system.cpu.fetch.Cycles 196871509 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1349795 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 697858274 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4233156 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.233854 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65923007 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67369318 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.146836 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 371818526 +system.cpu.fetch.rateDist.samples 325063615 system.cpu.fetch.rateDist.min_value 0 - 0 255080243 6860.34% - 1 9944321 267.45% - 2 12043396 323.91% - 3 10077209 271.02% - 4 7005486 188.41% - 5 3160802 85.01% - 6 3551742 95.52% - 7 3151910 84.77% - 8 67803417 1823.56% + 0 194115151 5971.61% + 1 10367448 318.94% + 2 15852914 487.69% + 3 14602370 449.22% + 4 12321515 379.05% + 5 14794025 455.11% + 6 6009823 184.88% + 7 3340187 102.75% + 8 53660182 1650.76% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_accesses 65922920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7890.798226 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5470.620843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65922018 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7117500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 87 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4934500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73084.277162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency -system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses -system.cpu.icache.demand_misses 967 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 65922920 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7890.798226 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency +system.cpu.icache.demand_hits 65922018 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses +system.cpu.icache.demand_misses 902 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4934500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65922920 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7890.798226 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5470.620843 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65389966 # number of overall hits -system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses -system.cpu.icache.overall_misses 967 # number of overall misses -system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 65922018 # number of overall hits +system.cpu.icache.overall_miss_latency 7117500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses +system.cpu.icache.overall_misses 902 # number of overall misses +system.cpu.icache.overall_mshr_hits 87 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4934500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,81 +229,81 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 33 # number of replacements -system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks. +system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use -system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 770.534444 # Cycle average of tags in use +system.cpu.icache.total_refs 65922018 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67136036 # Number of branches executed -system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate -system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41112797 # Number of stores executed +system.cpu.idleCycles 190397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67319692 # Number of branches executed +system.cpu.iew.EXEC:nop 42991424 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.842347 # Inst execution rate +system.cpu.iew.EXEC:refs 163918711 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41167815 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value -system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back +system.cpu.iew.WB:consumers 490977460 # num instructions consuming a value +system.cpu.iew.WB:count 595732364 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.805927 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 389064913 # num instructions producing a value -system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle -system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions +system.cpu.iew.WB:producers 395691865 # num instructions producing a value +system.cpu.iew.WB:rate 1.832664 # insts written-back per cycle +system.cpu.iew.WB:sent 596897738 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4671822 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 211982 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126743752 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 3268805 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43041597 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 662373944 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122750896 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6416858 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598879902 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1310 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9747531 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 36871 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 10085062 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 15402 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 28955 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5897 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11694242 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3229074 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 28955 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 540642 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4131180 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.739821 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.739821 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 605296760 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 435905994 72.35% # Type of FU issued - IntMult 6492 0.00% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued + IntAlu 438526639 72.45% # Type of FU issued + IntMult 6526 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 27 0.00% # Type of FU issued + FloatAdd 29 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued FloatCvt 5 0.00% # Type of FU issued FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 124769613 20.71% # Type of FU issued - MemWrite 41794213 6.94% # Type of FU issued + MemRead 124781721 20.61% # Type of FU issued + MemWrite 41981831 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 6717566 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011098 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 2980889 85.52% # attempts to use FU when none available - IntMult 104 0.00% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 5391256 80.26% # attempts to use FU when none available + IntMult 67 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -297,80 +311,105 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 331227 9.50% # attempts to use FU when none available - MemWrite 173244 4.97% # attempts to use FU when none available + MemRead 838838 12.49% # attempts to use FU when none available + MemWrite 487405 7.26% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526 +system.cpu.iq.ISSUE:issued_per_cycle.samples 325063615 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 125625601 3378.68% - 1 89616652 2410.23% - 2 55904072 1503.53% - 3 46310572 1245.52% - 4 27240019 732.62% - 5 12675210 340.90% - 6 11517465 309.76% - 7 2752555 74.03% - 8 176380 4.74% + 0 85796359 2639.37% + 1 67542387 2077.82% + 2 80092036 2463.89% + 3 31532999 970.06% + 4 32045835 985.83% + 5 15660373 481.76% + 6 10783606 331.74% + 7 1095697 33.71% + 8 514323 15.82% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate -system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.862087 # Inst issue rate +system.cpu.iq.iqInstsAdded 619382498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605296760 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 52509739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 11652 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits +system.cpu.iq.iqSquashedOperandsExamined 28327252 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 65923045 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 65923007 # ITB hits +system.cpu.itb.misses 38 # ITB misses +system.cpu.l2cache.ReadExReq_accesses 256667 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4174.217956 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2174.217956 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1071384000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 256667 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 558050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 256667 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 217111 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4357.993028 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.993028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 30930 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 811375500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.857538 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 186181 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 439013500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.857538 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 186181 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 80592 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4188.374777 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2188.374777 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 337549500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 80592 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 176365500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 80592 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 334093 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 334093 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 334093 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.206809 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 473778 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4251.480192 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 30930 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1882759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.934716 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 442848 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 997063500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.934716 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 442848 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 473778 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4251.480192 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2251.480192 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 793309 # number of overall hits -system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26299 # number of overall misses +system.cpu.l2cache.overall_hits 30930 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1882759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.934716 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 442848 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 997063500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.934716 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 442848 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,31 +421,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 931 # number of replacements -system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 14218 # number of replacements +system.cpu.l2cache.sampled_refs 15715 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8150.643180 # Cycle average of tags in use +system.cpu.l2cache.total_refs 66110 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 904 # number of writebacks -system.cpu.numCycles 371818526 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 325063615 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 11040699 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31586100 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 150557156 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 290380 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 895272473 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 679363424 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518606333 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 116560800 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9747531 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 37157112 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54751444 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 317 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 72001269 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.timesIdled 103 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index e7acc71a6..e21c42f32 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + +[system.cpu.itb] +type=AlphaITB +size=48 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index 5453dc099..c668a0459 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 963880 # Simulator instruction rate (inst/s) -host_mem_usage 148548 # Number of bytes of host memory used -host_seconds 624.41 # Real time elapsed on the host -host_tick_rate 481939681 # Simulator tick rate (ticks/s) +host_inst_rate 2906348 # Simulator instruction rate (inst/s) +host_mem_usage 174252 # Number of bytes of host memory used +host_seconds 207.08 # Real time elapsed on the host +host_tick_rate 1453183573 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.300928 # Number of seconds simulated -sim_ticks 300928482000 # Number of ticks simulated +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.300931 # Number of seconds simulated +sim_ticks 300930958000 # Number of ticks simulated +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861917 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861897 # ITB hits +system.cpu.itb.misses 20 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 601856965 # number of cpu cycles simulated -system.cpu.num_insts 601856965 # Number of instructions executed -system.cpu.num_refs 154862034 # Number of memory references +system.cpu.numCycles 601861917 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 16b6c6fda..21fbe2323 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=AlphaDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=AlphaITB +size=48 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index eaccc0729..b76b4e6c1 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1799420 # Simulator instruction rate (inst/s) -host_mem_usage 199568 # Number of bytes of host memory used -host_seconds 334.47 # Real time elapsed on the host -host_tick_rate 2297009943 # Simulator tick rate (ticks/s) +host_inst_rate 1730291 # Simulator instruction rate (inst/s) +host_mem_usage 181616 # Number of bytes of host memory used +host_seconds 347.84 # Real time elapsed on the host +host_tick_rate 2208778962 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.768288 # Number of seconds simulated -sim_ticks 768287940000 # Number of ticks simulated +sim_insts 601856964 # Number of instructions simulated +sim_seconds 0.768293 # Number of seconds simulated +sim_ticks 768292872000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 23626.361612 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21626.361612 # average ReadReq mshr miss latency @@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.970134 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.968001 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 342925000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 343385000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks -system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) +system.cpu.dtb.accesses 153970296 # DTB accesses +system.cpu.dtb.acv 0 # DTB access violations +system.cpu.dtb.hits 153965363 # DTB hits +system.cpu.dtb.misses 4933 # DTB misses +system.cpu.dtb.read_accesses 114516673 # DTB read accesses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_hits 114514042 # DTB read hits +system.cpu.dtb.read_misses 2631 # DTB read misses +system.cpu.dtb.write_accesses 39453623 # DTB write accesses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_hits 39451321 # DTB write hits +system.cpu.dtb.write_misses 2302 # DTB write misses +system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses @@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 757051.787421 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency -system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits +system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses @@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 601856171 # number of overall hits +system.cpu.icache.overall_hits 601861103 # number of overall hits system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses @@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.685789 # Cycle average of tags in use -system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 673.685273 # Cycle average of tags in use +system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 601861918 # ITB accesses +system.cpu.itb.acv 0 # ITB acv +system.cpu.itb.hits 601861898 # ITB hits +system.cpu.itb.misses 20 # ITB misses system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency @@ -224,14 +240,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 13394 # number of replacements system.cpu.l2cache.sampled_refs 14881 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8423.446687 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8423.428104 # Cycle average of tags in use system.cpu.l2cache.total_refs 52084 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 768287940000 # number of cpu cycles simulated -system.cpu.num_insts 601856965 # Number of instructions executed -system.cpu.num_refs 154862034 # Number of memory references +system.cpu.numCycles 768292872000 # number of cpu cycles simulated +system.cpu.num_insts 601856964 # Number of instructions executed +system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 1ce1e7585..470af89eb 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -11,7 +11,7 @@ physmem=system.physmem [system.cpu] type=DerivO3CPU -children=dcache fuPool icache l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -36,6 +36,7 @@ decodeToRenameDelay=1 decodeWidth=8 defer_registration=false dispatchWidth=8 +dtb=system.cpu.dtb fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -53,6 +54,7 @@ iewToRenameDelay=1 instShiftAmt=2 issueToExecuteDelay=1 issueWidth=8 +itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 localHistoryTableSize=2048 @@ -130,6 +132,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 @@ -303,6 +309,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index 47c1d93f0..51c499e27 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 183168209 # Number of BTB hits -global.BPredUnit.BTBLookups 207693172 # Number of BTB lookups +global.BPredUnit.BTBHits 183932235 # Number of BTB hits +global.BPredUnit.BTBLookups 208089812 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 83686538 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 256168234 # Number of conditional branches predicted -global.BPredUnit.lookups 256168234 # Number of BP lookups +global.BPredUnit.condIncorrect 84447535 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted +global.BPredUnit.lookups 256528366 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 108517 # Simulator instruction rate (inst/s) -host_mem_usage 202532 # Number of bytes of host memory used -host_seconds 13726.13 # Real time elapsed on the host -host_tick_rate 80131991 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 457134527 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 154100032 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 745124340 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 301027499 # Number of stores inserted to the mem dependence unit. +host_inst_rate 100069 # Simulator instruction rate (inst/s) +host_mem_usage 184776 # Number of bytes of host memory used +host_seconds 14046.38 # Real time elapsed on the host +host_tick_rate 78132380 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 302069201 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514761 # Number of instructions simulated -sim_seconds 1.099902 # Number of seconds simulated -sim_ticks 1099901861500 # Number of ticks simulated +sim_insts 1405610550 # Number of instructions simulated +sim_seconds 1.097477 # Number of seconds simulated +sim_ticks 1097476890500 # Number of ticks simulated system.cpu.commit.COM:branches 86246390 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 9028629 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 9005633 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1956850179 +system.cpu.commit.COM:committed_per_cycle.samples 1955398373 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1082285235 5530.75% - 1 575067444 2938.74% - 2 119112331 608.69% - 3 121687931 621.86% - 4 26918285 137.56% - 5 9398970 48.03% - 6 9197638 47.00% - 7 4153716 21.23% - 8 9028629 46.14% + 0 1080294174 5524.68% + 1 576226777 2946.85% + 2 118746551 607.28% + 3 121516054 621.44% + 4 26673737 136.41% + 5 9328411 47.71% + 6 9370387 47.92% + 7 4236649 21.67% + 8 9005633 46.06% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 1489514761 # Number of instructions committed -system.cpu.commit.COM:loads 402511688 # Number of loads committed +system.cpu.commit.COM:count 1489528973 # Number of instructions committed +system.cpu.commit.COM:loads 402516086 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569359656 # Number of memory references committed +system.cpu.commit.COM:refs 569373868 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83686538 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489514761 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2243499 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1386494932 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1489514761 # Number of Instructions Simulated -system.cpu.committedInsts_total 1489514761 # Number of Instructions Simulated -system.cpu.cpi 1.476859 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.476859 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 432423106 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21577.217813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4456.675710 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 432175035 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5352682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 248071 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 707847 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1105572000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248071 # number of ReadReq MSHR misses +system.cpu.commit.branchMispredicts 84447535 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1399558822 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405610550 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated +system.cpu.cpi 1.561566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.561566 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 422711123 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 22402.386533 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4523.374198 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 422473917 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5313980500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 237206 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 708416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1072971500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 237206 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 7012.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5012.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 7025 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5025 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 280500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 281000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 200500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 201000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses -system.cpu.dcache.WriteReq_accesses 165036365 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 45516.173877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5913.886312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164687129 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15895886500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002116 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 349236 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1810277 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2065342000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002116 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 349236 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 165053813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 45668.908621 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.368381 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164707389 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 15820806000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 346424 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1802643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2049572000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 346424 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1139.085750 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1145.843097 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 597459471 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35573.948573 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency -system.cpu.dcache.demand_hits 596862164 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21248568500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.001000 # miss rate for demand accesses -system.cpu.dcache.demand_misses 597307 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2518124 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3170914000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001000 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 597307 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 587764936 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36212.645854 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency +system.cpu.dcache.demand_hits 587181306 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 21134786500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000993 # miss rate for demand accesses +system.cpu.dcache.demand_misses 583630 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2511059 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3122543500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000993 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 583630 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 597459471 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35573.948573 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5308.683809 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 587764936 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36212.645854 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5350.210750 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 596862164 # number of overall hits -system.cpu.dcache.overall_miss_latency 21248568500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.001000 # miss rate for overall accesses -system.cpu.dcache.overall_misses 597307 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2518124 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3170914000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001000 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 597307 # number of overall MSHR misses +system.cpu.dcache.overall_hits 587181306 # number of overall hits +system.cpu.dcache.overall_miss_latency 21134786500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000993 # miss rate for overall accesses +system.cpu.dcache.overall_misses 583630 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2511059 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3122543500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000993 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 583630 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 519953 # number of replacements -system.cpu.dcache.sampled_refs 524049 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 508412 # number of replacements +system.cpu.dcache.sampled_refs 512508 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.788106 # Cycle average of tags in use -system.cpu.dcache.total_refs 596936748 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 72857000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 346070 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 407153301 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3453639261 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 763587746 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 783418811 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 242953531 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2690321 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 256168234 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 355186488 # Number of cache lines fetched -system.cpu.fetch.Cycles 1201174807 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10202313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3743631874 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 91259594 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.116450 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 355186488 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 183168209 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.701803 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.762102 # Cycle average of tags in use +system.cpu.dcache.total_refs 587253754 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 80526000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 343259 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 406688141 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3452580675 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 760521931 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 785512506 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 239555254 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2675795 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 256528366 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 355016142 # Number of cache lines fetched +system.cpu.fetch.Cycles 1201036760 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10894008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3738352844 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 89458561 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.116872 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 355016142 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 183932235 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.703158 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2199803710 +system.cpu.fetch.rateDist.samples 2194953627 system.cpu.fetch.rateDist.min_value 0 - 0 1353815392 6154.26% - 1 255570605 1161.79% - 2 82946121 377.06% - 3 38413739 174.62% - 4 83998079 381.84% - 5 40983172 186.30% - 6 33041033 150.20% - 7 20511116 93.24% - 8 290524453 1320.68% + 0 1348933053 6145.61% + 1 256313247 1167.74% + 2 82698191 376.77% + 3 38326183 174.61% + 4 84519360 385.06% + 5 41105906 187.27% + 6 32923583 150.00% + 7 20556634 93.65% + 8 289577470 1319.29% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 355186427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7448.556625 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5296.447076 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 355185076 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10063000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 355016079 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7452.363368 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5292.836041 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 355014725 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 10090500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1351 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 7155500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 7166500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 262905.311621 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 262196.990399 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 355186427 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7448.556625 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency -system.cpu.icache.demand_hits 355185076 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10063000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 355016079 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 7452.363368 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency +system.cpu.icache.demand_hits 355014725 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 10090500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1351 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 7155500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 7166500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 355186427 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7448.556625 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5296.447076 # average overall mshr miss latency +system.cpu.icache.overall_accesses 355016079 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 7452.363368 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5292.836041 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 355185076 # number of overall hits -system.cpu.icache.overall_miss_latency 10063000 # number of overall miss cycles +system.cpu.icache.overall_hits 355014725 # number of overall hits +system.cpu.icache.overall_miss_latency 10090500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1351 # number of overall misses -system.cpu.icache.overall_mshr_hits 61 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 7155500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1354 # number of overall misses +system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 7166500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -222,183 +222,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 207 # number of replacements -system.cpu.icache.sampled_refs 1351 # Sample count of references to valid blocks. +system.cpu.icache.replacements 208 # number of replacements +system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1040.211796 # Cycle average of tags in use -system.cpu.icache.total_refs 355185076 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1042.348080 # Cycle average of tags in use +system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8497 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 126707080 # Number of branches executed -system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.003361 # Inst execution rate -system.cpu.iew.EXEC:refs 760962527 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 208093186 # Number of stores executed +system.cpu.idleCycles 94965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 128778452 # Number of branches executed +system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate +system.cpu.iew.EXEC:refs 753461994 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 210026063 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1493645383 # num instructions consuming a value -system.cpu.iew.WB:count 2165444744 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.962819 # average fanout of values written-back +system.cpu.iew.WB:consumers 1497813793 # num instructions consuming a value +system.cpu.iew.WB:count 1867109874 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963032 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1438109572 # num instructions producing a value -system.cpu.iew.WB:rate 0.984381 # insts written-back per cycle -system.cpu.iew.WB:sent 2178310152 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91514542 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 458290 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 745124340 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21362312 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17090675 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 301027499 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2876000922 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 552869341 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 140121943 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2207196457 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 56098 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1442442170 # num instructions producing a value +system.cpu.iew.WB:rate 0.850638 # insts written-back per cycle +system.cpu.iew.WB:sent 1877161047 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 745627925 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21367021 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 17089542 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 302069201 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2889153048 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 543435931 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 103575555 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1900567912 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61243 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 242953531 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 87287 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9772 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 239555254 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 95884 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 119737756 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 85786 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 119997179 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 80650 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 10100571 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 342612652 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134179531 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 10100571 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1514083 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90000459 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.677113 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.677113 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2347318400 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 5250080 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 343111839 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 135211419 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 5250080 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1516982 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 89810699 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.640383 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.640383 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 2004143467 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 351441317 14.97% # Type of FU issued - IntAlu 1181231771 50.32% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued + IntAlu 1186366605 59.20% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 3000185 0.13% # Type of FU issued + FloatAdd 3003253 0.15% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 586473179 24.98% # Type of FU issued - MemWrite 225171948 9.59% # Type of FU issued + MemRead 584611723 29.17% # Type of FU issued + MemWrite 230161886 11.48% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3997880 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.001703 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 6010355 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002999 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 155579 3.89% # attempts to use FU when none available + IntAlu 143340 2.38% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 244024 6.10% # attempts to use FU when none available + FloatAdd 241345 4.02% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available FloatCvt 0 0.00% # attempts to use FU when none available FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3267233 81.72% # attempts to use FU when none available - MemWrite 331044 8.28% # attempts to use FU when none available + MemRead 5244225 87.25% # attempts to use FU when none available + MemWrite 381445 6.35% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2199803710 +system.cpu.iq.ISSUE:issued_per_cycle.samples 2194953627 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 993478594 4516.21% - 1 570157916 2591.86% - 2 321116547 1459.75% - 3 178901320 813.26% - 4 92584833 420.88% - 5 34984610 159.04% - 6 7286511 33.12% - 7 1105050 5.02% - 8 188329 0.86% + 0 1076765226 4905.64% + 1 582878371 2655.54% + 2 298125643 1358.23% + 3 159003575 724.41% + 4 52530250 239.32% + 5 16707223 76.12% + 6 8404252 38.29% + 7 392238 1.79% + 8 146849 0.67% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.067058 # Inst issue rate -system.cpu.iq.iqInstsAdded 2854330173 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2347318400 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21670749 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1311892803 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 993660 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19427250 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1293606933 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 275979 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 4897.575540 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2897.575540 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1351628000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.913069 # Inst issue rate +system.cpu.iq.iqInstsAdded 2513084593 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2004143467 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21683766 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1087893079 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 3817087 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19440265 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1299740082 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 275303 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 4888.651776 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2888.651776 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1345860500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 275979 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 799670000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 275303 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 795254500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 275979 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 249421 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4201.208939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2201.208939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 64300 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 777732000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.742203 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 185121 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 407490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.742203 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 185121 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 73301 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4221.136137 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2221.136137 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 309413500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 275303 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 238559 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4206.099871 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2206.099871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 56424 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 766078000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.763480 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 182135 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 401808000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.763480 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 182135 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 71169 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4205.419494 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2205.419494 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 299295500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 73301 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 162811500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 71169 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 156957500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 73301 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 346070 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_mshr_misses 71169 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 343259 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 346070 # number of Writeback misses +system.cpu.l2cache.Writeback_misses 343259 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 346070 # number of Writeback MSHR misses +system.cpu.l2cache.Writeback_mshr_misses 343259 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.935065 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.652891 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 525400 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4618.000434 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 64300 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2129360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.877617 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 461100 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 513862 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4616.884693 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 56424 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2111938500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.890196 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 457438 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1207160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.877617 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 461100 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1197062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.890196 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 457438 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 525400 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4618.000434 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2618.000434 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 513862 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4616.884693 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2616.884693 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 64300 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2129360000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.877617 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 461100 # number of overall misses +system.cpu.l2cache.overall_hits 56424 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2111938500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.890196 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 457438 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1207160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.877617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 461100 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1197062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.890196 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 457438 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -411,31 +411,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 19390 # number of replacements -system.cpu.l2cache.sampled_refs 20790 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 20786 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8555.838166 # Cycle average of tags in use -system.cpu.l2cache.total_refs 102600 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 8527.413561 # Cycle average of tags in use +system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2199803710 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 12980165 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244762261 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 40711 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 826156851 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 20049545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4942866473 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3108910588 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2431469653 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 720639508 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 242953531 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 28416809 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1186707392 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 368656846 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21929426 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 159084902 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21683995 # count of temporary serializing insts renamed -system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 2194953627 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 47407 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 822770114 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 20101500 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4935577703 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3109070263 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2428488542 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 723045080 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 239555254 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 28402170 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1183717485 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 368180121 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21968418 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 159248004 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21723083 # count of temporary serializing insts renamed +system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 19 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout index 0785768bd..dc3199e5a 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 12:23:15 -M5 started Sun Aug 12 12:23:18 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 22:51:35 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1099901861500 because target called exit() +Exiting @ tick 1097476890500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 144c9c7fe..c0e8863c5 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU -children=workload +children=dtb itb tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -25,11 +27,23 @@ phase=0 progress_interval=0 simulate_stalls=false system=system +tracer=system.cpu.tracer width=1 workload=system.cpu.workload dcache_port=system.membus.port[2] icache_port=system.membus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + +[system.cpu.itb] +type=SparcITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 @@ -53,7 +67,7 @@ bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index bdafc8603..09530dafb 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 723585 # Simulator instruction rate (inst/s) -host_mem_usage 149576 # Number of bytes of host memory used -host_seconds 2058.52 # Real time elapsed on the host -host_tick_rate 361792205 # Simulator tick rate (ticks/s) +host_inst_rate 1870525 # Simulator instruction rate (inst/s) +host_mem_usage 176480 # Number of bytes of host memory used +host_seconds 796.31 # Real time elapsed on the host +host_tick_rate 935265227 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514860 # Number of instructions simulated -sim_seconds 0.744757 # Number of seconds simulated -sim_ticks 744757429500 # Number of ticks simulated +sim_insts 1489514761 # Number of instructions simulated +sim_seconds 0.744760 # Number of seconds simulated +sim_ticks 744759833500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1489514860 # number of cpu cycles simulated -system.cpu.num_insts 1489514860 # Number of instructions executed -system.cpu.num_refs 569359656 # Number of memory references +system.cpu.numCycles 1489519668 # number of cpu cycles simulated +system.cpu.num_insts 1489514761 # Number of instructions executed +system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index b335083d4..d033c7748 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled May 15 2007 13:02:31 -M5 started Tue May 15 13:02:33 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 22:51:35 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 744757429500 because target called exit() +Exiting @ tick 744759833500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 8f0821576..86d8c5b0f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -11,12 +11,14 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=dcache icache l2cache toL2Bus tracer workload +children=dcache dtb icache itb l2cache toL2Bus tracer workload clock=500 cpu_id=0 defer_registration=false +dtb=system.cpu.dtb function_trace=false function_trace_start=0 +itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -65,6 +67,10 @@ write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] +[system.cpu.dtb] +type=SparcDTB +size=64 + [system.cpu.icache] type=BaseCache addr_range=0:18446744073709551615 @@ -101,6 +107,10 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.itb] +type=SparcITB +size=64 + [system.cpu.l2cache] type=BaseCache addr_range=0:18446744073709551615 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index e732be59f..2a33edee7 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1190065 # Simulator instruction rate (inst/s) -host_mem_usage 201788 # Number of bytes of host memory used -host_seconds 1251.63 # Real time elapsed on the host -host_tick_rate 1654548560 # Simulator tick rate (ticks/s) +host_inst_rate 1120793 # Simulator instruction rate (inst/s) +host_mem_usage 183848 # Number of bytes of host memory used +host_seconds 1328.98 # Real time elapsed on the host +host_tick_rate 1558243449 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1489514860 # Number of instructions simulated -sim_seconds 2.070875 # Number of seconds simulated -sim_ticks 2070875212000 # Number of ticks simulated +sim_insts 1489514761 # Number of instructions simulated +sim_seconds 2.070880 # Number of seconds simulated +sim_ticks 2070879986000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency @@ -86,14 +86,14 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.520244 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.519446 # Cycle average of tags in use system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 358125000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 358580000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316447 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses @@ -102,16 +102,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1356574.259563 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses @@ -122,11 +122,11 @@ system.cpu.icache.demand_mshr_misses 1098 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489513763 # number of overall hits +system.cpu.icache.overall_hits 1489518537 # number of overall hits system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses @@ -148,8 +148,8 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.566276 # Cycle average of tags in use -system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 891.566024 # Cycle average of tags in use +system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -234,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 18201 # number of replacements system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8449.172652 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8449.165713 # Cycle average of tags in use system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2070875212000 # number of cpu cycles simulated -system.cpu.num_insts 1489514860 # Number of instructions executed -system.cpu.num_refs 569359656 # Number of memory references +system.cpu.numCycles 2070879986000 # number of cpu cycles simulated +system.cpu.num_insts 1489514761 # Number of instructions executed +system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 6d07eec7c..51f82ab6b 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 12 2007 12:23:15 -M5 started Sun Aug 12 16:24:16 2007 -M5 executing on zeep +M5 compiled Aug 14 2007 22:48:17 +M5 started Tue Aug 14 23:04:52 2007 +M5 executing on nacho command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2070875212000 because target called exit() +Exiting @ tick 2070879986000 because target called exit() |