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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-25 19:10:42 -0500 |
| commit | e6d3fe8a0c02e0692444399e63e6c5ce6c3abd17 (patch) | |
| tree | c8cc90c2577733fa32cd6250a9488450f65d8335 /tests/long/00.gzip | |
| parent | 4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe (diff) | |
| download | gem5-e6d3fe8a0c02e0692444399e63e6c5ce6c3abd17.tar.xz | |
ARM: Update regression tests for ldr/str microcode changes.
Diffstat (limited to 'tests/long/00.gzip')
4 files changed, 22 insertions, 22 deletions
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout index 95afc07f5..7e268bf61 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 25 2010 20:52:35 -M5 revision ffac9df60637 7512 default tip -M5 started Jul 26 2010 23:53:12 +M5 compiled Aug 24 2010 15:34:40 +M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase +M5 started Aug 24 2010 15:35:18 M5 executing on zizzer command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 298674141000 because target called exit() +Exiting @ tick 300302141500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt index f2e408360..1337ef958 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2670640 # Simulator instruction rate (inst/s) -host_mem_usage 197140 # Number of bytes of host memory used -host_seconds 223.66 # Real time elapsed on the host -host_tick_rate 1335369827 # Simulator tick rate (ticks/s) +host_inst_rate 4210115 # Simulator instruction rate (inst/s) +host_mem_usage 202336 # Number of bytes of host memory used +host_seconds 142.65 # Real time elapsed on the host +host_tick_rate 2105134486 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 597325393 # Number of instructions simulated -sim_seconds 0.298674 # Number of seconds simulated -sim_ticks 298674141000 # Number of ticks simulated +sim_insts 600581394 # Number of instructions simulated +sim_seconds 0.300302 # Number of seconds simulated +sim_ticks 300302141500 # Number of ticks simulated system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597348283 # number of cpu cycles simulated -system.cpu.num_insts 597325393 # Number of instructions executed +system.cpu.numCycles 600604284 # number of cpu cycles simulated +system.cpu.num_insts 600581394 # Number of instructions executed system.cpu.num_refs 219174038 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index 86786e4fe..b8e1d7eb2 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 25 2010 20:52:35 -M5 revision ffac9df60637 7512 default tip -M5 started Jul 26 2010 23:53:12 +M5 compiled Aug 24 2010 15:34:40 +M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase +M5 started Aug 24 2010 15:44:30 M5 executing on zizzer command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index e4204dab3..bd7d26f79 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1588198 # Simulator instruction rate (inst/s) -host_mem_usage 204824 # Number of bytes of host memory used -host_seconds 374.87 # Real time elapsed on the host -host_tick_rate 2155749682 # Simulator tick rate (ticks/s) +host_inst_rate 1674821 # Simulator instruction rate (inst/s) +host_mem_usage 210020 # Number of bytes of host memory used +host_seconds 357.42 # Real time elapsed on the host +host_tick_rate 2260963263 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 595363823 # Number of instructions simulated +sim_insts 598619824 # Number of instructions simulated sim_seconds 0.808121 # Number of seconds simulated sim_ticks 808121048000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) @@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 61092 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1616242096 # number of cpu cycles simulated -system.cpu.num_insts 595363823 # Number of instructions executed +system.cpu.num_insts 598619824 # Number of instructions executed system.cpu.num_refs 219174038 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |