diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/00.gzip | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/00.gzip')
18 files changed, 1025 insertions, 1091 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 850b52f90..93b3428c5 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 9bd144353..d26bd1d3b 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:05 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:56:01 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -46,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 169506496500 because target called exit() +Exiting @ tick 165376986500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 29244fba0..13a46d5d3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178555 # Simulator instruction rate (inst/s) -host_mem_usage 207544 # Number of bytes of host memory used -host_seconds 3167.39 # Real time elapsed on the host -host_tick_rate 53516139 # Simulator tick rate (ticks/s) +host_inst_rate 264030 # Simulator instruction rate (inst/s) +host_mem_usage 193748 # Number of bytes of host memory used +host_seconds 2142.00 # Real time elapsed on the host +host_tick_rate 77206740 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.169506 # Number of seconds simulated -sim_ticks 169506496500 # Number of ticks simulated +sim_seconds 0.165377 # Number of seconds simulated +sim_ticks 165376986500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 64068954 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 71556079 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4120910 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70589657 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76519042 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1672225 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 19702213 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 327417755 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.838193 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.277454 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 105871733 32.34% 32.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 108541066 33.15% 65.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 36996526 11.30% 76.79% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 11988281 3.66% 80.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 10398233 3.18% 83.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21777635 6.65% 90.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 9735285 2.97% 93.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2406783 0.74% 93.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 19702213 6.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 327417755 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4120073 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 63088611 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.599437 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.599437 # CPI: Total CPI of All Threads +system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 116877204 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7693.277195 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 116024078 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16646128000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007299 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853126 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 634854 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1679227000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001868 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 218272 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37146976 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 73589663391 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.058410 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2304345 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1968193 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 11570226999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008521 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 336152 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7088.486726 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 323.627554 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 800999 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 156328525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 28578.502032 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153171054 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 90235791391 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020198 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3157471 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2603047 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13249453999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 554424 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency +system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999568 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.232018 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 156328525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 28578.502032 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153171054 # number of overall hits -system.cpu.dcache.overall_miss_latency 90235791391 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020198 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3157471 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2603047 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13249453999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 554424 # number of overall MSHR misses +system.cpu.dcache.overall_hits 152530559 # number of overall hits +system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1933689 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 471007 # number of replacements -system.cpu.dcache.sampled_refs 475103 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 471004 # number of replacements +system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.232018 # Cycle average of tags in use -system.cpu.dcache.total_refs 153756422 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126427000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 336082 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 53096224 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 870 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4174977 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 691367918 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 145684312 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123209609 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 10007520 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3007 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5427610 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163170180 # DTB accesses +system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use +system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 423151 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163094811 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163108618 # DTB hits -system.cpu.dtb.data_misses 61562 # DTB misses +system.cpu.dtb.data_hits 163045966 # DTB hits +system.cpu.dtb.data_misses 48845 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122378622 # DTB read accesses +system.cpu.dtb.read_accesses 122278185 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122354151 # DTB read hits -system.cpu.dtb.read_misses 24471 # DTB read misses -system.cpu.dtb.write_accesses 40791558 # DTB write accesses +system.cpu.dtb.read_hits 122255138 # DTB read hits +system.cpu.dtb.read_misses 23047 # DTB read misses +system.cpu.dtb.write_accesses 40816626 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40754467 # DTB write hits -system.cpu.dtb.write_misses 37091 # DTB write misses -system.cpu.fetch.Branches 76519042 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65743933 # Number of cache lines fetched -system.cpu.fetch.Cycles 196171036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1323544 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 700543147 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4180854 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.225711 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65743933 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 65741179 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.066420 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 337425275 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.076143 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.069329 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 40790828 # DTB write hits +system.cpu.dtb.write_misses 25798 # DTB write misses +system.cpu.fetch.Branches 76396550 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65649275 # Number of cache lines fetched +system.cpu.fetch.Cycles 195872330 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1325100 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 699185184 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4170349 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230977 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65649275 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 65605896 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.113913 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 330660336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.114512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.085107 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 206998212 61.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10205574 3.02% 64.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 16013127 4.75% 69.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13976667 4.14% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12062274 3.57% 76.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13987466 4.15% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5886424 1.74% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3487900 1.03% 83.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54807631 16.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 200437318 60.62% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10372140 3.14% 63.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15863919 4.80% 68.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13948828 4.22% 72.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12077397 3.65% 76.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13850642 4.19% 80.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5888624 1.78% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3427564 1.04% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 54793904 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 337425275 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 65743933 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36198.392555 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35509.868421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65742751 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42786500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 330660336 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 65649275 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36269.949066 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65648097 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42726000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1182 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32385000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1178 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 268 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32327500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 912 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 72086.349781 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 72140.765934 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65743933 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36198.392555 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency -system.cpu.icache.demand_hits 65742751 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42786500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65649275 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36269.949066 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency +system.cpu.icache.demand_hits 65648097 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42726000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1182 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32385000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1178 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 268 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32327500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 912 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.379446 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 777.105869 # Average occupied blocks per context -system.cpu.icache.overall_accesses 65743933 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36198.392555 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.378879 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 775.944948 # Average occupied blocks per context +system.cpu.icache.overall_accesses 65649275 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36269.949066 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65742751 # number of overall hits -system.cpu.icache.overall_miss_latency 42786500 # number of overall miss cycles +system.cpu.icache.overall_hits 65648097 # number of overall hits +system.cpu.icache.overall_miss_latency 42726000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1182 # number of overall misses -system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32385000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1178 # number of overall misses +system.cpu.icache.overall_mshr_hits 268 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32327500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 912 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.sampled_refs 912 # Sample count of references to valid blocks. +system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 777.105869 # Cycle average of tags in use -system.cpu.icache.total_refs 65742751 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 775.944948 # Cycle average of tags in use +system.cpu.icache.total_refs 65648097 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1587719 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67446690 # Number of branches executed -system.cpu.iew.EXEC:nop 43287555 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.768234 # Inst execution rate -system.cpu.iew.EXEC:refs 164109637 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41186586 # Number of stores executed +system.cpu.idleCycles 93638 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67433622 # Number of branches executed +system.cpu.iew.EXEC:nop 43234709 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.811577 # Inst execution rate +system.cpu.iew.EXEC:refs 164032675 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41211382 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 494218268 # num instructions consuming a value -system.cpu.iew.WB:count 596241723 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.805354 # average fanout of values written-back +system.cpu.iew.WB:consumers 492720055 # num instructions consuming a value +system.cpu.iew.WB:count 595983189 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.807592 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 398020536 # num instructions producing a value -system.cpu.iew.WB:rate 1.758758 # insts written-back per cycle -system.cpu.iew.WB:sent 597367655 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4601660 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251946 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 127252956 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3156398 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43259984 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 665052109 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122923051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6371334 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599454333 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2449 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 397916939 # num instructions producing a value +system.cpu.iew.WB:rate 1.801893 # insts written-back per cycle +system.cpu.iew.WB:sent 597091543 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4603878 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1505457 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126939472 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3143406 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43126164 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663744184 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122821293 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6299898 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599186314 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2121 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 33854 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 10007520 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 83713 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 28444 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9844039 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 43665 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 175 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 5470953 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10609 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 720 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7235686 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12544 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 93535 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5935 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 12203446 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3447461 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 93535 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 944573 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3657087 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.668232 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.668232 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 71476 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5929 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11889962 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3313641 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 71476 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 943110 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3660768 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.709889 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.709889 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 438988101 72.46% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6710 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 438748901 72.46% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.46% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 30 0.00% 72.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.46% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124874272 20.61% 93.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956540 6.93% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124774485 20.61% 93.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956101 6.93% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605825667 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 6927509 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011435 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 605486212 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 7206090 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5320205 76.80% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 51 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1245764 17.98% 94.78% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 361489 5.22% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5226098 72.52% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 72.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1579159 21.91% 94.44% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 400785 5.56% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 337425275 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.795437 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.663310 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 330660336 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.831143 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.672265 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 95395357 28.27% 28.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 68329461 20.25% 48.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 80056631 23.73% 72.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 36910615 10.94% 83.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 31840128 9.44% 92.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 12299933 3.65% 96.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 10951663 3.25% 99.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1050952 0.31% 99.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 590535 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 90539952 27.38% 27.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 66701453 20.17% 47.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 79600053 24.07% 71.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 36541170 11.05% 82.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 31317153 9.47% 92.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 13281184 4.02% 96.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 11041150 3.34% 99.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1066057 0.32% 99.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 572164 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 337425275 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.787028 # Inst issue rate -system.cpu.iq.iqInstsAdded 621764526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605825667 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 54809333 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 18475 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 31050369 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 330660336 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.830624 # Inst issue rate +system.cpu.iq.iqInstsAdded 620509446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605486212 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53535562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 17232 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29599324 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 65743973 # ITB accesses +system.cpu.itb.fetch_accesses 65649312 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 65743933 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.itb.fetch_hits 65649275 # ITB hits +system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,107 +343,98 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 256831 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.808951 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.097625 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12642 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8367822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.950777 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 244189 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7606267000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950777 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 244189 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 219184 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34300.593807 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31016.018663 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 183819 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1213040500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.161348 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35365 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1096881500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.161348 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35365 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 79334 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34139.271939 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31029.539668 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2708405000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 79334 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2461697500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 79334 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 336082 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 336082 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5312.500000 # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_accesses 256918 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 197081 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2065711500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.232903 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1879254000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 219092 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 186176 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1131972500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.150238 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32916 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1021003500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150238 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32916 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 423151 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 423151 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5261.194030 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.798768 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 5.283534 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 67 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 382500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 352500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 476015 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34271.956402 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 196461 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9580862500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.587280 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 279554 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 476010 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34475.262256 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 383257 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3197684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.194855 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 92753 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8703148500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.587280 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 279554 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2900257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.194855 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 92753 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052597 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.448200 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1723.488326 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14686.601231 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 476015 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34271.956402 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.052815 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.488399 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1730.637326 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16003.856484 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 476010 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34475.262256 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 196461 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9580862500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.587280 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 279554 # number of overall misses +system.cpu.l2cache.overall_hits 383257 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3197684000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.194855 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 92753 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8703148500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.587280 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 279554 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2900257500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.194855 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 92753 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84626 # number of replacements -system.cpu.l2cache.sampled_refs 100342 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 74446 # number of replacements +system.cpu.l2cache.sampled_refs 90349 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16410.089557 # Cycle average of tags in use -system.cpu.l2cache.total_refs 381176 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17734.493810 # Cycle average of tags in use +system.cpu.l2cache.total_refs 477362 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 62683 # number of writebacks -system.cpu.memDep0.conflictingLoads 23861424 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18454491 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 127252956 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43259984 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 339012994 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14846495 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 59324 # number of writebacks +system.cpu.memDep0.conflictingLoads 22261692 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15435128 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 126939472 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43126164 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 330753974 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 12738848 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 36228613 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 153406470 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1884931 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 97 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 897942713 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 681539497 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519842559 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115704820 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 10007520 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 43459223 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55987670 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 747 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 87364721 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.timesIdled 36935 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 34708853 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151708807 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 618719 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 896183749 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680208714 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518824645 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115765657 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9844039 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 40602289 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54969756 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 696 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 79641546 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.timesIdled 3516 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 850a6530b..028c210bb 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index d9a9a6b92..9cd4e92a6 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:59:22 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 16:13:16 +M5 executing on phenom command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -46,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 777351681000 because target called exit() +Exiting @ tick 765623032000 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index c92f137ce..ff829944e 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1386497 # Simulator instruction rate (inst/s) -host_mem_usage 206712 # Number of bytes of host memory used -host_seconds 434.08 # Real time elapsed on the host -host_tick_rate 1790782589 # Simulator tick rate (ticks/s) +host_inst_rate 1603392 # Simulator instruction rate (inst/s) +host_mem_usage 192888 # Number of bytes of host memory used +host_seconds 375.37 # Real time elapsed on the host +host_tick_rate 2039675547 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated -sim_seconds 0.777352 # Number of seconds simulated -sim_ticks 777351681000 # Number of ticks simulated +sim_seconds 0.765623 # Number of seconds simulated +sim_ticks 765623032000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4227398000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4126262000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3623702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3522566000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 39124493 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17781358000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.008284 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 326828 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16800874000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008284 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 326828 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6081180000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5318691000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41678.513805 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153437303 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 22008756000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003430 # miss rate for demand accesses -system.cpu.dcache.demand_misses 528060 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22414.479737 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10207442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses +system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20424576000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003430 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 528060 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8841257000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999560 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.197079 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.170317 # Average occupied blocks per context system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41678.513805 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38678.513805 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22414.479737 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153437303 # number of overall hits -system.cpu.dcache.overall_miss_latency 22008756000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003430 # miss rate for overall accesses -system.cpu.dcache.overall_misses 528060 # number of overall misses +system.cpu.dcache.overall_hits 153509968 # number of overall hits +system.cpu.dcache.overall_miss_latency 10207442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses +system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20424576000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003430 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 528060 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8841257000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.197079 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 578599000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 325740 # number of writebacks +system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 408190 # number of writebacks system.cpu.dtb.data_accesses 153970296 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 153965363 # DTB hits @@ -121,8 +121,8 @@ system.cpu.icache.demand_mshr_misses 795 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.328737 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 673.252668 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.328778 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 673.337154 # Average occupied blocks per context system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -140,7 +140,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 673.252668 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -164,37 +164,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12405 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12571416000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.951193 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 241758 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9670320000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.951193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 241758 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 194094 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 167657 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1787240000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.170126 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34370 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1374800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170126 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34370 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 72665 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3778580000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 72665 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2906600000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 72665 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 325740 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 325740 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 170065 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 31962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 408190 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.553777 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -203,44 +194,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 180062 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14358656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.605292 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 276128 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 364159 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11045120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.605292 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 276128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052155 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.448358 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1709.012624 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14691.802112 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.052565 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491366 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1722.436058 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16101.078831 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 180062 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14358656000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.605292 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 276128 # number of overall misses +system.cpu.l2cache.overall_hits 364159 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 92031 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11045120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.605292 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 276128 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 83906 # number of replacements -system.cpu.l2cache.sampled_refs 99616 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 73734 # number of replacements +system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16400.814735 # Cycle average of tags in use -system.cpu.l2cache.total_refs 354013 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 62672 # number of writebacks +system.cpu.l2cache.writebacks 59341 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1554703362 # number of cpu cycles simulated +system.cpu.numCycles 1531246064 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini index 4bef17201..19272883f 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout index b26d693cf..107f995a8 100755 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:52:30 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:54:54 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:05:18 +M5 executing on phenom command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -45,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 807517408000 because target called exit() +Exiting @ tick 796759936000 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt index 4b4cf244a..11f65fd19 100644 --- a/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1492183 # Simulator instruction rate (inst/s) -host_mem_usage 211112 # Number of bytes of host memory used -host_seconds 401.17 # Real time elapsed on the host -host_tick_rate 2012902303 # Simulator tick rate (ticks/s) +host_inst_rate 1338185 # Simulator instruction rate (inst/s) +host_mem_usage 196956 # Number of bytes of host memory used +host_seconds 447.34 # Real time elapsed on the host +host_tick_rate 1781116972 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 598619824 # Number of instructions simulated -sim_seconds 0.807517 # Number of seconds simulated -sim_ticks 807517408000 # Number of ticks simulated +sim_seconds 0.796760 # Number of seconds simulated +sim_ticks 796759936000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20842.812219 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.812219 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3956862000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3387333000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 69171110 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency -system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses -system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22578.791611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency +system.cpu.dcache.demand_hits 216774877 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9880276000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002015 # miss rate for demand accesses +system.cpu.dcache.demand_misses 437591 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8567503000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002015 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 437591 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999566 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.223177 # Average occupied blocks per context system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22578.791611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19578.791611 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 216715375 # number of overall hits -system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses -system.cpu.dcache.overall_misses 497093 # number of overall misses +system.cpu.dcache.overall_hits 216774877 # number of overall hits +system.cpu.dcache.overall_miss_latency 9880276000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002015 # miss rate for overall accesses +system.cpu.dcache.overall_misses 437591 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8567503000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002015 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 437591 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 433495 # number of replacements system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.223177 # Cycle average of tags in use system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 305501 # number of writebacks +system.cpu.dcache.writebacks 392389 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -114,8 +114,8 @@ system.cpu.icache.demand_mshr_misses 643 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.282094 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 577.728453 # Average occupied blocks per context system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency @@ -133,7 +133,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 12 # number of replacements system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use +system.cpu.icache.tagsinuse 577.728453 # Cycle average of tags in use system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -150,37 +150,28 @@ system.cpu.itb.write_misses 0 # DT system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 158940 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1640392000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.165608 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 31546 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1261840000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165608 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 31546 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 392389 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 392389 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.718118 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -189,44 +180,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 348237 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4679844000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.205363 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 89997 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3599880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.205363 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 89997 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.053819 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.492601 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1763.554655 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16141.554862 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 170026 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 268208 # number of overall misses +system.cpu.l2cache.overall_hits 348237 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4679844000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.205363 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 89997 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3599880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.205363 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 89997 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 80841 # number of replacements -system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 71809 # number of replacements +system.cpu.l2cache.sampled_refs 87292 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use -system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17905.109517 # Cycle average of tags in use +system.cpu.l2cache.total_refs 411854 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 60805 # number of writebacks +system.cpu.l2cache.writebacks 57886 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1615034816 # number of cpu cycles simulated +system.cpu.numCycles 1593519872 # number of cpu cycles simulated system.cpu.num_insts 598619824 # Number of instructions executed system.cpu.num_refs 219174038 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 659cb8ca7..5d6f66b52 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index d11cb55dd..b4e773530 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:05:09 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 16:20:33 +M5 executing on phenom command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -45,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1088441503500 because target called exit() +Exiting @ tick 1095331467500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 8e3cfada7..68e9f863d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,423 +1,414 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 76473 # Simulator instruction rate (inst/s) -host_mem_usage 212472 # Number of bytes of host memory used -host_seconds 18380.70 # Real time elapsed on the host -host_tick_rate 59216546 # Simulator tick rate (ticks/s) +host_inst_rate 138841 # Simulator instruction rate (inst/s) +host_mem_usage 198176 # Number of bytes of host memory used +host_seconds 10123.96 # Real time elapsed on the host +host_tick_rate 108192045 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618369 # Number of instructions simulated -sim_seconds 1.088442 # Number of seconds simulated -sim_ticks 1088441503500 # Number of ticks simulated +sim_insts 1405618374 # Number of instructions simulated +sim_seconds 1.095331 # Number of seconds simulated +sim_ticks 1095331467500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 173420048 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 194153919 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 175591574 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 198504175 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 81907161 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 251603669 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 251603669 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 83489596 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 252577407 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 252577407 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8072747 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 9068364 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1941955406 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.767030 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.200667 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1951658061 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.763216 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.203742 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 1072656731 55.24% 55.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 568585470 29.28% 84.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 118066725 6.08% 90.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 122346784 6.30% 96.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 28028862 1.44% 98.34% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 8610798 0.44% 98.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11084197 0.57% 99.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 4503092 0.23% 99.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8072747 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 1079992719 55.34% 55.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 573544089 29.39% 84.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 118996755 6.10% 90.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 118578034 6.08% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 27958213 1.43% 98.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 7829070 0.40% 98.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 11095017 0.57% 99.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 4595800 0.24% 99.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 9068364 0.46% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1941955406 # Number of insts commited each cycle -system.cpu.commit.COM:count 1489537512 # Number of instructions committed -system.cpu.commit.COM:loads 402517247 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 1951658061 # Number of insts commited each cycle +system.cpu.commit.COM:count 1489537517 # Number of instructions committed +system.cpu.commit.COM:loads 402517252 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375203 # Number of memory references committed +system.cpu.commit.COM:refs 569375208 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 81907161 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions +system.cpu.commit.branchMispredicts 83489596 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537517 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1348785802 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618369 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated -system.cpu.cpi 1.548701 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.548701 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 421715823 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14253.643501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6923.398779 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 420813257 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12864854000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002140 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 902566 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 664404 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1648890500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 238162 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 1344365389 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618374 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618374 # Number of Instructions Simulated +system.cpu.cpi 1.558505 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.558505 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 428071377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13932.868577 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6644.344451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 427202678 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12103469000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002029 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 868699 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 619015 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1658986500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 249684 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 684500 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 630500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164663038 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 80123447685 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013147 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2193592 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1850133 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12044158308 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002058 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 343459 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 14486.830110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11574.912497 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 165064790 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 25958081664 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010739 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1791840 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1512123 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3237699799 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001676 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 279717 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1140.778331 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1118.737886 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 588572453 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30033.448450 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency -system.cpu.dcache.demand_hits 585476295 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 92988301685 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005260 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3096158 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2514537 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13693048808 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000988 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 581621 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 594928007 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14305.954795 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency +system.cpu.dcache.demand_hits 592267468 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38061550664 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.004472 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2660539 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2131138 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4896686299 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000890 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 529401 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.574913 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 588572453 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30033.448450 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23542.906477 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.577700 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 594928007 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14305.954795 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 585476295 # number of overall hits -system.cpu.dcache.overall_miss_latency 92988301685 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005260 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3096158 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2514537 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13693048808 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000988 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 581621 # number of overall MSHR misses +system.cpu.dcache.overall_hits 592267468 # number of overall hits +system.cpu.dcache.overall_miss_latency 38061550664 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.004472 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2660539 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2131138 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4896686299 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000890 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 529401 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 509328 # number of replacements -system.cpu.dcache.sampled_refs 513424 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 525312 # number of replacements +system.cpu.dcache.sampled_refs 529408 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.574913 # Cycle average of tags in use -system.cpu.dcache.total_refs 585702974 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165969000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 343309 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 421597556 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3393767574 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 753336946 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 764050676 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 233579864 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2970228 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 251603669 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 350205998 # Number of cache lines fetched -system.cpu.fetch.Cycles 1175621134 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10022642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3685217760 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 87763558 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115580 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 350205998 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 173420048 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.692887 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 2175535270 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.844478 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.577700 # Cycle average of tags in use +system.cpu.dcache.total_refs 592268787 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 165936000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 467492 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 419165001 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3408944329 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 761736999 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 767859019 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 238675861 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2897042 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 252577407 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 355041427 # Number of cache lines fetched +system.cpu.fetch.Cycles 1184621367 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 11557522 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3696750718 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 90055290 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115297 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 355041427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 175591574 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.687503 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 2190333922 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.687757 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.837142 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1350120177 62.06% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 247723459 11.39% 73.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 78876862 3.63% 77.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36715633 1.69% 78.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82505940 3.79% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 39095379 1.80% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30113044 1.38% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 19663449 0.90% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 290721327 13.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1360754025 62.13% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 248782776 11.36% 73.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 79015111 3.61% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36736924 1.68% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 85275355 3.89% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 39319900 1.80% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30979848 1.41% 85.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19612924 0.90% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 289857059 13.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2175535270 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 350205998 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33274.163131 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34791.817524 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 350203877 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70574500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 2190333922 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 355041427 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33183.081998 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34797.601744 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 355039305 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70414500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2121 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 740 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 48047500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 2122 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 746 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 47881500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1376 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 253770.925362 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 258210.403636 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 350205998 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33274.163131 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency -system.cpu.icache.demand_hits 350203877 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70574500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 355041427 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33183.081998 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency +system.cpu.icache.demand_hits 355039305 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70414500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2121 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 740 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 48047500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 2122 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 746 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 47881500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1376 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.517204 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1059.233334 # Average occupied blocks per context -system.cpu.icache.overall_accesses 350205998 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33274.163131 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.517160 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1059.143452 # Average occupied blocks per context +system.cpu.icache.overall_accesses 355041427 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33183.081998 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 350203877 # number of overall hits -system.cpu.icache.overall_miss_latency 70574500 # number of overall miss cycles +system.cpu.icache.overall_hits 355039305 # number of overall hits +system.cpu.icache.overall_miss_latency 70414500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2121 # number of overall misses -system.cpu.icache.overall_mshr_hits 740 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 48047500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 2122 # number of overall misses +system.cpu.icache.overall_mshr_hits 746 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 47881500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1376 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 223 # number of replacements -system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks. +system.cpu.icache.replacements 218 # number of replacements +system.cpu.icache.sampled_refs 1375 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1059.233334 # Cycle average of tags in use -system.cpu.icache.total_refs 350203877 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1059.143452 # Cycle average of tags in use +system.cpu.icache.total_refs 355039305 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1347738 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 126526916 # Number of branches executed -system.cpu.iew.EXEC:nop 340982559 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.865733 # Inst execution rate -system.cpu.iew.EXEC:refs 746184493 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 208199925 # Number of stores executed +system.cpu.idleCycles 329014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 129329311 # Number of branches executed +system.cpu.iew.EXEC:nop 343977069 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.860181 # Inst execution rate +system.cpu.iew.EXEC:refs 750434371 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 206174463 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1479878942 # num instructions consuming a value -system.cpu.iew.WB:count 1850747692 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963175 # average fanout of values written-back +system.cpu.iew.WB:consumers 1480496045 # num instructions consuming a value +system.cpu.iew.WB:count 1847584929 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.961963 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1425382580 # num instructions producing a value -system.cpu.iew.WB:rate 0.850182 # insts written-back per cycle -system.cpu.iew.WB:sent 1860799390 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 88298258 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3065589 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 732363888 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21345183 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 16501703 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 296834010 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2838380214 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 537984568 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 98702938 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1884599663 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42681 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1424182878 # num instructions producing a value +system.cpu.iew.WB:rate 0.843391 # insts written-back per cycle +system.cpu.iew.WB:sent 1859595547 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 91828645 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2291655 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 731683017 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21329829 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 16631995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 299730608 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2833977471 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 544259908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 92682608 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1884367319 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 43246 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10075 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 233579864 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 76418 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 5071 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 238675861 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 70086 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 3315 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 116246268 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 24120 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 28836 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 116166112 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 85848 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 6177679 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 329846641 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 129976054 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 6177679 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2822462 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 85475796 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.645702 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.645702 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 6831445 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 329165765 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 132872652 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6831445 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2781524 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 89047121 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.641641 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.641641 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178510091 59.42% 59.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2995561 0.15% 59.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.57% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 574193114 28.95% 88.52% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 227603835 11.48% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1175590605 59.46% 59.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2994259 0.15% 59.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 570634170 28.86% 88.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 227830893 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1983302601 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 6030045 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.003040 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1977049927 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4131140 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002090 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 148667 2.47% 2.47% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 233339 3.87% 6.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 6.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5333431 88.45% 94.78% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 314608 5.22% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 148870 3.60% 3.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 222262 5.38% 8.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.98% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3423281 82.87% 91.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 336727 8.15% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 2175535270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.911639 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.163576 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 2190333922 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902625 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.145189 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 1067990413 49.09% 49.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 580044793 26.66% 75.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 292279315 13.43% 89.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 158370905 7.28% 96.47% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 51349615 2.36% 98.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 15864540 0.73% 99.56% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 8721161 0.40% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 777887 0.04% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 136641 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 1077130624 49.18% 49.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 581443700 26.55% 75.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 301967857 13.79% 89.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 159877963 7.30% 96.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 45264546 2.07% 98.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 18451049 0.84% 99.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 4794612 0.22% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1273045 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 130526 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 2175535270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.911075 # Inst issue rate -system.cpu.iq.iqInstsAdded 2475761446 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1983302601 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21636209 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1050320205 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 3387342 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19392538 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1256970263 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 275262 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34309.417551 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31170.249101 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 11754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 9040806000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.957299 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 263508 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8213610000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.957299 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 263508 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 239543 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 204890 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1181858000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.144663 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34653 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1074330000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144663 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34653 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 68215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2333844500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 68215 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2116155000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 68215 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 343309 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 343309 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 2190333922 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.902489 # Inst issue rate +system.cpu.iq.iqInstsAdded 2468355699 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1977049927 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21644703 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1031033219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 637277 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19401032 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1242826340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 279724 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34530.938042 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31386.377770 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 218618 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2110047500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.218451 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 61106 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1917896000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.218451 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 61106 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 251060 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34076.007326 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.126905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 217208 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1153541000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.134836 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33852 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1049484000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.134836 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33852 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 467492 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 467492 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.105608 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.866131 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 514805 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34285.718119 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 216644 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10222664000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.579173 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 298161 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 530784 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34368.757767 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 435826 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3263588500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.178901 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 94958 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9287940000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.579173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 298161 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2967380000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.178901 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 94958 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.057090 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.444973 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1870.709103 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14580.888860 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 514805 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34285.718119 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.061469 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.477467 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2014.215255 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15645.646003 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 530784 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34368.757767 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 216644 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10222664000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.579173 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 298161 # number of overall misses +system.cpu.l2cache.overall_hits 435826 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3263588500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.178901 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 94958 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9287940000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.579173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 298161 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2967380000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.178901 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 94958 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 83969 # number of replacements -system.cpu.l2cache.sampled_refs 99434 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 76745 # number of replacements +system.cpu.l2cache.sampled_refs 92262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16451.597962 # Cycle average of tags in use -system.cpu.l2cache.total_refs 408237 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17659.861257 # Cycle average of tags in use +system.cpu.l2cache.total_refs 541221 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61561 # number of writebacks -system.cpu.memDep0.conflictingLoads 445088392 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 142143895 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 732363888 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 296834010 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 2176883008 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 18665128 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 724 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 28925 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 816745640 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 24395596 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4856285750 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3051371057 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2392375919 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 700064958 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 233579864 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 34053219 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1147596661 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 372426461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21718962 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 176891245 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21553313 # count of temporary serializing insts renamed -system.cpu.timesIdled 41709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.l2cache.writebacks 59365 # number of writebacks +system.cpu.memDep0.conflictingLoads 443698156 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 136383139 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 731683017 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 299730608 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2190662936 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 17189054 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779268 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 463 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 34257 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 824291881 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 24214806 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4869886562 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3060544953 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2396042530 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 704670101 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 238675861 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 33809858 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1151263262 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 371697167 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21697179 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 175779479 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21533408 # count of temporary serializing insts renamed +system.cpu.timesIdled 8581 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 9514e3ea7..9772b8626 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 833f1cfc2..78e3d8264 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:03:41 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:04:04 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 16:28:00 +M5 executing on phenom command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -45,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2075400743000 because target called exit() +Exiting @ tick 2064258667000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 736d779d0..04e7c144d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1385286 # Simulator instruction rate (inst/s) -host_mem_usage 211532 # Number of bytes of host memory used -host_seconds 1075.25 # Real time elapsed on the host -host_tick_rate 1930162951 # Simulator tick rate (ticks/s) +host_inst_rate 1333935 # Simulator instruction rate (inst/s) +host_mem_usage 197236 # Number of bytes of host memory used +host_seconds 1116.64 # Real time elapsed on the host +host_tick_rate 1848636408 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.075401 # Number of seconds simulated -sim_ticks 2075400743000 # Number of ticks simulated +sim_seconds 2.064259 # Number of seconds simulated +sim_ticks 2064258667000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. @@ -47,42 +47,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency -system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses -system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency +system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses +system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 568847975 # number of overall hits -system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000899 # miss rate for overall accesses -system.cpu.dcache.overall_misses 511685 # number of overall misses +system.cpu.dcache.overall_hits 568906446 # number of overall hits +system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses +system.cpu.dcache.overall_misses 453214 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000899 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 316439 # number of writebacks +system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 407009 # number of writebacks system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency @@ -115,8 +115,8 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.442603 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency @@ -134,7 +134,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use +system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -142,37 +142,28 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12877124000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.953422 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1737320000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.448937 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -181,44 +172,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 173281 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14614444000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.618599 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 281047 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11241880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.618599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 281047 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052996 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447533 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1736.572582 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14664.762880 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.057187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.483685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 173281 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14614444000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.618599 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 281047 # number of overall misses +system.cpu.l2cache.overall_hits 361985 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 92343 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11241880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.618599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 281047 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 82461 # number of replacements -system.cpu.l2cache.sampled_refs 97909 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 74112 # number of replacements +system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16401.335462 # Cycle average of tags in use -system.cpu.l2cache.total_refs 337682 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use +system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61551 # number of writebacks +system.cpu.l2cache.writebacks 59035 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4150801486 # number of cpu cycles simulated +system.cpu.numCycles 4128517334 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini index 1bbdb5a19..da2490100 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini @@ -157,7 +157,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 5c6b0de63..d309b71a7 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 13:20:12 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 13:33:02 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:49 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:29:10 +M5 executing on phenom command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -46,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1814105620000 because target called exit() +Exiting @ tick 1803258587000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index f79a1a362..f28dbcde3 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1308474 # Simulator instruction rate (inst/s) -host_mem_usage 210192 # Number of bytes of host memory used -host_seconds 1237.60 # Real time elapsed on the host -host_tick_rate 1465826235 # Simulator tick rate (ticks/s) +host_inst_rate 1292356 # Simulator instruction rate (inst/s) +host_mem_usage 195556 # Number of bytes of host memory used +host_seconds 1253.03 # Real time elapsed on the host +host_tick_rate 1439113315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619366787 # Number of instructions simulated -sim_seconds 1.814106 # Number of seconds simulated -sim_ticks 1814105620000 # Number of ticks simulated +sim_seconds 1.803259 # Number of seconds simulated +sim_ticks 1803258587000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks. @@ -37,42 +37,42 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency -system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 20826246000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses -system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses +system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency +system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses +system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.999731 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 606722925 # number of overall hits -system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses -system.cpu.dcache.overall_misses 505257 # number of overall misses +system.cpu.dcache.overall_hits 606786134 # number of overall hits +system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses +system.cpu.dcache.overall_misses 442048 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 437952 # number of replacements system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 306200 # number of writebacks +system.cpu.dcache.writebacks 396372 # number of writebacks system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -105,8 +105,8 @@ system.cpu.icache.demand_mshr_misses 722 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.322357 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency @@ -124,7 +124,7 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use +system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks @@ -132,37 +132,28 @@ system.cpu.idle_fraction 0 # Pe system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -171,44 +162,44 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.057043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.494010 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 177813 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 264957 # number of overall misses +system.cpu.l2cache.overall_hits 353302 # number of overall hits +system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 89468 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 81078 # number of replacements -system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 71208 # number of replacements +system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use -system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use +system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61253 # number of writebacks +system.cpu.l2cache.writebacks 58007 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3628211240 # number of cpu cycles simulated +system.cpu.numCycles 3606517174 # number of cpu cycles simulated system.cpu.num_insts 1619366787 # Number of instructions executed system.cpu.num_refs 607228182 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls |