diff options
| author | Kevin Lim <ktlim@umich.edu> | 2007-04-15 22:29:37 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2007-04-15 22:29:37 -0400 |
| commit | 733a57d45a6a99a6259bff979ac7e40e5231f84f (patch) | |
| tree | d4b44f2feab3aecf667ae034472dd3e5d2e94091 /tests/long/00.gzip | |
| parent | 64b4572c3ea103a274fd125dff66cdaafd20178b (diff) | |
| download | gem5-733a57d45a6a99a6259bff979ac7e40e5231f84f.tar.xz | |
Update long test refs.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr:
Update refs.
--HG--
extra : convert_revision : 19483a5a18e76338a3208a58d7460a922377acd3
Diffstat (limited to 'tests/long/00.gzip')
4 files changed, 287 insertions, 365 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index fa5ac1725..853e93096 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -70,6 +29,7 @@ commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -155,7 +115,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -331,7 +291,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -388,7 +348,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= euid=100 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 8744b6907..e04428224 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -31,7 +28,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -173,6 +170,7 @@ type=DerivO3CPU clock=1 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -253,7 +251,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -291,7 +289,7 @@ assoc=2 block_size=64 latency=1 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -367,39 +365,3 @@ clock=1000 width=64 responder_set=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 8303336ed..78a2b3f52 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 97621780 # Number of BTB hits -global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups -global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted -global.BPredUnit.lookups 108029652 # Number of BP lookups -global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. -host_inst_rate 64442 # Simulator instruction rate (inst/s) -host_mem_usage 296420 # Number of bytes of host memory used -host_seconds 8776.17 # Real time elapsed on the host -host_tick_rate 192322 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 71631614 # Number of BTB hits +global.BPredUnit.BTBLookups 80215513 # Number of BTB lookups +global.BPredUnit.RASInCorrect 194 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4366377 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 76991765 # Number of conditional branches predicted +global.BPredUnit.lookups 83232960 # Number of BP lookups +global.BPredUnit.usedRAS 1776050 # Number of times the RAS was used to get a target. +host_inst_rate 91613 # Simulator instruction rate (inst/s) +host_mem_usage 151676 # Number of bytes of host memory used +host_seconds 6173.25 # Real time elapsed on the host +host_tick_rate 271486 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 26015543 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 23632204 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 134244919 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 44983310 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.001688 # Number of seconds simulated -sim_ticks 1687849017 # Number of ticks simulated +sim_seconds 0.001676 # Number of seconds simulated +sim_ticks 1675949017 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 16353031 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 701581491 +system.cpu.commit.COM:committed_per_cycle.samples 801372491 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 480309675 6846.10% - 1 104094392 1483.71% - 2 40244499 573.63% - 3 11990473 170.91% - 4 15113210 215.42% - 5 17360338 247.45% - 6 10367558 147.77% - 7 4968492 70.82% - 8 17132854 244.20% + 0 580782547 7247.35% + 1 101892793 1271.48% + 2 41339172 515.85% + 3 11939444 148.99% + 4 15719123 196.15% + 5 17754998 221.56% + 6 10147917 126.63% + 7 5443466 67.93% + 8 16353031 204.06% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4365734 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 90079827 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses +system.cpu.cpi 2.963384 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.963384 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 120253770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3927.286441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3434.366579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 119156440 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4309529230 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.009125 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1097330 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 872988 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 770472667 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001866 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 224342 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 9089.303046 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9344.661839 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37503702 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 17702499310 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.049368 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1947619 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1690762 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2400241806 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006511 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 256857 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 327.941025 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3498.764706 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 325.562069 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 3493 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 1145498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 59479 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency -system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 159705091 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7229.030286 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency +system.cpu.dcache.demand_hits 156660142 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 22012028540 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019066 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3044949 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2563750 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3170714473 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003013 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 481199 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 159705091 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7229.030286 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 152421092 # number of overall hits -system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1949244 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses +system.cpu.dcache.overall_hits 156660142 # number of overall hits +system.cpu.dcache.overall_miss_latency 22012028540 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019066 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3044949 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2563750 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3170714473 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003013 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 481199 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 476534 # number of replacements -system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 477103 # number of replacements +system.cpu.dcache.sampled_refs 481199 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use -system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 337990 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched -system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4063.174314 # Cycle average of tags in use +system.cpu.dcache.total_refs 156660142 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 20910000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338217 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 515310439 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 681 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4340917 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 740208637 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 161139948 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 116871564 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 14453620 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 2001 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 8050541 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 83232960 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 72135284 # Number of cache lines fetched +system.cpu.fetch.Cycles 198811102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1485258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 751818937 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5990379 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.102023 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 72135284 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 73407664 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.921543 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 755178522 +system.cpu.fetch.rateDist.samples 815826112 system.cpu.fetch.rateDist.min_value 0 - 0 512314112 6784.01% - 1 11453310 151.66% - 2 16801464 222.48% - 3 16318450 216.09% - 4 18767749 248.52% - 5 15201778 201.30% - 6 32935567 436.13% - 7 7297838 96.64% - 8 124088254 1643.16% + 0 689150299 8447.27% + 1 10579353 129.68% + 2 12110332 148.44% + 3 11560507 141.70% + 4 9007686 110.41% + 5 3425511 41.99% + 6 3768928 46.20% + 7 3222436 39.50% + 8 73001060 894.81% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 72135284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5699.600162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4917.297556 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 72134046 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7056105 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1238 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4627177 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3783 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 76656.797024 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 3783 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency -system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 72135284 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5699.600162 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency +system.cpu.icache.demand_hits 72134046 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7056105 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000017 # miss rate for demand accesses +system.cpu.icache.demand_misses 1238 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 297 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4627177 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency +system.cpu.icache.overall_accesses 72135284 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5699.600162 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 167526954 # number of overall hits -system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1230 # number of overall misses -system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses +system.cpu.icache.overall_hits 72134046 # number of overall hits +system.cpu.icache.overall_miss_latency 7056105 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000017 # miss rate for overall accesses +system.cpu.icache.overall_misses 1238 # number of overall misses +system.cpu.icache.overall_mshr_hits 297 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4627177 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,63 +215,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 47 # number of replacements -system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.replacements 44 # number of replacements +system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use -system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 749.515669 # Cycle average of tags in use +system.cpu.icache.total_refs 72134046 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 92484798 # Number of branches executed -system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate -system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 51400640 # Number of stores executed +system.cpu.idleCycles 860122906 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67691806 # Number of branches executed +system.cpu.iew.EXEC:nop 43795429 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.748142 # Inst execution rate +system.cpu.iew.EXEC:refs 168635664 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41396142 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value -system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back +system.cpu.iew.WB:consumers 508232399 # num instructions consuming a value +system.cpu.iew.WB:count 603225060 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.792920 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 394011709 # num instructions producing a value -system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle -system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions +system.cpu.iew.WB:producers 402987686 # num instructions producing a value +system.cpu.iew.WB:rate 0.739404 # insts written-back per cycle +system.cpu.iew.WB:sent 604785539 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4695315 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 442855270 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 134244919 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 5961708 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 44983310 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 691933738 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 127239522 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6754480 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 610353566 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 42801 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 120734 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 14453620 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 431168 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 1871526 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 4575118 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24838 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1001889 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5578 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 19195409 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 5170787 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1001889 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 542024 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4153291 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.337452 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.337452 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 617108046 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 496182294 65.92% # Type of FU issued - IntMult 8208 0.00% # Type of FU issued + IntAlu 445691749 72.22% # Type of FU issued + IntMult 6563 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 33 0.00% # Type of FU issued FloatCmp 6 0.00% # Type of FU issued @@ -279,16 +279,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 5 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 204178453 27.13% # Type of FU issued - MemWrite 52346873 6.95% # Type of FU issued + MemRead 129192933 20.94% # Type of FU issued + MemWrite 42216752 6.84% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3402065 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005513 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 2723724 78.58% # attempts to use FU when none available + IntAlu 2626203 77.19% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 683243 19.71% # attempts to use FU when none available - MemWrite 59353 1.71% # attempts to use FU when none available + MemRead 644339 18.94% # attempts to use FU when none available + MemWrite 131523 3.87% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522 +system.cpu.iq.ISSUE:issued_per_cycle.samples 815826112 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 450030250 5959.26% - 1 91846319 1216.22% - 2 83470092 1105.30% - 3 53962116 714.56% - 4 57175468 757.11% - 5 10089384 133.60% - 6 7448894 98.64% - 7 1047122 13.87% - 8 108877 1.44% + 0 553114491 6779.81% + 1 85371128 1046.44% + 2 77782451 953.42% + 3 52154516 639.28% + 4 28098332 344.42% + 5 10103046 123.84% + 6 7930576 97.21% + 7 956122 11.72% + 8 315450 3.87% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate -system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.756421 # Inst issue rate +system.cpu.iq.iqInstsAdded 648138284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 617108046 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 80438129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1088392 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits +system.cpu.iq.iqSquashedOperandsExamined 57507029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 482140 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 8078.944187 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.998861 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455802 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 212783232 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054627 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26338 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 62263002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054627 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26338 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338217 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338217 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.147278 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 482140 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 8078.944187 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455802 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 212783232 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054627 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26338 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 62263002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26338 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 820357 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 8078.944187 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 793226 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26319 # number of overall misses +system.cpu.l2cache.overall_hits 794019 # number of overall hits +system.cpu.l2cache.overall_miss_latency 212783232 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032106 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26338 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 62263002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032106 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26338 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,32 +382,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 934 # number of replacements -system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 935 # number of replacements +system.cpu.l2cache.sampled_refs 26338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 24391.955858 # Cycle average of tags in use +system.cpu.l2cache.total_refs 794019 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 907 # number of writebacks -system.cpu.numCycles 755178522 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 908 # number of writebacks +system.cpu.numCycles 815826112 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 467231804 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IQFullEvents 38638370 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 170863189 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8553533 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 36121 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 961623776 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 729244091 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 554812455 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115192044 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 14453620 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 48042805 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 90957566 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 42650 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 77555696 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 308219 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. |