diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
| -rw-r--r-- | tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 956 |
1 files changed, 479 insertions, 477 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 75071ea91..6ec7aca0a 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,447 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86499 # Simulator instruction rate (inst/s) -host_mem_usage 277924 # Number of bytes of host memory used -host_seconds 613.76 # Real time elapsed on the host -host_tick_rate 3042478511 # Simulator tick rate (ticks/s) +host_inst_rate 154746 # Simulator instruction rate (inst/s) +host_mem_usage 291744 # Number of bytes of host memory used +host_seconds 343.04 # Real time elapsed on the host +host_tick_rate 5443609822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53090223 # Number of instructions simulated -sim_seconds 1.867363 # Number of seconds simulated -sim_ticks 1867362977500 # Number of ticks simulated +sim_insts 53083414 # Number of instructions simulated +sim_seconds 1.867360 # Number of seconds simulated +sim_ticks 1867360295500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461925 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6774596 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12988394 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41867 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 814870 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12133144 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14563531 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1033178 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461193 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 999873 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.559325 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.322901 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 76387036 75.91% 75.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 10760374 10.69% 86.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5981089 5.94% 92.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 2990150 2.97% 95.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2079430 2.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 662647 0.66% 98.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 398739 0.40% 98.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 391912 0.39% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 978098 0.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 76371825 75.99% 75.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 10652369 10.60% 86.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5995069 5.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 2948172 2.93% 95.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2094039 2.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 649751 0.65% 98.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 415244 0.41% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 382142 0.38% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:count 56284559 # Number of instructions committed -system.cpu.commit.COM:loads 9308572 # Number of loads committed -system.cpu.commit.COM:membars 228000 # Number of memory barriers committed -system.cpu.commit.COM:refs 15700770 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:count 56277376 # Number of instructions committed +system.cpu.commit.COM:loads 9307406 # Number of loads committed +system.cpu.commit.COM:membars 227986 # Number of memory barriers committed +system.cpu.commit.COM:refs 15698987 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53090223 # Number of Instructions Simulated -system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated -system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 773341 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56277376 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667767 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9507253 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53083414 # Number of Instructions Simulated +system.cpu.committedInsts_total 53083414 # Number of Instructions Simulated +system.cpu.cpi 2.579204 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.579204 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.595548 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.625753 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 345718500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103721 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4847 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205988000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081158 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17435 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23910.895806 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22793.768876 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36690361000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.164206 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 450067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24717449000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116043 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084395 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904961500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.344016 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.344016 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689238000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.136420 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599277000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136420 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 29987 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 49095.565499 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54537.318055 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109486695038 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.362224 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21611393951 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064365 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 137083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 396268 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235673497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9968.474051 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.834980 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 138443 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1380065453 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15501348 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15501348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11736813 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11736813 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 146177056038 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.242852 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3764535 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3764535 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2283872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46328842951 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095518 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1480663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995450 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15499631 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::1 -0.019112 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995421 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -9.785268 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15501348 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15499631 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15501348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11736725 # number of overall hits +system.cpu.dcache.overall_hits::0 11736813 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11736725 # number of overall hits -system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.242774 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11736813 # number of overall hits +system.cpu.dcache.overall_miss_latency 146177056038 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.242852 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3762906 # number of overall misses +system.cpu.dcache.overall_misses::0 3764535 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3762906 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3764535 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2283872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46328842951 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095518 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1480663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140634997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1402110 # number of replacements -system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401152 # number of replacements +system.cpu.dcache.sampled_refs 1401664 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use -system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430447 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236133 # DTB accesses +system.cpu.dcache.tagsinuse 507.102797 # Cycle average of tags in use +system.cpu.dcache.total_refs 12383673 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430200 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48440098 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42540 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 615090 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72709786 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37935584 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12980555 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1639247 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 136073 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1152246 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1232975 # DTB accesses system.cpu.dtb.data_acv 823 # DTB access violations -system.cpu.dtb.data_hits 16770289 # DTB hits -system.cpu.dtb.data_misses 44393 # DTB misses +system.cpu.dtb.data_hits 16785642 # DTB hits +system.cpu.dtb.data_misses 44486 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 909859 # DTB read accesses -system.cpu.dtb.read_acv 588 # DTB read access violations -system.cpu.dtb.read_hits 10173052 # DTB read hits -system.cpu.dtb.read_misses 36219 # DTB read misses -system.cpu.dtb.write_accesses 326274 # DTB write accesses -system.cpu.dtb.write_acv 235 # DTB write access violations -system.cpu.dtb.write_hits 6597237 # DTB write hits -system.cpu.dtb.write_misses 8174 # DTB write misses -system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched -system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.726149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.019798 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 911401 # DTB read accesses +system.cpu.dtb.read_acv 582 # DTB read access violations +system.cpu.dtb.read_hits 10188595 # DTB read hits +system.cpu.dtb.read_misses 36193 # DTB read misses +system.cpu.dtb.write_accesses 321574 # DTB write accesses +system.cpu.dtb.write_acv 241 # DTB write access violations +system.cpu.dtb.write_hits 6597047 # DTB write hits +system.cpu.dtb.write_misses 8293 # DTB write misses +system.cpu.fetch.Branches 14563531 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8983923 # Number of cache lines fetched +system.cpu.fetch.Cycles 23375540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455206 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74277236 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 956999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106371 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8983923 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7807774 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542514 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 87829962 85.88% 85.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1051726 1.03% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2021481 1.98% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 968950 0.95% 89.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 2998384 2.93% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 688876 0.67% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 831559 0.81% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1217734 1.19% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4664036 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14917.128866 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116430 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.331981 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15609939999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.116480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 50514 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11860861000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110857 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 995930 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 10883.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.971412 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 653000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8983923 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8997144 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.demand_accesses::total 8983923 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7937479 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7949609 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116430 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7937479 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15609939999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.116480 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1046444 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1047535 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1046444 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 50514 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11860861000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.110857 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 995930 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995649 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.772438 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8997144 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995671 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.783438 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8983923 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8997144 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.overall_accesses::total 8983923 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7949609 # number of overall hits +system.cpu.icache.overall_hits::0 7937479 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7949609 # number of overall hits -system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116430 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7937479 # number of overall hits +system.cpu.icache.overall_miss_latency 15609939999 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.116480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1047535 # number of overall misses +system.cpu.icache.overall_misses::0 1046444 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1047535 # number of overall misses -system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1046444 # number of overall misses +system.cpu.icache.overall_mshr_hits 50514 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11860861000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.110857 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 995930 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 994957 # number of replacements -system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks. +system.cpu.icache.replacements 995232 # number of replacements +system.cpu.icache.sampled_refs 995743 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use -system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 509.783438 # Cycle average of tags in use +system.cpu.icache.total_refs 7937478 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25287643000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9164165 # Number of branches executed -system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate -system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6620337 # Number of stores executed +system.cpu.idleCycles 34765240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9170733 # Number of branches executed +system.cpu.iew.EXEC:nop 3662671 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420879 # Inst execution rate +system.cpu.iew.EXEC:refs 17068903 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6620272 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value -system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back +system.cpu.iew.WB:consumers 34614422 # num instructions consuming a value +system.cpu.iew.WB:count 57031603 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763117 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26380221 # num instructions producing a value -system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle -system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26414846 # num instructions producing a value +system.cpu.iew.WB:rate 0.416554 # insts written-back per cycle +system.cpu.iew.WB:sent 57130351 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 839771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9768928 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11058875 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1801420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1004974 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7015626 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65914650 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10448631 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 528111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57623776 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 52093 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6603 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1639247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554420 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 311339 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 434411 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10284 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7284 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39611417 68.15% 68.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62110 0.11% 68.27% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 46318 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 18429 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1751469 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 624045 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46318 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 408059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431712 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39633385 68.15% 68.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62109 0.11% 68.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10788116 18.56% 86.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6673339 11.48% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953263 1.64% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10799740 18.57% 86.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6666948 11.46% 98.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953172 1.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58124772 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 58151889 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 434913 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007479 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 50716 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 279321 64.50% 76.21% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 103014 23.79% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 52889 12.16% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 280249 64.44% 76.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 101775 23.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% 71.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% 85.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% 92.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% 95.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% 98.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% 99.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73060847 71.52% 71.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14641510 14.33% 85.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6377407 6.24% 92.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3918998 3.84% 95.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2506307 2.45% 98.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1046173 1.02% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 456673 0.45% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 116088 0.11% 99.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate -system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.424736 # Inst issue rate +system.cpu.iq.iqInstsAdded 60199205 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58151889 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2052774 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8775393 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1385007 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4703772 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1303750 # ITB accesses -system.cpu.itb.fetch_acv 951 # ITB acv -system.cpu.itb.fetch_hits 1264322 # ITB hits -system.cpu.itb.fetch_misses 39428 # ITB misses +system.cpu.itb.fetch_accesses 1302209 # ITB accesses +system.cpu.itb.fetch_acv 948 # ITB acv +system.cpu.itb.fetch_hits 1264828 # ITB hits +system.cpu.itb.fetch_misses 37381 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -457,51 +459,51 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175681 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175662 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192652 # number of callpals executed +system.cpu.kern.callpal::total 192631 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211789 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74950 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105947 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183030 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105933 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183009 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73583 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149305 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 102621000 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392338000 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867362103000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73583 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149292 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824774879500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 102464000 0.01% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392165500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42089912000 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867359421000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981761 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694583 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.ipl_used::31 0.694618 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5972 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5971 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319826 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320047 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3191204500 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 1.401192 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31307096500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3189085000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832863231500 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -534,29 +536,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136997789 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed -system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3116609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2798105 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11058875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7015626 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136912971 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14296513 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38253474 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1101619 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39527204 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2223744 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15702 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83467187 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68675679 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46041377 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12627654 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1639247 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5214289 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7787901 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28842822 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704528 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12805525 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256634 # count of temporary serializing insts renamed +system.cpu.timesIdled 1324969 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -572,14 +574,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -587,37 +589,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137793.747738 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85790.377840 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725605806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3564761780 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6164.456543 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10470 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64541860 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745548804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -625,7 +627,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3575708778 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -633,20 +635,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.079213 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.267415 # Average occupied blocks per context +system.iocache.occ_%::1 0.079211 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.267376 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745548804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -654,7 +656,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3575708778 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -664,137 +666,137 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267415 # Cycle average of tags in use +system.iocache.tagsinuse 1.267376 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716180121000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52374.719501 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.943752 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739179332 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 300582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 300582 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses::0 300511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 300511 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12085934495 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.745492 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 300511 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52047.601080 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.046370 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1785718 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785718 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16208195500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.148494 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 311411 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311411 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12461397000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.148493 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52274.462658 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.358873 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6800698494 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5216506000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130096 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430447 # number of Writeback hits -system.l2c.Writeback_hits::total 430447 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430200 # number of Writeback hits +system.l2c.Writeback_hits::total 430200 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. +system.l2c.avg_refs 4.595902 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2397640 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.demand_accesses::total 2397640 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency -system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency +system.l2c.demand_hits::0 1785718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses +system.l2c.demand_hits::total 1785718 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31947374832 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.255218 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 611735 # number of demand (read+write) misses +system.l2c.demand_misses::0 611922 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 611735 # number of demand (read+write) misses +system.l2c.demand_misses::total 611922 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24547331495 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.255218 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 611921 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context -system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context -system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.090196 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.378860 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5911.076462 # Average occupied blocks per context +system.l2c.occ_blocks::1 24828.993432 # Average occupied blocks per context +system.l2c.overall_accesses::0 2397640 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.overall_accesses::total 2397640 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1786590 # number of overall hits +system.l2c.overall_hits::0 1785718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1786590 # number of overall hits -system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses +system.l2c.overall_hits::total 1785718 # number of overall hits +system.l2c.overall_miss_latency 31947374832 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.255218 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 611735 # number of overall misses +system.l2c.overall_misses::0 611922 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 611735 # number of overall misses +system.l2c.overall_misses::total 611922 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24547331495 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.255218 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 611921 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926647998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396039 # number of replacements -system.l2c.sampled_refs 427720 # Sample count of references to valid blocks. +system.l2c.replacements 396067 # number of replacements +system.l2c.sampled_refs 427735 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use -system.l2c.total_refs 1966597 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119094 # number of writebacks +system.l2c.tagsinuse 30740.069893 # Cycle average of tags in use +system.l2c.total_refs 1965828 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645113000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119080 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |