diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:08 -0500 |
| commit | 999cd8aef5dfa3c22b02b55420608fbb8d7e7822 (patch) | |
| tree | 98f11453678ed2be66b2ae3239b0ee42ad6f4e05 /tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | |
| parent | b94f84196924d60d4d4677929ddb6f677e3d96d9 (diff) | |
| download | gem5-999cd8aef5dfa3c22b02b55420608fbb8d7e7822.tar.xz | |
StoreSet: Update stats for store-set clearing
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt')
| -rw-r--r-- | tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1078 |
1 files changed, 539 insertions, 539 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index eab7f5386..c17b9a135 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858709 # Number of seconds simulated -sim_ticks 1858708914500 # Number of ticks simulated +sim_seconds 1.857897 # Number of seconds simulated +sim_ticks 1857897393500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124964 # Simulator instruction rate (inst/s) -host_tick_rate 4374927606 # Simulator tick rate (ticks/s) -host_mem_usage 340632 # Number of bytes of host memory used -host_seconds 424.85 # Real time elapsed on the host -sim_insts 53091761 # Number of instructions simulated -system.l2c.replacements 391302 # number of replacements -system.l2c.tagsinuse 34944.632545 # Cycle average of tags in use -system.l2c.total_refs 2405534 # Total number of references to valid blocks. -system.l2c.sampled_refs 424233 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.670313 # Average number of references to valid blocks. +host_inst_rate 111366 # Simulator instruction rate (inst/s) +host_tick_rate 3896929552 # Simulator tick rate (ticks/s) +host_mem_usage 340840 # Number of bytes of host memory used +host_seconds 476.76 # Real time elapsed on the host +sim_insts 53094627 # Number of instructions simulated +system.l2c.replacements 391325 # number of replacements +system.l2c.tagsinuse 34942.141711 # Cycle average of tags in use +system.l2c.total_refs 2407783 # Total number of references to valid blocks. +system.l2c.sampled_refs 424213 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.675882 # Average number of references to valid blocks. system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12322.596332 # Average occupied blocks per context -system.l2c.occ_blocks::1 22622.036213 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188028 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345185 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801216 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801216 # number of ReadReq hits -system.l2c.Writeback_hits::0 835065 # number of Writeback hits -system.l2c.Writeback_hits::total 835065 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits +system.l2c.occ_blocks::0 12320.874417 # Average occupied blocks per context +system.l2c.occ_blocks::1 22621.267294 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188002 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.345173 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1800422 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1800422 # number of ReadReq hits +system.l2c.Writeback_hits::0 834998 # number of Writeback hits +system.l2c.Writeback_hits::total 834998 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183191 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183191 # number of ReadExReq hits -system.l2c.demand_hits::0 1984407 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183185 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183185 # number of ReadExReq hits +system.l2c.demand_hits::0 1983607 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984407 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984407 # number of overall hits +system.l2c.demand_hits::total 1983607 # number of demand (read+write) hits +system.l2c.overall_hits::0 1983607 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1984407 # number of overall hits -system.l2c.ReadReq_misses::0 308126 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308126 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116919 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116919 # number of ReadExReq misses -system.l2c.demand_misses::0 425045 # number of demand (read+write) misses +system.l2c.overall_hits::total 1983607 # number of overall hits +system.l2c.ReadReq_misses::0 308136 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308136 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 36 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116850 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116850 # number of ReadExReq misses +system.l2c.demand_misses::0 424986 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 425045 # number of demand (read+write) misses -system.l2c.overall_misses::0 425045 # number of overall misses +system.l2c.demand_misses::total 424986 # number of demand (read+write) misses +system.l2c.overall_misses::0 424986 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 425045 # number of overall misses -system.l2c.ReadReq_miss_latency 16035962500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 424986 # number of overall misses +system.l2c.ReadReq_miss_latency 16038372500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6137530000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22173492500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22173492500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2109342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109342 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835065 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835065 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 44 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency 6129219000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22167591500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22167591500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2108558 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108558 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 834998 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 834998 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300110 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300110 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409452 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300035 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300035 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2408593 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409452 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409452 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2408593 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2408593 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409452 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146077 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.704545 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389587 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176407 # miss rate for demand accesses +system.l2c.overall_accesses::total 2408593 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146136 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.692308 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389455 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176446 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176407 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176446 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52043.522780 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52049.655022 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 13709.677419 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 11805.555556 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52493.863273 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52453.735558 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52167.399922 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52160.757060 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52167.399922 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52160.757060 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117722 # number of writebacks +system.l2c.writebacks 117715 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308126 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116919 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425045 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425045 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308136 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116850 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 424986 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 424986 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12333217500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4715307000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17048524500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17048524500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 809593500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1114721998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1924315498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146077 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12334391000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1500000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4708487500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17042878500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17042878500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810033000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115131998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925164998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146136 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.704545 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.692308 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389587 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389455 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176407 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176446 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176407 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176446 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40026.539468 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40329.689785 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40029.048862 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41666.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40295.143346 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266801 # Cycle average of tags in use +system.iocache.tagsinuse 1.260372 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338851000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.266801 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079175 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338825000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.260372 # Average occupied blocks per context +system.iocache.occ_percent::1 0.078773 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -167,9 +167,9 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722275806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742213804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742213804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency 5722330806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742268804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742268804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -192,19 +192,19 @@ system.iocache.ReadReq_avg_miss_latency::0 inf # system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137713.607191 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137714.930834 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137620.462648 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137621.780803 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137620.462648 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137621.780803 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64594068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64585068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6170.621704 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6173.300325 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -217,9 +217,9 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561421998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572363996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572363996 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561477996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572419994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572419994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -234,9 +234,9 @@ system.iocache.overall_mshr_miss_rate::0 inf # ms system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85710.001877 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85711.349538 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10154080 # DTB read hits -system.cpu.dtb.read_misses 43144 # DTB read misses -system.cpu.dtb.read_acv 557 # DTB read access violations -system.cpu.dtb.read_accesses 952445 # DTB read accesses -system.cpu.dtb.write_hits 6614848 # DTB write hits -system.cpu.dtb.write_misses 9467 # DTB write misses -system.cpu.dtb.write_acv 320 # DTB write access violations -system.cpu.dtb.write_accesses 334339 # DTB write accesses -system.cpu.dtb.data_hits 16768928 # DTB hits -system.cpu.dtb.data_misses 52611 # DTB misses -system.cpu.dtb.data_acv 877 # DTB access violations -system.cpu.dtb.data_accesses 1286784 # DTB accesses -system.cpu.itb.fetch_hits 1336327 # ITB hits -system.cpu.itb.fetch_misses 39787 # ITB misses -system.cpu.itb.fetch_acv 1065 # ITB acv -system.cpu.itb.fetch_accesses 1376114 # ITB accesses +system.cpu.dtb.read_hits 10156439 # DTB read hits +system.cpu.dtb.read_misses 47122 # DTB read misses +system.cpu.dtb.read_acv 587 # DTB read access violations +system.cpu.dtb.read_accesses 977122 # DTB read accesses +system.cpu.dtb.write_hits 6633598 # DTB write hits +system.cpu.dtb.write_misses 11598 # DTB write misses +system.cpu.dtb.write_acv 414 # DTB write access violations +system.cpu.dtb.write_accesses 348122 # DTB write accesses +system.cpu.dtb.data_hits 16790037 # DTB hits +system.cpu.dtb.data_misses 58720 # DTB misses +system.cpu.dtb.data_acv 1001 # DTB access violations +system.cpu.dtb.data_accesses 1325244 # DTB accesses +system.cpu.itb.fetch_hits 1333506 # ITB hits +system.cpu.itb.fetch_misses 39875 # ITB misses +system.cpu.itb.fetch_acv 1125 # ITB acv +system.cpu.itb.fetch_accesses 1373381 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,275 +285,275 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 117237485 # number of cpu cycles simulated +system.cpu.numCycles 116343633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14455551 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12084424 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 532367 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13050115 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6745735 # Number of BTB hits +system.cpu.BPredUnit.lookups 14429393 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12066685 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 532769 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13006399 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6718907 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 978348 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45278 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29236023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74164805 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14455551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7724083 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14385478 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2439202 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37224537 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 262840 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335923 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9135306 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 83080083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.209867 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 975114 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45137 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29132882 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73870037 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14429393 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7694021 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14329837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2400358 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36580859 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259840 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335514 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9103703 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330872 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82240103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898224 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.215946 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68694605 82.68% 82.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1023953 1.23% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2033478 2.45% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 975932 1.17% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2976777 3.58% 91.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 700548 0.84% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 794915 0.96% 92.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1072238 1.29% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4807637 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67910266 82.58% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1028745 1.25% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2026192 2.46% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 969086 1.18% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2957231 3.60% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 692695 0.84% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 793723 0.97% 92.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070407 1.30% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4791758 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 83080083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123301 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632603 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30551542 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36838313 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13095678 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1034253 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1560296 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 613869 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42144 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72480994 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 127271 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1560296 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31800995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12812731 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19871114 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12262779 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4772166 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68475649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4094 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 996372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1464404 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45853535 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 83251938 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82772461 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479477 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38260770 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7592757 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700825 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251533 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12956852 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10812074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7051744 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2165147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2346616 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 60096918 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2117388 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58031681 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8738509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4816872 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1449642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 83080083 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.311149 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82240103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124024 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.634930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30393620 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36243117 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13115942 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 960226 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1527197 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 611480 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42119 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72202344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128169 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1527197 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31599738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12790599 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19770106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12256569 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4295892 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68223425 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6893 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 500375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1520799 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45688467 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82930883 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82451857 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479026 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38262876 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7425583 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700626 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251543 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12011289 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10748783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7011270 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1273745 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 840870 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59873388 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116185 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58064745 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115927 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8494287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4438181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1448436 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82240103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.706039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.353017 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56639169 68.17% 68.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11994103 14.44% 82.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5929931 7.14% 89.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3560683 4.29% 94.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2591551 3.12% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1336446 1.61% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 797054 0.96% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184259 0.22% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 46887 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56753994 69.01% 69.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11193552 13.61% 82.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5499635 6.69% 89.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3512602 4.27% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2643529 3.21% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1548822 1.88% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 707324 0.86% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 273213 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107432 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 83080083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82240103 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68783 12.83% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 305726 57.04% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161454 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64991 8.48% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 378109 49.32% 57.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323577 42.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39661101 68.34% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62145 0.11% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25610 0.04% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10623971 18.31% 86.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6695582 11.54% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952355 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39655118 68.29% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62174 0.11% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10635929 18.32% 86.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722688 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952312 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58031681 # Type of FU issued -system.cpu.iq.rate 0.494993 # Inst issue rate -system.cpu.iq.fu_busy_cnt 535963 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009236 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 199072460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 70641414 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56449878 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 689765 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 333951 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328040 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58199260 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361103 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 552721 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 58064745 # Type of FU issued +system.cpu.iq.rate 0.499080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 766677 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013204 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198560467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 70176120 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56485252 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 691729 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 332805 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328298 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58461376 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362765 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 576950 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1698615 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 23451 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 659180 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1635037 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13784 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26178 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 618376 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 200829 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18266 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170591 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1560296 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8872665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 625505 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65852816 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 871025 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10812074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7051744 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1870069 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 491565 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7470 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 23451 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 385257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383183 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 768440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57350351 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10227555 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 681329 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1527197 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8965647 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616674 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65615916 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 866303 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10748783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7011270 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1869859 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 484759 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15737 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26178 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 387398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 770562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57355078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10233934 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 709666 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3638510 # number of nop insts executed -system.cpu.iew.exec_refs 16867130 # number of memory reference insts executed -system.cpu.iew.exec_branches 9102477 # Number of branches executed -system.cpu.iew.exec_stores 6639575 # Number of stores executed -system.cpu.iew.exec_rate 0.489181 # Inst execution rate -system.cpu.iew.wb_sent 56909286 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56777918 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28083144 # num instructions producing a value -system.cpu.iew.wb_consumers 37838196 # num instructions consuming a value +system.cpu.iew.exec_nop 3626343 # number of nop insts executed +system.cpu.iew.exec_refs 16894519 # number of memory reference insts executed +system.cpu.iew.exec_branches 9105401 # Number of branches executed +system.cpu.iew.exec_stores 6660585 # Number of stores executed +system.cpu.iew.exec_rate 0.492980 # Inst execution rate +system.cpu.iew.wb_sent 56953037 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56813550 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28082126 # num instructions producing a value +system.cpu.iew.wb_consumers 37827297 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.484298 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742190 # average fanout of values written-back +system.cpu.iew.wb_rate 0.488325 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742377 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56286421 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9443080 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667746 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 702134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 81519787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.690463 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.566765 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56289333 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9199733 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667749 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 702560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80712906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.610815 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59658965 73.18% 73.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9249179 11.35% 84.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5213125 6.39% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2451549 3.01% 93.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1701758 2.09% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 617367 0.76% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 434350 0.53% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 791574 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1401920 1.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59526212 73.75% 73.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8907000 11.04% 84.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4712189 5.84% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2603041 3.23% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533921 1.90% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 653559 0.81% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475046 0.59% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 520427 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1781511 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 81519787 # Number of insts commited each cycle -system.cpu.commit.count 56286421 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80712906 # Number of insts commited each cycle +system.cpu.commit.count 56289333 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506023 # Number of memory references committed -system.cpu.commit.loads 9113459 # Number of loads committed -system.cpu.commit.membars 227879 # Number of memory barriers committed -system.cpu.commit.branches 8462155 # Number of branches committed +system.cpu.commit.refs 15506640 # Number of memory references committed +system.cpu.commit.loads 9113746 # Number of loads committed +system.cpu.commit.membars 227885 # Number of memory barriers committed +system.cpu.commit.branches 8462674 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52124782 # Number of committed integer instructions. -system.cpu.commit.function_calls 744514 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1401920 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52127663 # Number of committed integer instructions. +system.cpu.commit.function_calls 744579 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1781511 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 145596309 # The number of ROB reads -system.cpu.rob.rob_writes 133022104 # The number of ROB writes -system.cpu.timesIdled 1258228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34157402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53091761 # Number of Instructions Simulated -system.cpu.committedInsts_total 53091761 # Number of Instructions Simulated -system.cpu.cpi 2.208205 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.208205 # CPI: Total CPI of All Threads -system.cpu.ipc 0.452857 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.452857 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75150720 # number of integer regfile reads -system.cpu.int_regfile_writes 41017067 # number of integer regfile writes -system.cpu.fp_regfile_reads 166113 # number of floating regfile reads -system.cpu.fp_regfile_writes 167453 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996494 # number of misc regfile reads -system.cpu.misc_regfile_writes 949911 # number of misc regfile writes +system.cpu.rob.rob_reads 144169402 # The number of ROB reads +system.cpu.rob.rob_writes 132508314 # The number of ROB writes +system.cpu.timesIdled 1255085 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34103530 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53094627 # Number of Instructions Simulated +system.cpu.committedInsts_total 53094627 # Number of Instructions Simulated +system.cpu.cpi 2.191251 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.191251 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456360 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456360 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75184837 # number of integer regfile reads +system.cpu.int_regfile_writes 41033576 # number of integer regfile writes +system.cpu.fp_regfile_reads 166484 # number of floating regfile reads +system.cpu.fp_regfile_writes 167413 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996811 # number of misc regfile reads +system.cpu.misc_regfile_writes 949905 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1005090 # number of replacements -system.cpu.icache.tagsinuse 509.951538 # Cycle average of tags in use -system.cpu.icache.total_refs 8070754 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005599 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.025817 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23351335000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.951538 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995999 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8070755 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8070755 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8070755 # number of demand (read+write) hits +system.cpu.icache.replacements 1004633 # number of replacements +system.cpu.icache.tagsinuse 509.950442 # Cycle average of tags in use +system.cpu.icache.total_refs 8037423 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005142 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.996306 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23350341000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.950442 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8037424 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8037424 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8037424 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8070755 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8070755 # number of overall hits +system.cpu.icache.demand_hits::total 8037424 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8037424 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8070755 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1064551 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064551 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1064551 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8037424 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1066279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066279 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1066279 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064551 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1064551 # number of overall misses +system.cpu.icache.demand_misses::total 1066279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1066279 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1064551 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15926988994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15926988994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15926988994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9135306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9135306 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9135306 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1066279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15932595494 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15932595494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15932595494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9103703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9103703 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9103703 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9135306 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9135306 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9103703 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9103703 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9135306 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.116532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.116532 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9103703 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117126 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117126 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.116532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117126 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14961.226840 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14942.238846 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14961.226840 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14942.238846 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14961.226840 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14942.238846 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1261996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1325996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10516.633333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10607.968000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 232 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 58739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 58739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 58739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005812 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005812 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005812 # number of overall MSHR misses +system.cpu.icache.writebacks 235 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 60920 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60920 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60920 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005359 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005359 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12051659996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12051659996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12051659996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12047978496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12047978496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12047978496 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110102 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110434 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.110102 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.110434 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.110102 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.110434 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.020493 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.757539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403296 # number of replacements -system.cpu.dcache.tagsinuse 511.995990 # Cycle average of tags in use -system.cpu.dcache.total_refs 12128638 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.639813 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1402933 # number of replacements +system.cpu.dcache.tagsinuse 511.995988 # Cycle average of tags in use +system.cpu.dcache.total_refs 12110548 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403445 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.629158 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995990 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.995988 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7493448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7493448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4222901 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4222901 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192043 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192043 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220080 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220080 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11716349 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7476386 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7476386 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4221734 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4221734 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192117 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192117 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220089 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220089 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11698120 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11716349 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11716349 # number of overall hits +system.cpu.dcache.demand_hits::total 11698120 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11698120 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11716349 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1778869 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1778869 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1934444 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1934444 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 23262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23262 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11698120 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1807054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1807054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1935931 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1935931 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 22609 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22609 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3713313 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3742985 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3713313 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3713313 # number of overall misses +system.cpu.dcache.demand_misses::total 3742985 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3742985 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3713313 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38377192500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57331444318 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 363604000 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3742985 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38901669000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57798606480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 338580500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 95708636818 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 95708636818 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9272317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9272317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6157345 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157345 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 215305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220082 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15429662 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 96700275480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 96700275480 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9283440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9283440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6157665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 214726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220091 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220091 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15441105 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15429662 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15429662 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15441105 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15441105 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15429662 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.191847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314169 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15441105 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.194653 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314394 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105292 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.240661 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242404 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.240661 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21573.928434 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21527.673772 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29637.169294 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.716180 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15630.814203 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.474369 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25774.459847 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25835.068930 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25774.459847 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25835.068930 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 916364836 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 209000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 100291 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9137.059517 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23222.222222 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 919195309 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8982.218293 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834833 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 691203 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1635634 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5726 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2326837 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2326837 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087666 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298810 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17536 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834763 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 719698 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637137 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5136 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2356835 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2356835 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298794 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17473 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386476 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386150 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24813377000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8487477836 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207860000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24800644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8504282309 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206126500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33300854836 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33300854836 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904007000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234009498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138016498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117303 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33304926309 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33304926309 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904508000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234433998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138941998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048529 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048524 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081447 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081373 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089858 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089770 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089858 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089770 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22813.416067 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28404.263030 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11853.330292 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22808.210007 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28462.025037 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11796.858010 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -817,27 +817,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74884 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105815 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182822 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73517 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73519 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149159 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1820013648500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93762000 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384408000 0.02% 97.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38216235500 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858708054000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981745 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6435 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211583 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74879 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1881 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105809 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182812 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73512 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1881 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73515 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819252477000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94027000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384302500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38165726500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1857896533000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981744 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694788 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -876,8 +876,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175485 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6786 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed @@ -885,20 +885,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192443 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192432 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5954 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320349 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320289 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080914 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401263 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29483328500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2787065000 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826437652500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401126 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29181178000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2689752000 0.14% 1.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826025595000 98.28% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |