diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-09-21 23:07:35 -0700 |
| commit | 13a15c55a40e86e5f3948a387fb5e50b9a1cdccf (patch) | |
| tree | 762286677b3170cf9a7fb348f44e74a276230d6c /tests/long/10.linux-boot/ref/alpha/linux | |
| parent | e9185363804489ce2b84d50fe77ed94f3a5f1e01 (diff) | |
| download | gem5-13a15c55a40e86e5f3948a387fb5e50b9a1cdccf.tar.xz | |
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Diffstat (limited to 'tests/long/10.linux-boot/ref/alpha/linux')
6 files changed, 1521 insertions, 1529 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 1430c935e..14fd768c1 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,12 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -661,7 +661,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -681,7 +681,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -807,7 +807,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 592fcc28f..87e8bb8fc 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,14 +5,14 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 12:51:14 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:51:16 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:17:04 +M5 executing on phenom command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 125480500 -Exiting @ tick 1906675009500 because m5_exit instruction encountered +info: Launching CPU 1 @ 118370500 +Exiting @ tick 1900828642500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a77677815..a900ae38f 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,449 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 96877 # Simulator instruction rate (inst/s) -host_mem_usage 294552 # Number of bytes of host memory used -host_seconds 589.85 # Real time elapsed on the host -host_tick_rate 3232468675 # Simulator tick rate (ticks/s) +host_inst_rate 158375 # Simulator instruction rate (inst/s) +host_mem_usage 283016 # Number of bytes of host memory used +host_seconds 359.78 # Real time elapsed on the host +host_tick_rate 5283356726 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 57142904 # Number of instructions simulated -sim_seconds 1.906675 # Number of seconds simulated -sim_ticks 1906675009500 # Number of ticks simulated +sim_insts 56979511 # Number of instructions simulated +sim_seconds 1.900829 # Number of seconds simulated +sim_ticks 1900828642500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 6037320 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11351967 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27838 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 689824 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10583458 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12665096 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 889173 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7532122 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 868474 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5876227 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11175399 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27772 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 686228 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10431445 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12491766 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 881103 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7527502 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 920717 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 85531488 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.582160 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.346009 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 78591026 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.633671 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.400615 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 64118131 74.96% 74.96% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9419985 11.01% 85.98% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5464530 6.39% 92.37% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2511151 2.94% 95.30% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1836761 2.15% 97.45% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 609168 0.71% 98.16% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 353146 0.41% 98.58% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 350142 0.41% 98.98% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 868474 1.02% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 57312142 72.92% 72.92% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9330889 11.87% 84.80% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5427191 6.91% 91.70% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2440699 3.11% 94.81% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1862016 2.37% 97.18% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 630346 0.80% 97.98% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 341230 0.43% 98.41% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 325796 0.41% 98.83% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 920717 1.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 85531488 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49793044 # Number of instructions committed -system.cpu0.commit.COM:loads 8087035 # Number of loads committed -system.cpu0.commit.COM:membars 188923 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13499415 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 78591026 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49800850 # Number of instructions committed +system.cpu0.commit.COM:loads 8090667 # Number of loads committed +system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed +system.cpu0.commit.COM:refs 13515444 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 656667 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49793044 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 558254 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7909295 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46950766 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46950766 # Number of Instructions Simulated -system.cpu0.cpi 2.557983 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557983 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 175325 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 175325 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13891.838160 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 653618 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49800850 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 564747 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7272798 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46939821 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46939821 # Number of Instructions Simulated +system.cpu0.cpi 2.403302 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403302 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 178200 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 178200 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14347.227969 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10378.791946 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 156714 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156714 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 258541000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 18611 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18611 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3711 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 154644000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084985 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10538.474362 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 158864 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158864 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 277418000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108507 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 19336 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19336 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 4339 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158045500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084158 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 14900 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8024582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8024582 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 24823.193475 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 14997 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8021076 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8021076 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.144269 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23777.445948 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.790910 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6693712 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6693712 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 33036443500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.165849 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1330870 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1330870 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 349277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23339774500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122323 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6644033 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6644033 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 32707724000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.171678 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1377043 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1377043 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 391877 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23415219500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122822 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 981593 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922661000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 183239 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 183239 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 47093.631014 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 985166 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920846500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 185095 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185095 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13168.588688 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 44096.203773 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 165905 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 165905 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 816321000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.094598 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 17334 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 17334 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 764319500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.094592 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10165.293795 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 181453 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 181453 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 47960000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019676 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 3642 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3642 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37022000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019676 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 17333 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5213801 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5213801 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 48517.051427 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 3642 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5224623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5224623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32385.164412 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53069.050136 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30570.974366 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3350446 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3350446 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 90404490361 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.357389 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1863355 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1863355 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1547991 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 16736067927 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060486 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3608317 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3608317 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 52344335550 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.309363 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1616306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1616306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1352902 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 8052516932 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050416 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 315364 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1337193497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9713.605174 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.464502 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 124903 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 1213258427 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 129000 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 263404 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320254998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8777.270227 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21937.500000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 8.502455 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 83541 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 733261932 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 175500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13238383 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13245699 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13238383 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 38645.034041 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13245699 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28413.679644 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10044158 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 25203.021402 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10252350 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10044158 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 123440933861 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.241285 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10252350 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 85052059550 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.225986 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 3194225 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2993349 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3194225 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1897268 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 40075842427 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.097969 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2993349 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1744779 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 31467736432 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.094262 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1296957 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1248570 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.975170 # Average percentage of cache occupancy -system.cpu0.dcache.occ_%::1 -0.005787 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 499.286946 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -2.962988 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13238383 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.973042 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 498.197480 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 13245699 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13238383 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 38645.034041 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13245699 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28413.679644 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25203.021402 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10044158 # number of overall hits +system.cpu0.dcache.overall_hits::0 10252350 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10044158 # number of overall hits -system.cpu0.dcache.overall_miss_latency 123440933861 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.241285 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10252350 # number of overall hits +system.cpu0.dcache.overall_miss_latency 85052059550 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.225986 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 3194225 # number of overall misses +system.cpu0.dcache.overall_misses::0 2993349 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3194225 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1897268 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 40075842427 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.097969 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2993349 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1744779 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 31467736432 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.094262 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1296957 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2259854497 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1248570 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2241101498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1243005 # number of replacements -system.cpu0.dcache.sampled_refs 1243517 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1246736 # number of replacements +system.cpu0.dcache.sampled_refs 1247248 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.305455 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10525752 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.197481 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10604670 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 379678 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 40702182 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33733 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 526303 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 63705520 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32342676 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11446881 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1370864 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100557 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 1039748 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 867376 # DTB accesses -system.cpu0.dtb.data_acv 796 # DTB access violations -system.cpu0.dtb.data_hits 14352894 # DTB hits -system.cpu0.dtb.data_misses 32526 # DTB misses +system.cpu0.dcache.writebacks 721609 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 34091757 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33333 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 521194 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 62604059 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32208044 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11309029 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1270122 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100597 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 982195 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 794086 # DTB accesses +system.cpu0.dtb.data_acv 680 # DTB access violations +system.cpu0.dtb.data_hits 14244186 # DTB hits +system.cpu0.dtb.data_misses 32160 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 645773 # DTB read accesses -system.cpu0.dtb.read_acv 589 # DTB read access violations -system.cpu0.dtb.read_hits 8766713 # DTB read hits -system.cpu0.dtb.read_misses 26860 # DTB read misses -system.cpu0.dtb.write_accesses 221603 # DTB write accesses -system.cpu0.dtb.write_acv 207 # DTB write access violations -system.cpu0.dtb.write_hits 5586181 # DTB write hits -system.cpu0.dtb.write_misses 5666 # DTB write misses -system.cpu0.fetch.Branches 12665096 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7900913 # Number of cache lines fetched -system.cpu0.fetch.Cycles 20614864 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 378846 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 65028610 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 1156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 811969 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.105455 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7900913 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6926493 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.541457 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 86902352 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.748295 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.044395 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 598785 # DTB read accesses +system.cpu0.dtb.read_acv 509 # DTB read access violations +system.cpu0.dtb.read_hits 8659679 # DTB read hits +system.cpu0.dtb.read_misses 26490 # DTB read misses +system.cpu0.dtb.write_accesses 195301 # DTB write accesses +system.cpu0.dtb.write_acv 171 # DTB write access violations +system.cpu0.dtb.write_hits 5584507 # DTB write hits +system.cpu0.dtb.write_misses 5670 # DTB write misses +system.cpu0.fetch.Branches 12491766 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7797156 # Number of cache lines fetched +system.cpu0.fetch.Cycles 20279244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 375144 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 63684763 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 746145 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.110732 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7797156 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6757330 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.564528 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 79861148 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.797444 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.100172 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 74220009 85.41% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 901339 1.04% 86.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1804427 2.08% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 827724 0.95% 89.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2764395 3.18% 92.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 592140 0.68% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 693087 0.80% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 935405 1.08% 95.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4163826 4.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67408745 84.41% 84.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 900507 1.13% 85.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1775612 2.22% 87.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 807193 1.01% 88.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2749132 3.44% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 585022 0.73% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680161 0.85% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 829359 1.04% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4125417 5.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 86902352 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 7900913 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7900913 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15047.285683 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 79861148 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 7797156 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7797156 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15068.131136 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12005.143233 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 7053204 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7053204 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12755719499 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.107293 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 847709 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 847709 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 37907 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9721789000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.102495 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.324658 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6939758 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6939758 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12919385500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.109963 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 857398 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 857398 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 36516 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9864805500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105280 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 809802 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11235.849057 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 820882 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11596.153846 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.711370 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.455231 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 52 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 595500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 603000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7900913 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7797156 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7900913 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15047.285683 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7797156 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15068.131136 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 7053204 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12017.324658 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6939758 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7053204 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12755719499 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.107293 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6939758 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12919385500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.109963 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 847709 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 857398 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 847709 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 37907 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9721789000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.102495 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 857398 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 36516 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9864805500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.105280 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 809802 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 820882 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995703 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.799701 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7900913 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.861438 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7797156 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7900913 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15047.285683 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7797156 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15068.131136 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12017.324658 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 7053204 # number of overall hits +system.cpu0.icache.overall_hits::0 6939758 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7053204 # number of overall hits -system.cpu0.icache.overall_miss_latency 12755719499 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.107293 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6939758 # number of overall hits +system.cpu0.icache.overall_miss_latency 12919385500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.109963 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 847709 # number of overall misses +system.cpu0.icache.overall_misses::0 857398 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 847709 # number of overall misses -system.cpu0.icache.overall_mshr_hits 37907 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9721789000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.102495 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 857398 # number of overall misses +system.cpu0.icache.overall_mshr_hits 36516 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9864805500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.105280 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 809802 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 820882 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 809144 # number of replacements -system.cpu0.icache.sampled_refs 809655 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 820254 # number of replacements +system.cpu0.icache.sampled_refs 820765 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.799701 # Cycle average of tags in use -system.cpu0.icache.total_refs 7053204 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25253244000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 2 # number of writebacks -system.cpu0.idleCycles 33196891 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8125364 # Number of branches executed -system.cpu0.iew.EXEC:nop 3226641 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.422366 # Inst execution rate -system.cpu0.iew.EXEC:refs 14615271 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5604883 # Number of stores executed +system.cpu0.icache.tagsinuse 509.861438 # Cycle average of tags in use +system.cpu0.icache.total_refs 6939758 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 24435354000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 108 # number of writebacks +system.cpu0.idleCycles 32949400 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8094203 # Number of branches executed +system.cpu0.iew.EXEC:nop 3189422 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.446630 # Inst execution rate +system.cpu0.iew.EXEC:refs 14505244 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5602935 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31032245 # num instructions consuming a value -system.cpu0.iew.WB:count 50227097 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.763961 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31589475 # num instructions consuming a value +system.cpu0.iew.WB:count 50006148 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.758030 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23707433 # num instructions producing a value -system.cpu0.iew.WB:rate 0.418213 # insts written-back per cycle -system.cpu0.iew.WB:sent 50304093 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 713455 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9315247 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9510497 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1499135 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 880070 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5918886 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57821470 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 9010388 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 501816 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50725864 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 38579 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23945765 # num instructions producing a value +system.cpu0.iew.WB:rate 0.443275 # insts written-back per cycle +system.cpu0.iew.WB:sent 50087986 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 712279 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9112948 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9340675 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1511795 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 758903 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5843423 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57183881 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8902309 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 466602 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50384547 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 59804 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 5036 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1370864 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 530507 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 6983 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1270122 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 547925 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 262065 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 407910 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 13281 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 121839 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 411299 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 11485 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 40793 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18036 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1423462 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 506506 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 40793 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 332881 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 380574 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.390933 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.390933 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35394718 69.09% 69.10% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 55798 0.11% 69.21% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15086 0.03% 69.24% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.24% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.24% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.24% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1884 0.00% 69.24% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.24% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9327899 18.21% 87.45% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645566 11.02% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 782961 1.53% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 38596 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18609 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1250008 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 418646 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 38596 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 332551 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 379728 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.416094 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416094 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3763 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35146664 69.12% 69.12% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 56139 0.11% 69.23% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.23% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.26% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.26% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.26% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.26% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.27% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.27% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9202305 18.10% 87.36% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645893 11.10% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779184 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 51227682 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 363911 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007104 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 50851151 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 379787 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007469 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 39751 10.92% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.92% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 236746 65.06% 75.98% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 87414 24.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 40748 10.73% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.73% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 225975 59.50% 70.23% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 113064 29.77% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 86902352 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.589486 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.157706 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 79861148 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.636745 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.207484 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 61545337 70.82% 70.82% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12554046 14.45% 85.27% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5586431 6.43% 91.70% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3486187 4.01% 95.71% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2264793 2.61% 98.31% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 945170 1.09% 99.40% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 407098 0.47% 99.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 91717 0.11% 99.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 21573 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 55051799 68.93% 68.93% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12151486 15.22% 84.15% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5444442 6.82% 90.97% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3407774 4.27% 95.23% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2222623 2.78% 98.02% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 997342 1.25% 99.27% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 433832 0.54% 99.81% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 107535 0.13% 99.94% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 44315 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 86902352 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.426545 # Inst issue rate -system.cpu0.iq.iqInstsAdded 52886391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 51227682 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1708438 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 7322246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 33660 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1150184 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3910877 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 79861148 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.450766 # Inst issue rate +system.cpu0.iq.iqInstsAdded 52272510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 50851151 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1721949 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6732996 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24094 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1157202 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3425901 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 999568 # ITB accesses -system.cpu0.itb.fetch_acv 893 # ITB acv -system.cpu0.itb.fetch_hits 968847 # ITB hits -system.cpu0.itb.fetch_misses 30721 # ITB misses +system.cpu0.itb.fetch_accesses 952090 # ITB accesses +system.cpu0.itb.fetch_acv 738 # ITB acv +system.cpu0.itb.fetch_hits 923140 # ITB hits +system.cpu0.itb.fetch_misses 28950 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -453,550 +453,550 @@ system.cpu0.itb.write_acv 0 # DT system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 393 0.25% 0.25% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3319 2.08% 2.33% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.36% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.36% # number of callpals executed -system.cpu0.kern.callpal::swpipl 144424 90.42% 92.78% # number of callpals executed -system.cpu0.kern.callpal::rdps 6390 4.00% 96.78% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.79% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.79% # number of callpals executed -system.cpu0.kern.callpal::rti 4592 2.87% 99.67% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.24% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 351 0.22% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 147044 90.75% 93.03% # number of callpals executed +system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 159723 # number of callpals executed +system.cpu0.kern.callpal::total 162036 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 175260 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6689 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 61186 40.39% 40.39% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 239 0.16% 40.55% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1930 1.27% 41.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 300 0.20% 42.02% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 87830 57.98% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 151485 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 60407 49.12% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 239 0.19% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1930 1.57% 50.88% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 300 0.24% 51.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 60108 48.87% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 122984 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866417310500 97.89% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 97564500 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 399841000 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 136212500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39623165500 2.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906674094000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.987268 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 176105 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6623 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 89358 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 153912 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862678817000 97.99% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96273000 0.01% 98.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398546000 0.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 103367000 0.01% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37550788000 1.98% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900827791000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684368 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1353 -system.cpu0.kern.mode_good::user 1354 +system.cpu0.kern.ipl_used::31 0.682793 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1171 +system.cpu0.kern.mode_good::user 1172 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 7157 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1172 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.189046 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169956 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904400738500 99.88% 99.88% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2273347500 0.12% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1898857065000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1970718000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3320 # number of times the context was actually changed -system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 232 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2539862 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2208172 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9510497 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5918886 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 120099243 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 13446049 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 34012953 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1022261 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33782009 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1807708 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16757 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 73652966 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 60220724 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 40595001 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11156910 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1370864 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 4406747 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 6582046 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 22739771 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1403717 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10900390 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 213877 # count of temporary serializing insts renamed -system.cpu0.timesIdled 1182515 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.kern.swap_context 3288 # number of times the context was actually changed +system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.46% 11.44% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.49% 12.94% # number of syscalls executed +system.cpu0.kern.syscall::6 27 13.43% 26.37% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.50% 26.87% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.48% 31.34% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.99% 34.33% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.99% 36.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.50% 36.82% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.49% 38.31% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.48% 41.79% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.00% 42.79% # number of syscalls executed +system.cpu0.kern.syscall::45 36 17.91% 60.70% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.49% 62.19% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.48% 65.67% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.48% 70.15% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.50% 70.65% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.49% 73.13% # number of syscalls executed +system.cpu0.kern.syscall::71 27 13.43% 86.57% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.49% 88.06% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.48% 91.54% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.50% 92.04% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.50% 92.54% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.48% 96.02% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.00% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.00% 98.01% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 201 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2328642 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1937858 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9340675 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5843423 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 112810548 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 12992019 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 33999562 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1006246 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33622049 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1438466 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 43293 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 72562175 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 59339637 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 39991159 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11032673 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1270122 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 4054916 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5991595 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 16889367 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1393634 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10149085 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 207632 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1187372 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1168869 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2724358 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8216 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 170435 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2536443 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 3058879 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 214059 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1536055 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 205800 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1155732 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2684041 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8261 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 171129 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2476500 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 2988933 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 209112 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1513156 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 195927 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 19921603 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.539460 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.350836 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 17812439 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.593209 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.404519 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 15476427 77.69% 77.69% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2094576 10.51% 88.20% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 801789 4.02% 92.23% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 588293 2.95% 95.18% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 417407 2.10% 97.27% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 144338 0.72% 98.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 104661 0.53% 98.52% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 88312 0.44% 98.97% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 205800 1.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 13432656 75.41% 75.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2071277 11.63% 87.04% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 798332 4.48% 91.52% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 569921 3.20% 94.72% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 392752 2.20% 96.93% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 150104 0.84% 97.77% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 110432 0.62% 98.39% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 91038 0.51% 98.90% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 195927 1.10% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 19921603 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10746901 # Number of instructions committed -system.cpu1.commit.COM:loads 2021572 # Number of loads committed -system.cpu1.commit.COM:membars 56653 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3430255 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 17812439 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10566506 # Number of instructions committed +system.cpu1.commit.COM:loads 1991573 # Number of loads committed +system.cpu1.commit.COM:membars 52753 # Number of memory barriers committed +system.cpu1.commit.COM:refs 3374641 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 163240 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10746901 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 172585 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1766208 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10192138 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10192138 # Number of Instructions Simulated -system.cpu1.cpi 2.158157 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.158157 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 48648 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 48648 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10962.569444 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 163273 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10566506 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 163051 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1705232 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10039690 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10039690 # Number of Instructions Simulated +system.cpu1.cpi 1.952682 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.952682 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 46395 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46395 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11084.323923 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7807.164404 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 41448 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 41448 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 78930500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.148002 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 7200 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 7200 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 570 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 51761500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136285 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8010.474275 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 39665 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39665 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 74597500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145059 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 763 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47798500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128613 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 6630 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2081061 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2081061 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16526.110109 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2059923 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2059923 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15005.371131 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11960.136769 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11669.279162 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1891958 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1891958 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 3125137000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.090869 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 189103 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 189103 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 93175 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1147312000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046096 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1864992 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1864992 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 2925012000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.094630 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 194931 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 194931 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 99875 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1109235000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046145 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95928 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 16183000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 45890 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 45890 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35468.138068 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 95056 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 43203 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43203 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13176.417292 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32471.951759 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 36851 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 36851 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 320596500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.196971 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 9039 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9039 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 293481500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.196949 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10174.605229 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 39340 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 39340 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 50900500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3863 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3863 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39304500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089415 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 9038 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1356401 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1356401 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 48468.442060 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 3863 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1333474 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1333474 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 21222.665351 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 50000.550136 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18784.142303 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1038709 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1038709 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 15398036295 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.234217 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 317692 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 317692 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 255162 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 3126534400 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.046100 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1083830 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1083830 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 5298111069 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.187213 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 249644 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 249644 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 201142 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 911068470 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036373 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 62530 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 383884000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11747.407108 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 48502 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377673500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9931.219300 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 23.303685 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 12380 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 22.846422 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 5285 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 145432900 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 52486494 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3437462 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3393397 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3437462 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 36549.637023 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3393397 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 18496.593531 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2930667 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14073.081751 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2948822 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2930667 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 18523173295 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.147433 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2948822 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 8223123069 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.131012 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 506795 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 444575 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 506795 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 348337 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4273846400 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.046097 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 444575 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 301017 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 2020303470 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.042305 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 158458 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 143558 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.929332 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 475.817757 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3437462 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.932894 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 477.641661 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3393397 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3437462 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 36549.637023 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3393397 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 18496.593531 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14073.081751 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2930667 # number of overall hits +system.cpu1.dcache.overall_hits::0 2948822 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2930667 # number of overall hits -system.cpu1.dcache.overall_miss_latency 18523173295 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.147433 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2948822 # number of overall hits +system.cpu1.dcache.overall_miss_latency 8223123069 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.131012 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 506795 # number of overall misses +system.cpu1.dcache.overall_misses::0 444575 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 506795 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 348337 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4273846400 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.046097 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 444575 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 301017 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 2020303470 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.042305 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 158458 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 400067000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 143558 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 395351000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 131481 # number of replacements -system.cpu1.dcache.sampled_refs 131801 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 132490 # number of replacements +system.cpu1.dcache.sampled_refs 132884 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 475.817757 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3071449 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1882597271000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 66520 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 8690485 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 7262 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 129460 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 14175016 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8601755 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2517670 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 311026 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 21330 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 111692 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 379731 # DTB accesses -system.cpu1.dtb.data_acv 79 # DTB access violations -system.cpu1.dtb.data_hits 3682802 # DTB hits -system.cpu1.dtb.data_misses 10764 # DTB misses +system.cpu1.dcache.tagsinuse 477.641661 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3035924 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1877659074000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 88699 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 6971990 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 7938 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 127719 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 13891801 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8246933 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2493797 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 302659 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 23688 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 99718 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 452227 # DTB accesses +system.cpu1.dtb.data_acv 183 # DTB access violations +system.cpu1.dtb.data_hits 3607185 # DTB hits +system.cpu1.dtb.data_misses 12842 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 273464 # DTB read accesses -system.cpu1.dtb.read_acv 11 # DTB read access violations -system.cpu1.dtb.read_hits 2232523 # DTB read hits -system.cpu1.dtb.read_misses 8601 # DTB read misses -system.cpu1.dtb.write_accesses 106267 # DTB write accesses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_hits 1450279 # DTB write hits -system.cpu1.dtb.write_misses 2163 # DTB write misses -system.cpu1.fetch.Branches 3058879 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1688815 # Number of cache lines fetched -system.cpu1.fetch.Cycles 4357354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 105751 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14416907 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 193553 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.139064 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1688815 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1382928 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.655426 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 20232629 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.712557 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.050166 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 320739 # DTB read accesses +system.cpu1.dtb.read_acv 82 # DTB read access violations +system.cpu1.dtb.read_hits 2181924 # DTB read hits +system.cpu1.dtb.read_misses 10502 # DTB read misses +system.cpu1.dtb.write_accesses 131488 # DTB write accesses +system.cpu1.dtb.write_acv 101 # DTB write access violations +system.cpu1.dtb.write_hits 1425261 # DTB write hits +system.cpu1.dtb.write_misses 2340 # DTB write misses +system.cpu1.fetch.Branches 2988933 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1669639 # Number of cache lines fetched +system.cpu1.fetch.Cycles 4303594 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 104390 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14140107 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 288 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 190275 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.152463 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1669639 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1364844 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.721275 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 18115098 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.780570 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.128559 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 17569535 86.84% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 215879 1.07% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 322874 1.60% 89.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 192834 0.95% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 374265 1.85% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 129017 0.64% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 159403 0.79% 93.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 272361 1.35% 95.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 996461 4.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15489559 85.51% 85.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 208264 1.15% 86.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 323571 1.79% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 199234 1.10% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 375752 2.07% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 125718 0.69% 92.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169462 0.94% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 249675 1.38% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 973863 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 20232629 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 1688815 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1688815 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14598.075134 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 18115098 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 1669639 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1669639 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14675.575285 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11541.965319 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1410406 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1410406 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 4064235500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.164855 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 278409 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 278409 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 7888 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 3122344000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.160184 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11632.875773 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1406074 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1406074 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3867968000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.157857 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 263565 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 263565 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 8225 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2970338500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152931 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 270521 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 8125 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 255340 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5055.555556 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.214764 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.507925 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 65000 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 45500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1688815 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1669639 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1688815 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14598.075134 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1669639 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14675.575285 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11541.965319 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1410406 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11632.875773 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1406074 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1410406 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 4064235500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.164855 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1406074 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3867968000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.157857 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 278409 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 263565 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 278409 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 7888 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 3122344000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.160184 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 263565 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 8225 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2970338500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.152931 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 270521 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 255340 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.900098 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 460.849961 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1688815 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.900435 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 461.022508 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1669639 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1688815 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14598.075134 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1669639 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14675.575285 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11541.965319 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11632.875773 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1410406 # number of overall hits +system.cpu1.icache.overall_hits::0 1406074 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1410406 # number of overall hits -system.cpu1.icache.overall_miss_latency 4064235500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.164855 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1406074 # number of overall hits +system.cpu1.icache.overall_miss_latency 3867968000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.157857 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 278409 # number of overall misses +system.cpu1.icache.overall_misses::0 263565 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 278409 # number of overall misses -system.cpu1.icache.overall_mshr_hits 7888 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 3122344000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.160184 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 263565 # number of overall misses +system.cpu1.icache.overall_mshr_hits 8225 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2970338500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.152931 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 270521 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 255340 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 269955 # number of replacements -system.cpu1.icache.sampled_refs 270464 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 254770 # number of replacements +system.cpu1.icache.sampled_refs 255282 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 460.849961 # Cycle average of tags in use -system.cpu1.icache.total_refs 1410406 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1902950008000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 1763601 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1647161 # Number of branches executed -system.cpu1.iew.EXEC:nop 633873 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.498846 # Inst execution rate -system.cpu1.iew.EXEC:refs 3712298 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1459673 # Number of stores executed +system.cpu1.icache.tagsinuse 461.022508 # Cycle average of tags in use +system.cpu1.icache.total_refs 1406074 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897916485000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 12 # number of writebacks +system.cpu1.idleCycles 1489226 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1621685 # Number of branches executed +system.cpu1.iew.EXEC:nop 600518 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.550648 # Inst execution rate +system.cpu1.iew.EXEC:refs 3638770 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1434645 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6255206 # num instructions consuming a value -system.cpu1.iew.WB:count 10847139 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.739229 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6221893 # num instructions consuming a value +system.cpu1.iew.WB:count 10690151 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.737580 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4624029 # num instructions producing a value -system.cpu1.iew.WB:rate 0.493136 # insts written-back per cycle -system.cpu1.iew.WB:sent 10867556 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 177268 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 332920 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2358529 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 525453 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 201798 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1538474 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12592629 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2252625 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 104488 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10972727 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 3148 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4589145 # num instructions producing a value +system.cpu1.iew.WB:rate 0.545296 # insts written-back per cycle +system.cpu1.iew.WB:sent 10713297 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 177050 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 257506 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2306314 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 500674 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 208241 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1509678 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12354884 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2204125 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 106415 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10795075 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 2676 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 1572 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 311026 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 9766 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 4880 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 302659 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 10387 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 50281 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 68629 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 4124 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 20658 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 67397 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 2150 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 9401 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 371 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 336957 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 129791 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 9401 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104860 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 72408 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.463358 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.463358 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3519 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6926354 62.53% 62.56% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 18692 0.17% 62.73% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.73% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11838 0.11% 62.84% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.02% 62.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2331483 21.05% 83.90% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1476157 13.33% 97.22% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307413 2.78% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 10614 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 379 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 314741 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 126610 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 10614 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104614 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 72436 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.512116 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.512116 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3525 0.03% 0.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6828006 62.63% 62.67% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 17554 0.16% 62.83% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.83% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 62.93% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.93% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.93% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.93% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 62.95% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2279720 20.91% 83.86% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1451557 13.32% 97.18% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307934 2.82% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 11077215 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 158215 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014283 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 10901490 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 154119 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014137 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 4066 2.57% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 92866 58.70% 61.27% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 61283 38.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 3997 2.59% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.59% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 90686 58.84% 61.43% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 59436 38.57% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 20232629 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.547493 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.152304 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 18115098 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.601790 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.204979 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 14868449 73.49% 73.49% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2672522 13.21% 86.70% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1102181 5.45% 92.14% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 699877 3.46% 95.60% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 518299 2.56% 98.16% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 241576 1.19% 99.36% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 93786 0.46% 99.82% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 30604 0.15% 99.97% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 5335 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 12897978 71.20% 71.20% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2566961 14.17% 85.37% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1067808 5.89% 91.27% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 689821 3.81% 95.07% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 522358 2.88% 97.96% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 233805 1.29% 99.25% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 92642 0.51% 99.76% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 34659 0.19% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 9066 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 20232629 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.503596 # Inst issue rate -system.cpu1.iq.iqInstsAdded 11373839 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 11077215 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 584917 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1698901 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10384 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 412332 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 877867 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 18115098 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.556076 # Inst issue rate +system.cpu1.iq.iqInstsAdded 11198244 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 10901490 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 556122 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1641267 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10273 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 393071 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 839516 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 413824 # ITB accesses -system.cpu1.itb.fetch_acv 100 # ITB acv -system.cpu1.itb.fetch_hits 408478 # ITB hits -system.cpu1.itb.fetch_misses 5346 # ITB misses +system.cpu1.itb.fetch_accesses 447863 # ITB accesses +system.cpu1.itb.fetch_acv 278 # ITB acv +system.cpu1.itb.fetch_hits 439724 # ITB hits +system.cpu1.itb.fetch_misses 8139 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1006,95 +1006,105 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 300 0.50% 0.50% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.50% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.50% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1497 2.49% 3.00% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 254 0.44% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed +system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 52375 87.24% 90.26% # number of callpals executed -system.cpu1.kern.callpal::rdps 2373 3.95% 94.21% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.21% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.22% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.22% # number of callpals executed -system.cpu1.kern.callpal::rti 3300 5.50% 99.72% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.21% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49382 86.51% 89.53% # number of callpals executed +system.cpu1.kern.callpal::rdps 2383 4.17% 93.71% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 93.72% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.72% # number of callpals executed +system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # number of callpals executed +system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 60033 # number of callpals executed +system.cpu1.kern.callpal::total 57084 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 66427 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2553 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 21855 37.68% 37.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1927 3.32% 41.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 393 0.68% 41.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 33821 58.32% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 57996 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 21257 47.83% 47.83% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1927 4.34% 52.17% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 393 0.88% 53.05% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 20864 46.95% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 44441 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874788065000 98.35% 98.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 349524500 0.02% 98.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 166729500 0.01% 98.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30954744500 1.62% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1906259063500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.972638 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 64923 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 20673 37.58% 37.58% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 3.49% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 32062 58.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 55008 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 20166 47.73% 47.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 4.55% 52.27% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 19815 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 42254 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870782192000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 347977500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 137627500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29209741000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900477538000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975475 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.616895 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 700 -system.cpu1.kern.mode_good::user 383 -system.cpu1.kern.mode_good::idle 317 -system.cpu1.kern.mode_switch::kernel 1588 # number of protection mode switches -system.cpu1.kern.mode_switch::user 383 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2627 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.440806 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.618021 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 849 +system.cpu1.kern.mode_good::user 573 +system.cpu1.kern.mode_good::idle 276 +system.cpu1.kern.mode_switch::kernel 1769 # number of protection mode switches +system.cpu1.kern.mode_switch::user 573 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2540 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.479932 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.120670 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.561476 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 7544739000 0.40% 0.40% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 853569500 0.04% 0.44% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897425262500 99.56% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1498 # number of times the context was actually changed -system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed -system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed -system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 94 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 510972 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 447437 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2358529 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1538474 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 21996230 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 659886 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7238905 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 29431 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8848928 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 376341 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 2702 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15628999 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 13115251 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8582665 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2365502 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 311026 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 913464 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1343760 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 7133821 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 521569 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2485864 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 55479 # count of temporary serializing insts renamed -system.cpu1.timesIdled 207727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.kern.mode_switch_good::idle 0.108661 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.588594 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6304093000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1020319500 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893140641500 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1451 # number of times the context was actually changed +system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed +system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.80% 12.80% # number of syscalls executed +system.cpu1.kern.syscall::6 15 12.00% 24.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.80% 25.60% # number of syscalls executed +system.cpu1.kern.syscall::17 6 4.80% 30.40% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.20% 33.60% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.60% 35.20% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.40% 37.60% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.40% 40.00% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.20% 43.20% # number of syscalls executed +system.cpu1.kern.syscall::45 18 14.40% 57.60% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.40% 60.00% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.40% 62.40% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.80% 63.20% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.60% 64.80% # number of syscalls executed +system.cpu1.kern.syscall::71 27 21.60% 86.40% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.20% 93.60% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.60% 95.20% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.60% 96.80% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 125 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 493721 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 420829 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2306314 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1509678 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 19604324 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 523322 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7130376 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 34965 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8479727 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 256792 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 15396 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15372563 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 12869198 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8442140 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2348315 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 302659 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 803488 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1311764 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 5657585 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 515686 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2307049 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 52733 # count of temporary serializing insts renamed +system.cpu1.timesIdled 194546 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1110,14 +1120,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 172 # number of ReadReq misses system.iocache.ReadReq_misses::total 172 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -1125,37 +1135,37 @@ system.iocache.ReadReq_mshr_misses 172 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137834.973190 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137710.430449 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85831.529120 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5727318806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85706.873219 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5722143806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3566471698 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561291996 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6167.680658 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6177.017118 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64507772 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64593068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137741.966350 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137617.913048 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85738.536478 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85614.370482 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5747145804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741969804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -1163,7 +1173,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3577354696 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572173994 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -1171,20 +1181,20 @@ system.iocache.demand_mshr_misses 41724 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029720 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.475524 # Average occupied blocks per context +system.iocache.occ_%::1 0.029205 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.467285 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137741.966350 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137617.913048 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85738.536478 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85614.370482 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5747145804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741969804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -1192,7 +1202,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3577354696 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572173994 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -1202,196 +1212,196 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41692 # number of replacements system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.475524 # Cycle average of tags in use +system.iocache.tagsinuse 0.467285 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1715203940000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711286407000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257631 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 41153 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298784 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 60735.824013 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 380275.607871 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257280 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 42301 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 299581 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55984.106319 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 837903.858521 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40207.175331 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 1663 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 271 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1934 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 15546427401 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.993545 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.993415 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 255968 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 40882 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 296850 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 11935499997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.152229 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 7.213326 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40324.237567 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 140913 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 34526 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175439 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6514702500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.452297 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.183802 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116367 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7775 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124142 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5005931500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.482517 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.934730 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 296850 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1795093 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 360112 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2155205 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52872.781104 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3365794.496366 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 124142 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1807521 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 343124 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2150645 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52801.759863 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3686733.249197 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40019.494912 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.781571 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1488578 # number of ReadReq hits -system.l2c.ReadReq_hits::1 355297 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1843875 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16206300500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.170752 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.013371 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 306515 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4815 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311330 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12458549000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.173424 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.864487 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1503236 # number of ReadReq hits +system.l2c.ReadReq_hits::1 338766 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1842002 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16066783500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.168344 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.012701 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304285 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4358 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308643 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12350876500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.170746 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.899462 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311312 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840831000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 14188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 5331 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19519 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 67372.602257 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 179272.565209 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 308627 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840467500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 597 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 609 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1206 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 4976.234004 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4685.025818 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.251217 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 955343500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.999436 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.999625 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 14180 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 5329 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 19509 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 780579500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.375035 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 3.659539 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40010.195035 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 50 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 2722000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.916248 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.954023 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 547 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 581 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1128 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 45131500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.889447 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.852217 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 19509 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 55251 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 16863 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 72114 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 64253.326605 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 210525.121307 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 1128 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 2889 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 1652 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4541 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5869.326501 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12325.134512 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.687237 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 5 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 21 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 3549032495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.999710 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.999703 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 55235 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 16858 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 72093 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 2885283498 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.304827 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.275218 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.488966 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 157 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 351 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 508 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 16035000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.945656 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.787530 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 2732 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 1301 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4033 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 161386500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.395985 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.441283 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 72093 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4033 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1554057498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 446200 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 446200 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 446200 # number of Writeback hits -system.l2c.Writeback_hits::total 446200 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1532909498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 810428 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 810428 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 810428 # number of Writeback hits +system.l2c.Writeback_hits::total 810428 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.752489 # Average number of references to valid blocks. +system.l2c.avg_refs 5.655479 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2052724 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 401265 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2064801 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 385425 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2453989 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 56451.000121 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 694853.664376 # average overall miss latency +system.l2c.demand_accesses::total 2450226 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 53682.107776 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1861162.614358 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency -system.l2c.demand_hits::0 1490241 # number of demand (read+write) hits -system.l2c.demand_hits::1 355568 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40106.403185 # average overall mshr miss latency +system.l2c.demand_hits::0 1644149 # number of demand (read+write) hits +system.l2c.demand_hits::1 373292 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1845809 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31752727901 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.274018 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.113882 # miss rate for demand accesses +system.l2c.demand_hits::total 2017441 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22581486000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.203725 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.031480 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 562483 # number of demand (read+write) misses -system.l2c.demand_misses::1 45697 # number of demand (read+write) misses +system.l2c.demand_misses::0 420652 # number of demand (read+write) misses +system.l2c.demand_misses::1 12133 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 608180 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24394048997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.296271 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.515612 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 432785 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 17356808000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.209594 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.122836 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 608162 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 432769 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.174396 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005052 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.332288 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 11429.229058 # Average occupied blocks per context -system.l2c.occ_blocks::1 331.081192 # Average occupied blocks per context -system.l2c.occ_blocks::2 21776.825321 # Average occupied blocks per context -system.l2c.overall_accesses::0 2052724 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 401265 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.187903 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005747 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.351863 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12314.431078 # Average occupied blocks per context +system.l2c.occ_blocks::1 376.630124 # Average occupied blocks per context +system.l2c.occ_blocks::2 23059.694781 # Average occupied blocks per context +system.l2c.overall_accesses::0 2064801 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 385425 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2453989 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 56451.000121 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 694853.664376 # average overall miss latency +system.l2c.overall_accesses::total 2450226 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 53682.107776 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1861162.614358 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40106.403185 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1490241 # number of overall hits -system.l2c.overall_hits::1 355568 # number of overall hits +system.l2c.overall_hits::0 1644149 # number of overall hits +system.l2c.overall_hits::1 373292 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1845809 # number of overall hits -system.l2c.overall_miss_latency 31752727901 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.274018 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.113882 # miss rate for overall accesses +system.l2c.overall_hits::total 2017441 # number of overall hits +system.l2c.overall_miss_latency 22581486000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.203725 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.031480 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 562483 # number of overall misses -system.l2c.overall_misses::1 45697 # number of overall misses +system.l2c.overall_misses::0 420652 # number of overall misses +system.l2c.overall_misses::1 12133 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 608180 # number of overall misses -system.l2c.overall_mshr_hits 18 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24394048997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.296271 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.515612 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 432785 # number of overall misses +system.l2c.overall_mshr_hits 16 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 17356808000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.209594 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.122836 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 608162 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2394888498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 432769 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2373376998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 399060 # number of replacements -system.l2c.sampled_refs 435274 # Sample count of references to valid blocks. +system.l2c.replacements 395546 # number of replacements +system.l2c.sampled_refs 431605 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 33537.135570 # Cycle average of tags in use -system.l2c.total_refs 2068635 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9277782000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 122307 # number of writebacks +system.l2c.tagsinuse 35750.755983 # Cycle average of tags in use +system.l2c.total_refs 2440933 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 121345 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 208609d63..422a343b6 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,12 +8,12 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -356,7 +356,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -376,7 +376,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -502,7 +502,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f8d53b80a..bdccd9639 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 12:51:14 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:51:33 -M5 executing on zizzer +M5 compiled Sep 20 2010 15:04:50 +M5 revision 0c4a7d867247 7686 default qtip print-identical tip +M5 started Sep 20 2010 15:17:56 +M5 executing on phenom command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865288389500 because m5_exit instruction encountered +Exiting @ tick 1865720303500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index df900ba3a..eeeafc5e0 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,449 +1,447 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83534 # Simulator instruction rate (inst/s) -host_mem_usage 292436 # Number of bytes of host memory used -host_seconds 635.06 # Real time elapsed on the host -host_tick_rate 2937207030 # Simulator tick rate (ticks/s) +host_inst_rate 159619 # Simulator instruction rate (inst/s) +host_mem_usage 280620 # Number of bytes of host memory used +host_seconds 332.38 # Real time elapsed on the host +host_tick_rate 5613142222 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53048754 # Number of instructions simulated -sim_seconds 1.865288 # Number of seconds simulated -sim_ticks 1865288389500 # Number of ticks simulated +sim_insts 53054978 # Number of instructions simulated +sim_seconds 1.865720 # Number of seconds simulated +sim_ticks 1865720303500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6766434 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12986969 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41472 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 813466 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12097848 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14524578 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1028567 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8457223 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1009026 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6622960 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12821186 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 40564 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 813627 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11934155 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14336611 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1015763 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8457975 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1007897 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 98617953 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.570296 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.335991 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 89507255 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.628419 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.391887 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 74454640 75.50% 75.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10711227 10.86% 86.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 5970777 6.05% 92.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2911969 2.95% 95.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2119464 2.15% 97.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 692478 0.70% 98.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 398357 0.40% 98.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 350015 0.35% 98.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1009026 1.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 65378590 73.04% 73.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10678414 11.93% 84.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6017811 6.72% 91.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2845727 3.18% 94.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2113660 2.36% 97.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 688870 0.77% 98.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 399291 0.45% 98.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 376995 0.42% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1007897 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 98617953 # Number of insts commited each cycle -system.cpu.commit.COM:count 56241389 # Number of instructions committed -system.cpu.commit.COM:loads 9301917 # Number of loads committed -system.cpu.commit.COM:membars 227986 # Number of memory barriers committed -system.cpu.commit.COM:refs 15690474 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 89507255 # Number of insts commited each cycle +system.cpu.commit.COM:count 56248094 # Number of instructions committed +system.cpu.commit.COM:loads 9303211 # Number of loads committed +system.cpu.commit.COM:membars 227966 # Number of memory barriers committed +system.cpu.commit.COM:refs 15692722 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 771977 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56241389 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667741 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9346936 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53048754 # Number of Instructions Simulated -system.cpu.committedInsts_total 53048754 # Number of Instructions Simulated -system.cpu.cpi 2.541919 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.541919 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214829 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214829 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15450.383219 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 772391 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56248094 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667633 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8673540 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53054978 # Number of Instructions Simulated +system.cpu.committedInsts_total 53054978 # Number of Instructions Simulated +system.cpu.cpi 2.357684 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.357684 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 215825 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215825 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14729.331951 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11789.484229 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192518 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192518 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344713500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103855 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22311 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4842 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205950500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081316 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11874.503483 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 193641 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 193641 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 326755500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.102787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22184 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22184 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4813 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206272000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080487 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17469 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9301988 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9301988 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23801.813261 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17371 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9299177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9299177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 22716.761778 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22758.438856 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22778.216619 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7781909 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7781909 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36180636500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.163414 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1520079 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1520079 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 436579 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24658768500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116480 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7724529 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7724529 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 35770903500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.169332 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1574648 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1574648 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 490606 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24692543500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116574 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1083500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904975000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219792 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56335.990566 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084042 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906118000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53335.990566 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 198592 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198592 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1194323000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.096455 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 21200 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 21200 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1130723000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.096455 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 219738 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219738 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 56000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000018 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 44000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000018 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 21200 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6153614 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6153614 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 48733.687858 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 4 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6154612 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6154612 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29779.159103 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53794.875061 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.813701 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3986142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3986142 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 105628903889 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.352227 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2167472 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2167472 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1799517 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 19794093253 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.059795 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4298505 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4298505 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 55273305665 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.301580 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 1856107 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1856107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1556374 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8419743863 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048701 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 367955 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235122997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9816.976394 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17750 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.810921 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 136746 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 299733 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235249998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8585.120096 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.876782 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 86206 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1342432254 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 35500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 740088863 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15455602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15453789 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15455602 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38456.292642 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15453789 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26537.659834 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11768051 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23928.953307 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 12023034 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11768051 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 141809540389 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.238590 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 12023034 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 91044209165 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.222001 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3687551 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3430755 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3687551 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2236096 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 44452861753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.093911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3430755 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2046980 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33112287363 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.089543 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1451455 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1383775 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_%::1 -0.007635 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995459 # Average occupied blocks per context -system.cpu.dcache.occ_blocks::1 -3.909039 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15455602 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.995487 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15453789 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15455602 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38456.292642 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15453789 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26537.659834 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23928.953307 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11768051 # number of overall hits +system.cpu.dcache.overall_hits::0 12023034 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11768051 # number of overall hits -system.cpu.dcache.overall_miss_latency 141809540389 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.238590 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 12023034 # number of overall hits +system.cpu.dcache.overall_miss_latency 91044209165 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.222001 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3687551 # number of overall misses +system.cpu.dcache.overall_misses::0 3430755 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3687551 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2236096 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 44452861753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.093911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3430755 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2046980 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33112287363 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.089543 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1451455 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140097997 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1383775 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2141367998 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400442 # number of replacements -system.cpu.dcache.sampled_refs 1400954 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400502 # number of replacements +system.cpu.dcache.sampled_refs 1401014 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 510.040943 # Cycle average of tags in use -system.cpu.dcache.total_refs 12343695 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.995487 # Cycle average of tags in use +system.cpu.dcache.total_refs 12436496 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 455265 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 46660710 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42482 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 616847 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72473028 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37849528 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12958836 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1616629 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 135444 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1148878 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1239402 # DTB accesses -system.cpu.dtb.data_acv 830 # DTB access violations -system.cpu.dtb.data_hits 16737953 # DTB hits -system.cpu.dtb.data_misses 44771 # DTB misses +system.cpu.dcache.writebacks 832844 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 38077949 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42141 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 613000 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 71339111 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37499395 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12847543 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1512175 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134289 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1082367 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1229801 # DTB accesses +system.cpu.dtb.data_acv 813 # DTB access violations +system.cpu.dtb.data_hits 16587007 # DTB hits +system.cpu.dtb.data_misses 46930 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 913549 # DTB read accesses -system.cpu.dtb.read_acv 594 # DTB read access violations -system.cpu.dtb.read_hits 10142643 # DTB read hits -system.cpu.dtb.read_misses 36670 # DTB read misses -system.cpu.dtb.write_accesses 325853 # DTB write accesses -system.cpu.dtb.write_acv 236 # DTB write access violations -system.cpu.dtb.write_hits 6595310 # DTB write hits -system.cpu.dtb.write_misses 8101 # DTB write misses -system.cpu.fetch.Branches 14524578 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8948260 # Number of cache lines fetched -system.cpu.fetch.Cycles 23311047 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 456775 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 73989590 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2537 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 952530 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.107713 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8948260 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7795001 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.548698 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 100234582 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.738164 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.038365 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 909497 # DTB read accesses +system.cpu.dtb.read_acv 578 # DTB read access violations +system.cpu.dtb.read_hits 10001234 # DTB read hits +system.cpu.dtb.read_misses 38618 # DTB read misses +system.cpu.dtb.write_accesses 320304 # DTB write accesses +system.cpu.dtb.write_acv 235 # DTB write access violations +system.cpu.dtb.write_hits 6585773 # DTB write hits +system.cpu.dtb.write_misses 8312 # DTB write misses +system.cpu.fetch.Branches 14336611 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8856375 # Number of cache lines fetched +system.cpu.fetch.Cycles 23007170 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 453326 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 72609191 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 3119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 881894 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114613 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8856375 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7638723 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.580470 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 91019430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.797733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.106251 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 85912196 85.71% 85.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1042441 1.04% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1978378 1.97% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 936363 0.93% 89.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2989129 2.98% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 664727 0.66% 93.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 787515 0.79% 94.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1214601 1.21% 95.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4709232 4.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76908614 84.50% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1045900 1.15% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1970690 2.17% 87.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 922798 1.01% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2985749 3.28% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 648659 0.71% 92.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 777022 0.85% 93.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1074890 1.18% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4685108 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 100234582 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8948260 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8948260 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14907.888251 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 91019430 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8856375 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8856375 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14955.618992 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11902.318660 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7903415 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7903415 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15576432500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116765 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1044845 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1044845 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 50305 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11837332000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111143 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.509769 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7815975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7815975 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15559825999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.117475 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1040400 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1040400 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 47600 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11852552499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112100 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 994540 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12104.838710 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 992800 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 12245.264151 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.948315 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 62 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.874156 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 53 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 750500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 648999 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8948260 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8856375 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8948260 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14907.888251 # average overall miss latency +system.cpu.icache.demand_accesses::total 8856375 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14955.618992 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7903415 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11938.509769 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7815975 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7903415 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15576432500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116765 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7815975 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15559825999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.117475 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1044845 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1040400 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1044845 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 50305 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11837332000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.111143 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1040400 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 47600 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11852552499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.112100 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 994540 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 992800 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995598 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.746088 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8948260 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.810488 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8856375 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8948260 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14907.888251 # average overall miss latency +system.cpu.icache.overall_accesses::total 8856375 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14955.618992 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11938.509769 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7903415 # number of overall hits +system.cpu.icache.overall_hits::0 7815975 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7903415 # number of overall hits -system.cpu.icache.overall_miss_latency 15576432500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116765 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7815975 # number of overall hits +system.cpu.icache.overall_miss_latency 15559825999 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.117475 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1044845 # number of overall misses +system.cpu.icache.overall_misses::0 1040400 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1044845 # number of overall misses -system.cpu.icache.overall_mshr_hits 50305 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11837332000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.111143 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1040400 # number of overall misses +system.cpu.icache.overall_mshr_hits 47600 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11852552499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.112100 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 994540 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 992800 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 993840 # number of replacements -system.cpu.icache.sampled_refs 994351 # Sample count of references to valid blocks. +system.cpu.icache.replacements 992100 # number of replacements +system.cpu.icache.sampled_refs 992611 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.746088 # Cycle average of tags in use -system.cpu.icache.total_refs 7903415 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25251004000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 5 # number of writebacks -system.cpu.idleCycles 34611048 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9149461 # Number of branches executed -system.cpu.iew.EXEC:nop 3645494 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.426187 # Inst execution rate -system.cpu.iew.EXEC:refs 17021543 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6618330 # Number of stores executed +system.cpu.icache.tagsinuse 509.810488 # Cycle average of tags in use +system.cpu.icache.total_refs 7815974 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 24432976000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 92 # number of writebacks +system.cpu.idleCycles 34067458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9122615 # Number of branches executed +system.cpu.iew.EXEC:nop 3587548 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.456821 # Inst execution rate +system.cpu.iew.EXEC:refs 16872636 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6608998 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34491432 # num instructions consuming a value -system.cpu.iew.WB:count 56873596 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.763558 # average fanout of values written-back +system.cpu.iew.WB:consumers 35235161 # num instructions consuming a value +system.cpu.iew.WB:count 56707736 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757346 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26336207 # num instructions producing a value -system.cpu.iew.WB:rate 0.421768 # insts written-back per cycle -system.cpu.iew.WB:sent 56969504 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 835772 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9640204 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11032857 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1798988 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1002562 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7014115 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65718389 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10403213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 554442 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57469408 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 44506 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26685206 # num instructions producing a value +system.cpu.iew.WB:rate 0.453347 # insts written-back per cycle +system.cpu.iew.WB:sent 56809510 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 839127 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9343071 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10818405 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1790311 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 888014 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6925516 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65053041 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10263638 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 522865 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57142298 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 63050 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6661 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1616629 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 544895 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 11753 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1512175 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 559162 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 306779 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 434666 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 127334 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 439799 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8819 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45591 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 18153 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1730940 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 625558 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45591 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 404736 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 431036 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.393404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.393404 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39532589 68.13% 68.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62065 0.11% 68.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25614 0.04% 68.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10774153 18.57% 86.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6665338 11.49% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953173 1.64% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 42451 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17646 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1515194 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 536005 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42451 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 406021 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 433106 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.424145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424145 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39339623 68.22% 68.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62341 0.11% 68.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10615152 18.41% 86.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6658629 11.55% 98.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 952896 1.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58023852 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 434401 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007487 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 57665165 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 433439 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007516 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 47887 11.02% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 281518 64.81% 75.83% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 104996 24.17% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 48806 11.26% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 267453 61.70% 72.97% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 117180 27.03% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 100234582 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.578881 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.146223 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 91019430 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.633548 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.199187 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 71270288 71.10% 71.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14553068 14.52% 85.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6335877 6.32% 91.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3893576 3.88% 95.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2543708 2.54% 98.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1056426 1.05% 99.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 441326 0.44% 99.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 109120 0.11% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 31193 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 62621832 68.80% 68.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14091892 15.48% 84.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6228717 6.84% 91.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3803889 4.18% 95.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2535360 2.79% 98.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1092488 1.20% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 467011 0.51% 99.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 127702 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 50539 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 100234582 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.430298 # Inst issue rate -system.cpu.iq.iqInstsAdded 60022452 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58023852 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2050443 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8631662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 41705 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1382702 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4647656 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 91019430 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.461001 # Inst issue rate +system.cpu.iq.iqInstsAdded 59425779 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 57665165 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2039714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8033204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 30047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1372081 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4119513 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1304111 # ITB accesses -system.cpu.itb.fetch_acv 934 # ITB acv -system.cpu.itb.fetch_hits 1264639 # ITB hits -system.cpu.itb.fetch_misses 39472 # ITB misses +system.cpu.itb.fetch_accesses 1291442 # ITB accesses +system.cpu.itb.fetch_acv 931 # ITB acv +system.cpu.itb.fetch_hits 1252390 # ITB hits +system.cpu.itb.fetch_misses 39052 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -456,55 +454,55 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175665 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::swpipl 175588 91.19% 93.39% # number of callpals executed system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5219 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5222 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192634 # number of callpals executed +system.cpu.kern.callpal::total 192558 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211790 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74955 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 237 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1888 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105930 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183010 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73588 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1888 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73588 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149301 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1823061244500 97.74% 97.74% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98162000 0.01% 97.74% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 391950000 0.02% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41736158500 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865287515000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981762 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211717 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6422 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74912 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 242 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105896 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182939 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73545 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 242 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73548 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149224 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1826190656000 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98153500 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 391767500 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39038852000 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865719429000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694685 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694530 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good::kernel 1909 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5970 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5960 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319765 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320302 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31031458000 1.66% 1.66% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3177312000 0.17% 1.83% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1831078737000 98.17% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401024 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 30084580500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3003065000 0.16% 1.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832631775500 98.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -536,29 +534,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3098880 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2694658 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11032857 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7014115 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 134845630 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14093810 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38225332 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1080811 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39441227 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2214917 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 14670 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83145881 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68419430 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45844130 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12603060 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1616629 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5180630 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7618796 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 27299224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1703562 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12710348 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 255623 # count of temporary serializing insts renamed -system.cpu.timesIdled 1320206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 2912046 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2554541 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 10818405 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6925516 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 125086888 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 13518840 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38230175 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1063400 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39070962 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1708241 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 58560 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 82154290 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 67531938 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45272379 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12498732 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1512175 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4709748 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7042202 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 19708971 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1694119 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 11797121 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 247227 # count of temporary serializing insts renamed +system.cpu.timesIdled 1311679 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -589,37 +587,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137804.625674 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137713.414661 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85801.092270 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5726057806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85709.809347 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5722267806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3565206986 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561413998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6169.984712 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.345934 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10466 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64575060 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137711.103751 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137620.270917 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85707.584997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85616.680551 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745995804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5742205804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -627,7 +625,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3576148984 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572355996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -635,20 +633,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.078725 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.259600 # Average occupied blocks per context +system.iocache.occ_%::1 0.081045 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.296712 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137711.103751 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137620.270917 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85707.584997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85616.680551 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5745995804 # number of overall miss cycles +system.iocache.overall_miss_latency 5742205804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -656,7 +654,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3576148984 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572355996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -666,156 +664,144 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.259600 # Cycle average of tags in use +system.iocache.tagsinuse 1.296712 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1715198512000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711281276000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300711 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300711 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52369.611662 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300943 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300943 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52461.384650 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40214.373242 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 2213 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 2213 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 15632224342 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.992641 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 298498 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 298498 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12003909984 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.992641 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40312.785193 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 183917 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183917 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6139346000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.388864 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 117026 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117026 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4717644000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.388864 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 298498 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2094821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2094821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52048.515602 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 117026 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2092753 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2092753 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52046.663805 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.565251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.758954 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1784931 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1784931 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16129314500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.147931 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 309890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309890 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12400383500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.147931 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1785277 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785277 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16003100000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.146924 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307476 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307476 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 12303885500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146924 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 309889 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810515000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 21199 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 21199 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 52327.059157 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000.731201 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 1109229000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.999953 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 21198 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21198 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 847935500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.999953 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 21198 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 69854 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 69854 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52150.764423 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 307476 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 811482500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_hits::0 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_accesses::0 27 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 20722.222222 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40013.263378 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 3642939498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 69854 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 69854 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 2795086500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 43333.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 373000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.666667 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 780000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.666667 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 69854 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 18 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1115590498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 455270 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 455270 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 455270 # number of Writeback hits -system.l2c.Writeback_hits::total 455270 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1115672498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 832936 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 832936 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 832936 # number of Writeback hits +system.l2c.Writeback_hits::total 832936 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.693284 # Average number of references to valid blocks. +system.l2c.avg_refs 5.637084 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2395532 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2393696 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2395532 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52206.057388 # average overall miss latency +system.l2c.demand_accesses::total 2393696 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52160.993352 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency -system.l2c.demand_hits::0 1787144 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40097.642650 # average overall mshr miss latency +system.l2c.demand_hits::0 1969194 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1787144 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31761538842 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.253968 # miss rate for demand accesses +system.l2c.demand_hits::total 1969194 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22142446000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.177342 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 608388 # number of demand (read+write) misses +system.l2c.demand_misses::0 424502 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 608388 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24404293484 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.253967 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 424502 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 17021529500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.177342 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 608387 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 424502 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.176515 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.325488 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 11568.063937 # Average occupied blocks per context -system.l2c.occ_blocks::1 21331.159568 # Average occupied blocks per context -system.l2c.overall_accesses::0 2395532 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.187192 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.344481 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12267.817300 # Average occupied blocks per context +system.l2c.occ_blocks::1 22575.879516 # Average occupied blocks per context +system.l2c.overall_accesses::0 2393696 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2395532 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52206.057388 # average overall miss latency +system.l2c.overall_accesses::total 2393696 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52160.993352 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40097.642650 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1787144 # number of overall hits +system.l2c.overall_hits::0 1969194 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1787144 # number of overall hits -system.l2c.overall_miss_latency 31761538842 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.253968 # miss rate for overall accesses +system.l2c.overall_hits::total 1969194 # number of overall hits +system.l2c.overall_miss_latency 22142446000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.177342 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 608388 # number of overall misses +system.l2c.overall_misses::0 424502 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 608388 # number of overall misses -system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24404293484 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.253967 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 424502 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 17021529500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.177342 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 608387 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926105498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 424502 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1927154998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 394069 # number of replacements -system.l2c.sampled_refs 426267 # Sample count of references to valid blocks. +system.l2c.replacements 391012 # number of replacements +system.l2c.sampled_refs 423751 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 32899.223505 # Cycle average of tags in use -system.l2c.total_refs 2000592 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5644310000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 118209 # number of writebacks +system.l2c.tagsinuse 34843.696815 # Cycle average of tags in use +system.l2c.total_refs 2388720 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 117653 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |