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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:28 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:28 -0500 |
commit | fea2c26402894aa26de7b7d8e14fe71070b76296 (patch) | |
tree | e0fda155959ce40d9528ef511c47ee851de516fb /tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr | |
parent | cefd6960e5312c27b613dcb783c66539baa0307d (diff) | |
download | gem5-fea2c26402894aa26de7b7d8e14fe71070b76296.tar.xz |
ARM: Update ARM_FS stats for mp changes
Diffstat (limited to 'tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr')
-rwxr-xr-x | tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr index 701e9297b..36f522422 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -8,16 +8,12 @@ warn: The clidr register always reports 0 caches. For more information see: http://www.m5sim.org/warn/23a3c326 warn: The csselr register isn't implemented. For more information see: http://www.m5sim.org/warn/c0c486b8 -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: The ccsidr register isn't implemented and always reads as 0. For more information see: http://www.m5sim.org/warn/2c4acb9c warn: instruction 'mcr dccimvac' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented @@ -36,8 +32,6 @@ warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Need to flush all TLBs in MP -For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb hack: be nice to actually delete the event here |