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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:20:22 -0500 |
| commit | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (patch) | |
| tree | f3dada322d407488b3081a6b9139948b42a610b3 /tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr | |
| parent | ccaaa98b4916f730e5eee0cb1d206dca21cb802d (diff) | |
| download | gem5-63eb337b3b93ab71ab3157ec6487901d4fc6cda6.tar.xz | |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
Diffstat (limited to 'tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr')
| -rwxr-xr-x | tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr new file mode 100755 index 000000000..701e9297b --- /dev/null +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -0,0 +1,43 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: The clidr register always reports 0 caches. +For more information see: http://www.m5sim.org/warn/23a3c326 +warn: The csselr register isn't implemented. +For more information see: http://www.m5sim.org/warn/c0c486b8 +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: The ccsidr register isn't implemented and always reads as 0. +For more information see: http://www.m5sim.org/warn/2c4acb9c +warn: instruction 'mcr dccimvac' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr dccmvau' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr icimvau' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +For more information see: http://www.m5sim.org/warn/7998f2ea +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +For more information see: http://www.m5sim.org/warn/7998f2ea +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +warn: Need to flush all TLBs in MP +For more information see: http://www.m5sim.org/warn/6cccf999 +warn: instruction 'mcr bpiall' unimplemented +For more information see: http://www.m5sim.org/warn/21b09adb +hack: be nice to actually delete the event here |