diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:23 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:23 -0800 |
| commit | d1dd7a24dbeec44a5de232549fa863ff597be349 (patch) | |
| tree | 83755e42e7507fd86f6f573d13570118dec9549e /tests/long/10.linux-boot/ref/arm/linux | |
| parent | 61c14da751ae80e8c19e0b63ddd629c4152f1c72 (diff) | |
| download | gem5-d1dd7a24dbeec44a5de232549fa863ff597be349.tar.xz | |
imported patch ext/stats_updates.patch
--HG--
extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
Diffstat (limited to 'tests/long/10.linux-boot/ref/arm/linux')
6 files changed, 1496 insertions, 1497 deletions
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 3a986614c..fb7470780 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index eb8b03237..caf37a67b 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout -Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:41:18 -gem5 started Aug 20 2011 15:46:02 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:32:34 +gem5 started Nov 22 2011 02:00:14 +gem5 executing on u200540-lin command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582520130500 because m5_exit instruction encountered +Exiting @ tick 2582494395500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b36a36f09..fc137bfb1 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582520 # Number of seconds simulated -sim_ticks 2582520130500 # Number of ticks simulated +sim_seconds 2.582494 # Number of seconds simulated +sim_ticks 2582494395500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84908 # Simulator instruction rate (inst/s) -host_tick_rate 2745493933 # Simulator tick rate (ticks/s) -host_mem_usage 385348 # Number of bytes of host memory used -host_seconds 940.64 # Real time elapsed on the host -sim_insts 79867485 # Number of instructions simulated -system.l2c.replacements 132224 # number of replacements -system.l2c.tagsinuse 27582.981749 # Cycle average of tags in use -system.l2c.total_refs 1821382 # Total number of references to valid blocks. -system.l2c.sampled_refs 162180 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.230620 # Average number of references to valid blocks. +host_inst_rate 86259 # Simulator instruction rate (inst/s) +host_tick_rate 2789337609 # Simulator tick rate (ticks/s) +host_mem_usage 380504 # Number of bytes of host memory used +host_seconds 925.85 # Real time elapsed on the host +sim_insts 79862069 # Number of instructions simulated +system.l2c.replacements 132200 # number of replacements +system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use +system.l2c.total_refs 1817822 # Total number of references to valid blocks. +system.l2c.sampled_refs 162144 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.211158 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 5000.765535 # Average occupied blocks per context -system.l2c.occ_blocks::1 7177.119061 # Average occupied blocks per context -system.l2c.occ_blocks::2 15405.097153 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076306 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.109514 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.235063 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 739666 # number of ReadReq hits -system.l2c.ReadReq_hits::1 629011 # number of ReadReq hits -system.l2c.ReadReq_hits::2 183263 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1551940 # number of ReadReq hits -system.l2c.Writeback_hits::0 599118 # number of Writeback hits -system.l2c.Writeback_hits::total 599118 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1040 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 1060 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2100 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 181 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 449 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 630 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 58369 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 39072 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97441 # number of ReadExReq hits -system.l2c.demand_hits::0 798035 # number of demand (read+write) hits -system.l2c.demand_hits::1 668083 # number of demand (read+write) hits -system.l2c.demand_hits::2 183263 # number of demand (read+write) hits -system.l2c.demand_hits::total 1649381 # number of demand (read+write) hits -system.l2c.overall_hits::0 798035 # number of overall hits -system.l2c.overall_hits::1 668083 # number of overall hits -system.l2c.overall_hits::2 183263 # number of overall hits -system.l2c.overall_hits::total 1649381 # number of overall hits -system.l2c.ReadReq_misses::0 19689 # number of ReadReq misses -system.l2c.ReadReq_misses::1 20600 # number of ReadReq misses -system.l2c.ReadReq_misses::2 170 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40459 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7392 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3836 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11228 # number of UpgradeReq misses +system.l2c.occ_blocks::0 5000.897751 # Average occupied blocks per context +system.l2c.occ_blocks::1 7176.831699 # Average occupied blocks per context +system.l2c.occ_blocks::2 15405.259775 # Average occupied blocks per context +system.l2c.occ_percent::0 0.076308 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.109510 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.235066 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 738573 # number of ReadReq hits +system.l2c.ReadReq_hits::1 628212 # number of ReadReq hits +system.l2c.ReadReq_hits::2 178875 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1545660 # number of ReadReq hits +system.l2c.Writeback_hits::0 598786 # number of Writeback hits +system.l2c.Writeback_hits::total 598786 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 1039 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1048 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2087 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 451 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 626 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 58347 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 39083 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 97430 # number of ReadExReq hits +system.l2c.demand_hits::0 796920 # number of demand (read+write) hits +system.l2c.demand_hits::1 667295 # number of demand (read+write) hits +system.l2c.demand_hits::2 178875 # number of demand (read+write) hits +system.l2c.demand_hits::total 1643090 # number of demand (read+write) hits +system.l2c.overall_hits::0 796920 # number of overall hits +system.l2c.overall_hits::1 667295 # number of overall hits +system.l2c.overall_hits::2 178875 # number of overall hits +system.l2c.overall_hits::total 1643090 # number of overall hits +system.l2c.ReadReq_misses::0 19694 # number of ReadReq misses +system.l2c.ReadReq_misses::1 20569 # number of ReadReq misses +system.l2c.ReadReq_misses::2 168 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40431 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 7390 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3840 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11230 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 461 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1325 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 98007 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 50222 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148229 # number of ReadExReq misses -system.l2c.demand_misses::0 117696 # number of demand (read+write) misses -system.l2c.demand_misses::1 70822 # number of demand (read+write) misses -system.l2c.demand_misses::2 170 # number of demand (read+write) misses -system.l2c.demand_misses::total 188688 # number of demand (read+write) misses -system.l2c.overall_misses::0 117696 # number of overall misses -system.l2c.overall_misses::1 70822 # number of overall misses -system.l2c.overall_misses::2 170 # number of overall misses -system.l2c.overall_misses::total 188688 # number of overall misses -system.l2c.ReadReq_miss_latency 2113875000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 61547500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 8091500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7780940999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9894815999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9894815999 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 759355 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 649611 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 183433 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1592399 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 599118 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 599118 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8432 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4896 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13328 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1045 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 910 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1955 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 156376 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 89294 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245670 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 915731 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 738905 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 183433 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1838069 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 915731 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 738905 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 183433 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1838069 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025929 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031711 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000927 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.058567 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.876660 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.783497 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.826794 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.506593 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.626739 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.562434 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.128527 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.095847 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000927 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.225301 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.128527 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.095847 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000927 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.225301 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 107363.248514 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 102615.291262 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 12434558.823529 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12644537.363306 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8326.231061 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 16044.708029 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_misses::1 454 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1318 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 97999 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 50217 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148216 # number of ReadExReq misses +system.l2c.demand_misses::0 117693 # number of demand (read+write) misses +system.l2c.demand_misses::1 70786 # number of demand (read+write) misses +system.l2c.demand_misses::2 168 # number of demand (read+write) misses +system.l2c.demand_misses::total 188647 # number of demand (read+write) misses +system.l2c.overall_misses::0 117693 # number of overall misses +system.l2c.overall_misses::1 70786 # number of overall misses +system.l2c.overall_misses::2 168 # number of overall misses +system.l2c.overall_misses::total 188647 # number of overall misses +system.l2c.ReadReq_miss_latency 2112279500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 61500500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 8037000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7780237999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9892517499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9892517499 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 758267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 648781 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 179043 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1586091 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 598786 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 598786 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 8429 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4888 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13317 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1039 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 905 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1944 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 156346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 89300 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245646 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 914613 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 738081 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 179043 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1831737 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 914613 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 738081 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 179043 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1831737 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.025972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.031704 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.000938 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.058615 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.876735 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.785597 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.831569 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.501657 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.626808 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.562340 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.128681 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.095905 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.000938 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.225524 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.128681 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.095905 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.000938 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.225524 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 107254.976135 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 102692.376878 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 12573092.261905 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12783039.614917 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8322.124493 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 16015.755208 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9365.162037 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17552.060738 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 9302.083333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17702.643172 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79391.686298 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 154930.926666 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 79390.993775 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 154932.353566 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 84070.962471 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 139713.874206 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 58204799.994118 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 58428584.830795 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 84070.962471 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 139713.874206 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 58204799.994118 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 58428584.830795 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 84053.575820 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 139752.458099 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 58884032.732143 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 59107838.766062 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 84053.575820 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 139752.458099 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 58884032.732143 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 59107838.766062 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,56 +143,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 112853 # number of writebacks -system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 40365 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 11228 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1325 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148229 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 188594 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 188594 # number of overall MSHR misses +system.l2c.writebacks 112847 # number of writebacks +system.l2c.ReadReq_mshr_hits 98 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 98 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 98 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 40333 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 11230 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1318 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 148216 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 188549 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 188549 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1617473000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 449580000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 53034500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5939516999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7556989999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7556989999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131965465500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32542103084 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164507568584 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.053157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.062137 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.220053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.335347 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.331594 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.293301 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1616144000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 449664000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 52753500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5939088499 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7555232499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7555232499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131965191500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32542078084 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164507269584 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.053191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.062167 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.225270 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.340628 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.332305 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.297463 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.267943 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456044 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.268527 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456354 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.947901 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.660011 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.948000 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.659754 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.205949 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.255234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.028136 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.489319 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.205949 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.255234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.028136 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.489319 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40071.175523 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40040.969006 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40026.037736 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40069.871611 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.206152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.255458 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.053093 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.514703 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.206152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.255458 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.053093 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.514703 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40070.017108 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40041.317898 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40025.417299 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40070.495082 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -207,27 +207,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 42414340 # DTB read hits -system.cpu0.dtb.read_misses 56223 # DTB read misses -system.cpu0.dtb.write_hits 6898086 # DTB write hits -system.cpu0.dtb.write_misses 11305 # DTB write misses +system.cpu0.dtb.read_hits 42404013 # DTB read hits +system.cpu0.dtb.read_misses 55271 # DTB read misses +system.cpu0.dtb.write_hits 6896316 # DTB write hits +system.cpu0.dtb.write_misses 11117 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2713 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 11513 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 590 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 10190 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 580 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1641 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 42470563 # DTB read accesses -system.cpu0.dtb.write_accesses 6909391 # DTB write accesses +system.cpu0.dtb.perms_faults 1489 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 42459284 # DTB read accesses +system.cpu0.dtb.write_accesses 6907433 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 49312426 # DTB hits -system.cpu0.dtb.misses 67528 # DTB misses -system.cpu0.dtb.accesses 49379954 # DTB accesses -system.cpu0.itb.inst_hits 6438737 # ITB inst hits -system.cpu0.itb.inst_misses 18334 # ITB inst misses +system.cpu0.dtb.hits 49300329 # DTB hits +system.cpu0.dtb.misses 66388 # DTB misses +system.cpu0.dtb.accesses 49366717 # DTB accesses +system.cpu0.itb.inst_hits 6430047 # ITB inst hits +system.cpu0.itb.inst_misses 17344 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -236,122 +236,122 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1577 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 6092 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 5810 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6457071 # ITB inst accesses -system.cpu0.itb.hits 6438737 # DTB hits -system.cpu0.itb.misses 18334 # DTB misses -system.cpu0.itb.accesses 6457071 # DTB accesses -system.cpu0.numCycles 352502516 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6447391 # ITB inst accesses +system.cpu0.itb.hits 6430047 # DTB hits +system.cpu0.itb.misses 17344 # DTB misses +system.cpu0.itb.accesses 6447391 # DTB accesses +system.cpu0.numCycles 352464224 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 8652992 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6404778 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 637693 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7363134 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5053345 # Number of BTB hits +system.cpu0.BPredUnit.lookups 8639262 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 6396113 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 634960 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7354016 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5046946 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 807352 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 136692 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16884109 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45966993 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8652992 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5860697 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11522341 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2668103 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 112168 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 79167270 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 2014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 119305 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 115037 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6432455 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 291981 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 9711 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109779148 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.541337 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.795461 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 806008 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 135144 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 16864575 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45911459 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8639262 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5852954 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11507352 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2656909 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 105092 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 79183942 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 2005 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 114543 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 115021 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6424056 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 290090 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 8736 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 109741052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.540842 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.794710 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98275003 89.52% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1141137 1.04% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1489424 1.36% 91.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1304085 1.19% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1112037 1.01% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 879763 0.80% 94.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 783842 0.71% 95.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 505631 0.46% 96.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4288226 3.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98251365 89.53% 89.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 1141553 1.04% 90.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1483062 1.35% 91.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1305311 1.19% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1111109 1.01% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 877492 0.80% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 783730 0.71% 95.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 504789 0.46% 96.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4282641 3.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109779148 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.024547 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.130402 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18050945 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78849390 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10366657 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 743574 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1768582 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1352275 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89418 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56923097 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 298418 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1768582 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 19113011 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33326039 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41047359 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10060323 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4463834 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54560689 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1472 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 580904 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3150021 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 227 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54846534 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 247844774 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 247794895 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 49879 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41443860 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13402673 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 827250 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 762254 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8494444 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 11787351 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7696820 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1444181 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1562010 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51022975 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1296408 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80307756 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 139273 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9946263 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22977035 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 252908 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109779148 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731539 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.440195 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109741052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.024511 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.130258 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18015904 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78867966 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10351735 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 744902 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1760545 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1349765 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89024 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56859019 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 296865 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1760545 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19077781 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 33324855 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 41068350 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10047301 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4462220 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54490886 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1483 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54779836 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13338678 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 11770384 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50961906 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1297751 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80276175 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 253323 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 80155628 73.02% 73.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10112206 9.21% 82.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4137187 3.77% 86.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3171994 2.89% 88.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9961890 9.07% 97.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1265964 1.15% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 671041 0.61% 99.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224336 0.20% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 78902 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 80125799 73.01% 73.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9954077 9.07% 97.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1265280 1.15% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109779148 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109741052 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 37945 0.47% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 630 0.01% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 37808 0.47% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available @@ -379,373 +379,374 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7705227 95.96% 96.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285473 3.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 7704393 95.96% 96.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 285533 3.56% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29747563 37.04% 37.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 62367 0.08% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 4 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1707 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29731482 37.04% 37.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1694 0.00% 37.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 43146000 53.73% 90.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7261641 9.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 43135014 53.73% 90.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80307756 # Type of FU issued -system.cpu0.iq.rate 0.227822 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8029275 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.099981 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278618763 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62278383 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46688761 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11606 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7153 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5243 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88242529 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6041 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 399833 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 80276175 # Type of FU issued +system.cpu0.iq.rate 0.227757 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 278513866 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46668616 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 88210043 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2542386 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5153 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20600 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1003035 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2526229 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5188 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20554 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 993550 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 32220164 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13264 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 32220160 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 13300 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1768582 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25955516 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 355771 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 52493661 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 246498 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 11787351 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7696820 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 864266 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62537 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20600 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 509776 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 136927 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 646703 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79579333 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 42855337 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 728423 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1760545 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 25952608 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 355602 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 52433539 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 865739 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 79551296 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174278 # number of nop insts executed -system.cpu0.iew.exec_refs 50025973 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6436853 # Number of branches executed -system.cpu0.iew.exec_stores 7170636 # Number of stores executed -system.cpu0.iew.exec_rate 0.225755 # Inst execution rate -system.cpu0.iew.wb_sent 79157088 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46694004 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24804627 # num instructions producing a value -system.cpu0.iew.wb_consumers 46107956 # num instructions consuming a value +system.cpu0.iew.exec_nop 173882 # number of nop insts executed +system.cpu0.iew.exec_refs 50011427 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6433542 # Number of branches executed +system.cpu0.iew.exec_stores 7167520 # Number of stores executed +system.cpu0.iew.exec_rate 0.225700 # Inst execution rate +system.cpu0.iew.wb_sent 79133798 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46673788 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24793926 # num instructions producing a value +system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.132464 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.537968 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.132421 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.538081 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 41930270 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 10408005 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1043500 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 570177 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 108054182 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.388049 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.248702 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 41927345 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 10365163 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1044428 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567784 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 108024119 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.388129 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.248779 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 91026362 84.24% 84.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 9315133 8.62% 92.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2453841 2.27% 95.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1345650 1.25% 96.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1029771 0.95% 97.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 653477 0.60% 97.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 658529 0.61% 98.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 238490 0.22% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1332929 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90994296 84.24% 84.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 9318293 8.63% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2453548 2.27% 95.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1344047 1.24% 96.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1036100 0.96% 97.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 648919 0.60% 97.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 654404 0.61% 98.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241700 0.22% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1332812 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 108054182 # Number of insts commited each cycle -system.cpu0.commit.count 41930270 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 108024119 # Number of insts commited each cycle +system.cpu0.commit.count 41927345 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 15938750 # Number of memory references committed -system.cpu0.commit.loads 9244965 # Number of loads committed -system.cpu0.commit.membars 288660 # Number of memory barriers committed -system.cpu0.commit.branches 5543054 # Number of branches committed -system.cpu0.commit.fp_insts 4980 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37176133 # Number of committed integer instructions. -system.cpu0.commit.function_calls 620334 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1332929 # number cycles where commit BW limit reached +system.cpu0.commit.refs 15937410 # Number of memory references committed +system.cpu0.commit.loads 9244155 # Number of loads committed +system.cpu0.commit.membars 288635 # Number of memory barriers committed +system.cpu0.commit.branches 5542672 # Number of branches committed +system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 37173454 # Number of committed integer instructions. +system.cpu0.commit.function_calls 620264 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1332812 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 157975997 # The number of ROB reads -system.cpu0.rob.rob_writes 106454954 # The number of ROB writes -system.cpu0.timesIdled 1454281 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 242723368 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 41804443 # Number of Instructions Simulated -system.cpu0.committedInsts_total 41804443 # Number of Instructions Simulated -system.cpu0.cpi 8.432178 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.432178 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.118593 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.118593 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354304839 # number of integer regfile reads -system.cpu0.int_regfile_writes 46156049 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 1342 # number of floating regfile writes -system.cpu0.misc_regfile_reads 65708495 # number of misc regfile reads -system.cpu0.misc_regfile_writes 636034 # number of misc regfile writes -system.cpu0.icache.replacements 540132 # number of replacements -system.cpu0.icache.tagsinuse 511.623908 # Cycle average of tags in use -system.cpu0.icache.total_refs 5846805 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 540644 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.814519 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 157900366 # The number of ROB reads +system.cpu0.rob.rob_writes 106355397 # The number of ROB writes +system.cpu0.timesIdled 1453890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 242723172 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 4812468828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41801518 # Number of Instructions Simulated +system.cpu0.committedInsts_total 41801518 # Number of Instructions Simulated +system.cpu0.cpi 8.431852 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 354175082 # number of integer regfile reads +system.cpu0.int_regfile_writes 46137252 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads +system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes +system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads +system.cpu0.misc_regfile_writes 635954 # number of misc regfile writes +system.cpu0.icache.replacements 539173 # number of replacements +system.cpu0.icache.tagsinuse 511.623608 # Cycle average of tags in use +system.cpu0.icache.total_refs 5839899 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 539685 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.820940 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.623908 # Average occupied blocks per context +system.cpu0.icache.occ_blocks::0 511.623608 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5846805 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5846805 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5846805 # number of demand (read+write) hits +system.cpu0.icache.ReadReq_hits::0 5839899 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5839899 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5839899 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5846805 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5846805 # number of overall hits +system.cpu0.icache.demand_hits::total 5839899 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5839899 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5846805 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 585522 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 585522 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 585522 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 5839899 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 584029 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 584029 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 584029 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 585522 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 585522 # number of overall misses +system.cpu0.icache.demand_misses::total 584029 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 584029 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 585522 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 8762208993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 8762208993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 8762208993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 6432327 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6432327 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 6432327 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 584029 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 8742056490 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 8742056490 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 8742056490 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6423928 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6423928 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6423928 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6432327 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 6432327 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 6423928 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6423928 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6432327 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.091028 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.091028 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 6423928 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.090915 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.090915 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.091028 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.090915 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14964.781841 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14968.531511 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14964.781841 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14968.531511 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14964.781841 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14968.531511 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1480495 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1586493 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 196 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7553.545918 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7554.728571 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 29912 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 44859 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 44859 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 44859 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 540663 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 540663 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 540663 # number of overall MSHR misses +system.cpu0.icache.writebacks 29902 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 44323 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 44323 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 44323 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 539706 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 539706 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 539706 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 6562850995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 6562850995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 6562850995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 6552393493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 6552393493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 6552393493 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084054 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084015 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.084054 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.084015 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.084054 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.084015 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.524358 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12140.671945 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12140.671945 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 372646 # number of replacements -system.cpu0.dcache.tagsinuse 487.071508 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12784845 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 373158 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.261211 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 372215 # number of replacements +system.cpu0.dcache.tagsinuse 487.071305 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12774859 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 372727 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.274037 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 487.071508 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.951312 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7969031 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7969031 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4348200 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4348200 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 221332 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 221332 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 199760 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199760 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12317231 # number of demand (read+write) hits +system.cpu0.dcache.occ_blocks::0 487.071305 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.951311 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 7959466 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7959466 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 4347928 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4347928 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 221270 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 221270 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 199751 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199751 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 12307394 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12317231 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12317231 # number of overall hits +system.cpu0.dcache.demand_hits::total 12307394 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 12307394 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 12317231 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 463423 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463423 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1863605 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1863605 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9962 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9962 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7780 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 2327028 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 12307394 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 462880 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 462880 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1863380 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1863380 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 9956 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9956 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 7770 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7770 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 2326260 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2327028 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 2327028 # number of overall misses +system.cpu0.dcache.demand_misses::total 2326260 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 2326260 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2327028 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 6461559500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 70508741836 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 120808500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 88519000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 76970301336 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 76970301336 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8432454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8432454 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6211805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6211805 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 231294 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 231294 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 207540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 207540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14644259 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 2326260 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 6451753000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 70471171342 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 120838000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 88450500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 76922924342 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 76922924342 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8422346 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8422346 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6211308 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6211308 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 231226 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 231226 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 207521 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 207521 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14633654 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14644259 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14644259 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14633654 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14633654 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14644259 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.054957 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.300010 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043071 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037487 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.158904 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14633654 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.054959 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.299998 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043057 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037442 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.158966 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.158904 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.158966 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 13943.113527 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 13938.284221 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37834.595763 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 37819.001675 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12126.932343 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12137.203696 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11377.763496 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11383.590734 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 33076.654572 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 33067.208456 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 33076.654572 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 33067.208456 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6713488 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1808000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 859 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 6759989 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1802000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 868 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7815.469150 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 14699.186992 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7788.005760 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 14650.406504 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 327128 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 223214 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1685177 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 329 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1908391 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1908391 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 240209 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 178428 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7778 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 418637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 418637 # number of overall MSHR misses +system.cpu0.dcache.writebacks 326934 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 223096 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1684995 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1908091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1908091 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 239784 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 178385 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9630 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 7769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 418169 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 418169 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2943893000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6377983487 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86869500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9321876487 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9321876487 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959490000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038770484 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 139998260484 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028486 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 2937322500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6377417488 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86877000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65112500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 9314739988 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 9314739988 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038732984 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 139998111984 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028719 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037477 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037437 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028587 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.028576 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028587 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.028576 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12255.548293 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35745.418247 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9017.907194 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8376.832091 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12249.868632 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35750.861833 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9021.495327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8381.065774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -754,27 +755,27 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10576986 # DTB read hits -system.cpu1.dtb.read_misses 41991 # DTB read misses -system.cpu1.dtb.write_hits 5532460 # DTB write hits -system.cpu1.dtb.write_misses 15559 # DTB write misses +system.cpu1.dtb.read_hits 10573739 # DTB read hits +system.cpu1.dtb.read_misses 42015 # DTB read misses +system.cpu1.dtb.write_hits 5529871 # DTB write hits +system.cpu1.dtb.write_misses 15191 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 5132 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1927 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3403 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 787 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10618977 # DTB read accesses -system.cpu1.dtb.write_accesses 5548019 # DTB write accesses +system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10615754 # DTB read accesses +system.cpu1.dtb.write_accesses 5545062 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16109446 # DTB hits -system.cpu1.dtb.misses 57550 # DTB misses -system.cpu1.dtb.accesses 16166996 # DTB accesses -system.cpu1.itb.inst_hits 8208666 # ITB inst hits -system.cpu1.itb.inst_misses 3757 # ITB inst misses +system.cpu1.dtb.hits 16103610 # DTB hits +system.cpu1.dtb.misses 57206 # DTB misses +system.cpu1.dtb.accesses 16160816 # DTB accesses +system.cpu1.itb.inst_hits 8206065 # ITB inst hits +system.cpu1.itb.inst_misses 3031 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -783,122 +784,122 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1367 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2255 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2156 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8212423 # ITB inst accesses -system.cpu1.itb.hits 8208666 # DTB hits -system.cpu1.itb.misses 3757 # DTB misses -system.cpu1.itb.accesses 8212423 # DTB accesses -system.cpu1.numCycles 69081256 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8209096 # ITB inst accesses +system.cpu1.itb.hits 8206065 # DTB hits +system.cpu1.itb.misses 3031 # DTB misses +system.cpu1.itb.accesses 8209096 # DTB accesses +system.cpu1.numCycles 69056369 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 8330796 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6738871 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 503522 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7267639 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5704343 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8325282 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 6737041 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 502555 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7261407 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5699060 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 683793 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 107847 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 17620797 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62561411 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8330796 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6388136 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13917594 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4639299 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 49548 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 15790396 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 3022 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 34407 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 125274 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 237 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8206050 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 760093 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2394 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 50674659 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.494403 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.744832 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 682916 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 107380 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 17608500 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 62544782 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8325282 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6381976 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13909998 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4633998 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 45331 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 15806576 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 3075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 32937 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 125179 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8203545 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 759342 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1683 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 50660963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.494360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.745003 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 36764920 72.55% 72.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 704096 1.39% 73.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1222881 2.41% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2516311 4.97% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1142608 2.25% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 651052 1.28% 84.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1887369 3.72% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 403735 0.80% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5381687 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 36758800 72.56% 72.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 702781 1.39% 73.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1220162 2.41% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2515175 4.96% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1141377 2.25% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 650709 1.28% 84.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1886656 3.72% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 404310 0.80% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5380993 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 50674659 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.120594 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.905621 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18672830 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16053118 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12511393 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 382905 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3054413 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1082178 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 80433 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69756936 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 260341 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3054413 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19817710 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3624621 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 10850261 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11740016 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1587638 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63840108 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3002 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 319994 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 862075 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 38212 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 68266339 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 296265404 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 296212618 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52786 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39108942 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29157397 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 433648 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 381432 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4194062 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11085935 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7020391 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 635108 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 890373 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 56044948 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 651331 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 50360925 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 120514 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18223761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52593424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 131996 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 50674659 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.993809 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.617399 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 50660963 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.120558 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.905706 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18651451 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16071797 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12503703 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 383683 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3050329 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1080503 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 80301 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69737045 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 259727 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3050329 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19796555 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3624603 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 10867059 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11733074 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1589343 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63809564 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2981 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 320281 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 864112 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 38202 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 68239803 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 296124940 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 296072200 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52740 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39106608 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29133195 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 434621 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 382462 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4203927 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11080202 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7013216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 634211 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 885799 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 56015216 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 652114 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 50333331 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 120412 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18201885 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52559759 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 132486 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 50660963 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.993533 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.617126 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 32153473 63.45% 63.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5526378 10.91% 74.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3775422 7.45% 81.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3611274 7.13% 88.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2989508 5.90% 94.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1557590 3.07% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 784960 1.55% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 214293 0.42% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61761 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 32144545 63.45% 63.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5530112 10.92% 74.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3775848 7.45% 81.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3605586 7.12% 88.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2986827 5.90% 94.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1557942 3.08% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 784538 1.55% 99.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 214001 0.42% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61564 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 50674659 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 50660963 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 15522 1.51% 1.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1191 0.12% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 15475 1.52% 1.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1190 0.12% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available @@ -926,373 +927,374 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 749386 73.14% 74.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 258502 25.23% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 748820 73.38% 75.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 254917 24.98% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32758484 65.05% 65.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 50347 0.10% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 759 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32741822 65.05% 65.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 50334 0.10% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.19% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11614499 23.06% 88.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5918207 11.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11609954 23.07% 88.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5911828 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 50360925 # Type of FU issued -system.cpu1.iq.rate 0.729010 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1024601 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020345 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 152586143 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 74924785 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 44270347 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12757 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7087 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5824 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 51360226 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6678 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 266055 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 50333331 # Type of FU issued +system.cpu1.iq.rate 0.728873 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1020402 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020273 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 152512648 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 74873900 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 44249478 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12744 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7082 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5800 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 51328452 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6659 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 264599 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3973405 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7375 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 12287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1481060 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3968304 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7379 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 12210 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1474293 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1850150 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1139659 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 1850149 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1139663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3054413 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2505400 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 71046 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56747555 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 255776 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11085935 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7020391 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 408110 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28416 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3434 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 12287 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 384769 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 125659 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 510428 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 47569274 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10848117 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2791651 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3050329 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2505738 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 70750 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56718238 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 255272 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11080202 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7013216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 408861 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28043 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3317 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 12210 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 383709 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 125709 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 509418 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 47546383 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10844490 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2786948 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 51276 # number of nop insts executed -system.cpu1.iew.exec_refs 16673626 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5809146 # Number of branches executed -system.cpu1.iew.exec_stores 5825509 # Number of stores executed -system.cpu1.iew.exec_rate 0.688599 # Inst execution rate -system.cpu1.iew.wb_sent 46311223 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 44276171 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24275566 # num instructions producing a value -system.cpu1.iew.wb_consumers 44463888 # num instructions consuming a value +system.cpu1.iew.exec_nop 50908 # number of nop insts executed +system.cpu1.iew.exec_refs 16665607 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5805305 # Number of branches executed +system.cpu1.iew.exec_stores 5821117 # Number of stores executed +system.cpu1.iew.exec_rate 0.688516 # Inst execution rate +system.cpu1.iew.wb_sent 46287732 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 44255278 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24264943 # num instructions producing a value +system.cpu1.iew.wb_consumers 44435618 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.640929 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545961 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.640857 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.546070 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38087596 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18562736 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 519335 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 450588 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 47661477 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.799127 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.835707 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38085105 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18540440 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 519628 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 449695 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 47651856 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.799237 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835547 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 34693281 72.79% 72.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6099066 12.80% 85.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1834262 3.85% 89.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 962147 2.02% 91.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 825706 1.73% 93.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 739217 1.55% 94.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 588574 1.23% 95.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 450580 0.95% 96.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1468644 3.08% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 34686600 72.79% 72.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6094128 12.79% 85.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1835097 3.85% 89.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 960943 2.02% 91.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 825753 1.73% 93.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 740854 1.55% 94.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 593786 1.25% 95.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 449604 0.94% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1465091 3.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 47661477 # Number of insts commited each cycle -system.cpu1.commit.count 38087596 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 47651856 # Number of insts commited each cycle +system.cpu1.commit.count 38085105 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 12651861 # Number of memory references committed -system.cpu1.commit.loads 7112530 # Number of loads committed -system.cpu1.commit.membars 148745 # Number of memory barriers committed -system.cpu1.commit.branches 4804762 # Number of branches committed +system.cpu1.commit.refs 12650821 # Number of memory references committed +system.cpu1.commit.loads 7111898 # Number of loads committed +system.cpu1.commit.membars 148710 # Number of memory barriers committed +system.cpu1.commit.branches 4804442 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34029989 # Number of committed integer instructions. -system.cpu1.commit.function_calls 433336 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1468644 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 34027730 # Number of committed integer instructions. +system.cpu1.commit.function_calls 433273 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1465091 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 102084600 # The number of ROB reads -system.cpu1.rob.rob_writes 116474424 # The number of ROB writes -system.cpu1.timesIdled 450576 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18406597 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 38063042 # Number of Instructions Simulated -system.cpu1.committedInsts_total 38063042 # Number of Instructions Simulated -system.cpu1.cpi 1.814917 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.814917 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550989 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550989 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 222881114 # number of integer regfile reads -system.cpu1.int_regfile_writes 47167594 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4241 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1808 # number of floating regfile writes -system.cpu1.misc_regfile_reads 77248425 # number of misc regfile reads -system.cpu1.misc_regfile_writes 323332 # number of misc regfile writes -system.cpu1.icache.replacements 486491 # number of replacements -system.cpu1.icache.tagsinuse 498.789046 # Cycle average of tags in use -system.cpu1.icache.total_refs 7677673 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 487003 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 15.765145 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 102053926 # The number of ROB reads +system.cpu1.rob.rob_writes 116420763 # The number of ROB writes +system.cpu1.timesIdled 449905 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18395406 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5095165422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38060551 # Number of Instructions Simulated +system.cpu1.committedInsts_total 38060551 # Number of Instructions Simulated +system.cpu1.cpi 1.814382 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.814382 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551152 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551152 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 222777169 # number of integer regfile reads +system.cpu1.int_regfile_writes 47147395 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4225 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1812 # number of floating regfile writes +system.cpu1.misc_regfile_reads 77230796 # number of misc regfile reads +system.cpu1.misc_regfile_writes 323252 # number of misc regfile writes +system.cpu1.icache.replacements 485904 # number of replacements +system.cpu1.icache.tagsinuse 498.788757 # Cycle average of tags in use +system.cpu1.icache.total_refs 7675789 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 486416 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 15.780297 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.789046 # Average occupied blocks per context +system.cpu1.icache.occ_blocks::0 498.788757 # Average occupied blocks per context system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7677673 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7677673 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7677673 # number of demand (read+write) hits +system.cpu1.icache.ReadReq_hits::0 7675789 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7675789 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 7675789 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7677673 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7677673 # number of overall hits +system.cpu1.icache.demand_hits::total 7675789 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 7675789 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 7677673 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 528325 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 528325 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 528325 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 7675789 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 527703 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 527703 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 527703 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 528325 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 528325 # number of overall misses +system.cpu1.icache.demand_misses::total 527703 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 527703 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 528325 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7771273996 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7771273996 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7771273996 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 8205998 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8205998 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 8205998 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 527703 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7760328997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7760328997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7760328997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 8203492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8203492 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 8203492 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8205998 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 8205998 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 8203492 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 8203492 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8205998 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.064383 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.064383 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 8203492 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.064327 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.064327 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.064383 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.064327 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14709.267962 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14705.864846 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14709.267962 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14705.864846 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14709.267962 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14705.864846 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1184497 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 1243497 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 157 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7544.566879 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7446.089820 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18578 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 41295 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 41295 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 41295 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 487030 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 487030 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 487030 # number of overall MSHR misses +system.cpu1.icache.writebacks 18536 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 41257 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 41257 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 41257 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 486446 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 486446 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 486446 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5811540497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5811540497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5811540497 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5802515997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5802515997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5802515997 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059350 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059297 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.059350 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.059297 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.059350 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.059297 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11932.612975 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11928.386701 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 272380 # number of replacements -system.cpu1.dcache.tagsinuse 444.916025 # Cycle average of tags in use -system.cpu1.dcache.total_refs 10412119 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 272723 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 38.178368 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 272184 # number of replacements +system.cpu1.dcache.tagsinuse 444.922817 # Cycle average of tags in use +system.cpu1.dcache.total_refs 10410516 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 272526 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 38.200084 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 66749899000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 444.916025 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.868977 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 7081898 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7081898 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3139500 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3139500 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 75302 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75302 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 72598 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72598 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 10221398 # number of demand (read+write) hits +system.cpu1.dcache.occ_blocks::0 444.922817 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.868990 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 7080702 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7080702 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 3139041 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3139041 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 75297 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 75297 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 72589 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72589 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 10219743 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10221398 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 10221398 # number of overall hits +system.cpu1.dcache.demand_hits::total 10219743 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 10219743 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 10221398 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 324241 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 324241 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 1274343 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1274343 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 12700 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12700 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 11096 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 11096 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1598584 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 10219743 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 323641 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 323641 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 1274421 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1274421 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 12692 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 12692 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 11088 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 11088 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 1598062 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1598584 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1598584 # number of overall misses +system.cpu1.dcache.demand_misses::total 1598062 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 1598062 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1598584 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 5065302500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 46249656862 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 148116500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 88362500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 51314959362 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 51314959362 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 7406139 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7406139 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 4413843 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4413843 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 88002 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 88002 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 83694 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83694 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11819982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 1598062 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 5056918000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 46262292366 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 147873000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 87994000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 51319210366 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 51319210366 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 7404343 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7404343 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 4413462 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4413462 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 87989 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87989 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 83677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 11817805 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11819982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11819982 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11817805 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 11817805 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11819982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.043780 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.288715 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144315 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132578 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.135244 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 11817805 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.043710 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.288758 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144245 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132510 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.135225 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.135244 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.135225 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15622.029601 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15625.084584 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36292.942216 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 36300.635635 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11662.716535 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11650.882446 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7963.455299 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7935.966811 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32100.258330 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 32113.403839 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32100.258330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 32113.403839 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 13378551 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5449500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3082 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4340.866645 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34710.191083 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 13353050 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5461500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3087 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4325.574992 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34134.375000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 223500 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 134561 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1158019 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 988 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1292580 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1292580 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 189680 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 116324 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11712 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 11095 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 306004 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 306004 # number of overall MSHR misses +system.cpu1.dcache.writebacks 223414 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 134188 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 1158095 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 989 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 1292283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 1292283 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 189453 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 116326 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 11703 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 11087 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 305779 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 305779 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2497244500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3447430551 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 55002000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5944675051 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5944675051 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455396000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503639517 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49959035517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025611 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2493574500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 3446976050 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 98971000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54655500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 5940550550 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 5940550550 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455171000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503599517 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 49958770517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025587 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026357 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133088 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133005 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132566 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132498 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.025889 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.025874 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.025889 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.025874 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13165.565690 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29636.451214 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8468.280396 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4957.368184 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13161.968932 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29632.034541 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8456.891395 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4929.692433 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1353,8 +1355,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308164389827 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308164389827 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1308164258694 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1308164258694 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -1369,8 +1371,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 55750 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 55740 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 41971 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 41953 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 79ce98ed4..b9ffca20c 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index b45c8117b..61a472c55 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout -Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:41:18 -gem5 started Aug 20 2011 15:46:02 -gem5 executing on zizzer +gem5 compiled Nov 21 2011 16:32:34 +gem5 started Nov 22 2011 02:00:08 +gem5 executing on u200540-lin command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503587516500 because m5_exit instruction encountered +Exiting @ tick 2503566110500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ae3ccdd2b..b782cd5c8 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503588 # Number of seconds simulated -sim_ticks 2503587516500 # Number of ticks simulated +sim_seconds 2.503566 # Number of seconds simulated +sim_ticks 2503566110500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84198 # Simulator instruction rate (inst/s) -host_tick_rate 2745069755 # Simulator tick rate (ticks/s) -host_mem_usage 385208 # Number of bytes of host memory used -host_seconds 912.03 # Real time elapsed on the host -sim_insts 76790714 # Number of instructions simulated -system.l2c.replacements 119531 # number of replacements -system.l2c.tagsinuse 25929.939584 # Cycle average of tags in use -system.l2c.total_refs 1799445 # Total number of references to valid blocks. -system.l2c.sampled_refs 150368 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.966941 # Average number of references to valid blocks. +host_inst_rate 84156 # Simulator instruction rate (inst/s) +host_tick_rate 2743719152 # Simulator tick rate (ticks/s) +host_mem_usage 380536 # Number of bytes of host memory used +host_seconds 912.47 # Real time elapsed on the host +sim_insts 76790007 # Number of instructions simulated +system.l2c.replacements 119509 # number of replacements +system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use +system.l2c.total_refs 1795434 # Total number of references to valid blocks. +system.l2c.sampled_refs 150343 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.942252 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11550.967581 # Average occupied blocks per context -system.l2c.occ_blocks::1 14378.972003 # Average occupied blocks per context -system.l2c.occ_percent::0 0.176254 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219406 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1351962 # number of ReadReq hits -system.l2c.ReadReq_hits::1 155464 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1507426 # number of ReadReq hits -system.l2c.Writeback_hits::0 630774 # number of Writeback hits -system.l2c.Writeback_hits::total 630774 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105933 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105933 # number of ReadExReq hits -system.l2c.demand_hits::0 1457895 # number of demand (read+write) hits -system.l2c.demand_hits::1 155464 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613359 # number of demand (read+write) hits -system.l2c.overall_hits::0 1457895 # number of overall hits -system.l2c.overall_hits::1 155464 # number of overall hits -system.l2c.overall_hits::total 1613359 # number of overall hits -system.l2c.ReadReq_misses::0 36117 # number of ReadReq misses -system.l2c.ReadReq_misses::1 148 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36265 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3244 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3244 # number of UpgradeReq misses +system.l2c.occ_blocks::0 11551.232252 # Average occupied blocks per context +system.l2c.occ_blocks::1 14378.665001 # Average occupied blocks per context +system.l2c.occ_percent::0 0.176258 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.219401 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1350292 # number of ReadReq hits +system.l2c.ReadReq_hits::1 153003 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1503295 # number of ReadReq hits +system.l2c.Writeback_hits::0 629881 # number of Writeback hits +system.l2c.Writeback_hits::total 629881 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 16 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 105934 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105934 # number of ReadExReq hits +system.l2c.demand_hits::0 1456226 # number of demand (read+write) hits +system.l2c.demand_hits::1 153003 # number of demand (read+write) hits +system.l2c.demand_hits::total 1609229 # number of demand (read+write) hits +system.l2c.overall_hits::0 1456226 # number of overall hits +system.l2c.overall_hits::1 153003 # number of overall hits +system.l2c.overall_hits::total 1609229 # number of overall hits +system.l2c.ReadReq_misses::0 36080 # number of ReadReq misses +system.l2c.ReadReq_misses::1 144 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36224 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3255 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3255 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140419 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140419 # number of ReadExReq misses -system.l2c.demand_misses::0 176536 # number of demand (read+write) misses -system.l2c.demand_misses::1 148 # number of demand (read+write) misses -system.l2c.demand_misses::total 176684 # number of demand (read+write) misses -system.l2c.overall_misses::0 176536 # number of overall misses -system.l2c.overall_misses::1 148 # number of overall misses -system.l2c.overall_misses::total 176684 # number of overall misses -system.l2c.ReadReq_miss_latency 1896887000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 953000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7384203500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9281090500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9281090500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1388079 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 155612 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1543691 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 630774 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 630774 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3286 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246352 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246352 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1634431 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 155612 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1790043 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1634431 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 155612 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1790043 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026019 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000951 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026970 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.987219 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.105263 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569993 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.108011 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000951 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108962 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.108011 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000951 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108962 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52520.613561 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12816804.054054 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12869324.667616 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 293.773120 # average UpgradeReq miss latency +system.l2c.ReadExReq_misses::0 140433 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140433 # number of ReadExReq misses +system.l2c.demand_misses::0 176513 # number of demand (read+write) misses +system.l2c.demand_misses::1 144 # number of demand (read+write) misses +system.l2c.demand_misses::total 176657 # number of demand (read+write) misses +system.l2c.overall_misses::0 176513 # number of overall misses +system.l2c.overall_misses::1 144 # number of overall misses +system.l2c.overall_misses::total 176657 # number of overall misses +system.l2c.ReadReq_miss_latency 1894696500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 1006500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7384268500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9278965000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9278965000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1386372 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 153147 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1539519 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 629881 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 629881 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3293 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3293 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1632739 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 153147 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785886 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1632739 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 153147 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785886 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026025 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000940 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026965 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.988460 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.111111 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.570015 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.108109 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000940 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109049 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.108109 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000940 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109049 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52513.761086 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 13157614.583333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 13210128.344420 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 309.216590 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52586.925559 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52582.145934 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52573.358975 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 62710070.945946 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 62762644.304921 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52573.358975 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 62710070.945946 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 62762644.304921 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52568.167784 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 64437256.944444 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64489825.112228 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52568.167784 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 64437256.944444 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64489825.112228 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -107,50 +107,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102665 # number of writebacks -system.l2c.ReadReq_mshr_hits 95 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 95 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 95 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36170 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3244 # number of UpgradeReq MSHR misses +system.l2c.writebacks 102655 # number of writebacks +system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 94 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 36130 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3255 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140419 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176589 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176589 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses 140433 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 176563 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 176563 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1451509500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 130965000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 1449837500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 131527500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5640198500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7091708000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7091708000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131769561500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32342663570 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164112225070 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026058 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.232437 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.258495 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.987219 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_latency 5640075000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7089912500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7089912500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131769527500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32342636570 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164112164070 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.235917 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.261978 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.988460 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.105263 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.111111 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569993 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.570015 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.108043 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.134803 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.242846 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.108043 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.134803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.242846 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40130.204589 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40371.454994 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.108139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.152899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.261038 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.108139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.152899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.261038 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40166.918295 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -165,27 +165,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52225825 # DTB read hits -system.cpu.dtb.read_misses 89986 # DTB read misses -system.cpu.dtb.write_hits 11975736 # DTB write hits -system.cpu.dtb.write_misses 26350 # DTB write misses +system.cpu.dtb.read_hits 52217329 # DTB read hits +system.cpu.dtb.read_misses 90306 # DTB read misses +system.cpu.dtb.write_hits 11974176 # DTB write hits +system.cpu.dtb.write_misses 25588 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4338 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 8018 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 617 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5563 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 685 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2450 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52315811 # DTB read accesses -system.cpu.dtb.write_accesses 12002086 # DTB write accesses +system.cpu.dtb.perms_faults 2233 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52307635 # DTB read accesses +system.cpu.dtb.write_accesses 11999764 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64201561 # DTB hits -system.cpu.dtb.misses 116336 # DTB misses -system.cpu.dtb.accesses 64317897 # DTB accesses -system.cpu.itb.inst_hits 14135631 # ITB inst hits -system.cpu.itb.inst_misses 11185 # ITB inst misses +system.cpu.dtb.hits 64191505 # DTB hits +system.cpu.dtb.misses 115894 # DTB misses +system.cpu.dtb.accesses 64307399 # DTB accesses +system.cpu.itb.inst_hits 14124795 # ITB inst hits +system.cpu.itb.inst_misses 9853 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -194,516 +194,517 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2607 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2606 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8440 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 7868 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14146816 # ITB inst accesses -system.cpu.itb.hits 14135631 # DTB hits -system.cpu.itb.misses 11185 # DTB misses -system.cpu.itb.accesses 14146816 # DTB accesses -system.cpu.numCycles 415920995 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 14134648 # ITB inst accesses +system.cpu.itb.hits 14124795 # DTB hits +system.cpu.itb.misses 9853 # DTB misses +system.cpu.itb.accesses 14134648 # DTB accesses +system.cpu.numCycles 415912091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16219215 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12559944 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1110172 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13927920 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10224432 # Number of BTB hits +system.cpu.BPredUnit.lookups 16206323 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12554772 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1108177 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13916811 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10226428 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1424516 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 228409 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32955891 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104818490 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16219215 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11648948 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24471055 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7079806 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 137198 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92799321 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 151217 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217200 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 351 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14126420 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1047323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6165 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155547085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.838560 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.184344 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1423283 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 227054 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32931583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104747250 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16206323 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11649711 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24460631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7066944 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 130925 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92852979 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 144764 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217141 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14116150 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1044696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4826 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155542524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.838034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.183637 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131101786 84.28% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1736791 1.12% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2601051 1.67% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3653656 2.35% 89.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2169863 1.39% 90.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1434892 0.92% 91.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2627328 1.69% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 855909 0.55% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9365809 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131107701 84.29% 84.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1736645 1.12% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2606210 1.68% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3650547 2.35% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2167045 1.39% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1435515 0.92% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2626627 1.69% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 854151 0.55% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9358083 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155547085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038996 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.252015 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35186802 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92649693 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21977926 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1094000 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4638664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2316854 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 177884 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122073457 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 575981 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4638664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37340555 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36816085 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49864787 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20912628 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5974366 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 113922984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4414 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 914987 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3980816 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42327 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118460665 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 523781573 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 523685374 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 96199 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77493785 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40966879 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1201529 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1095575 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12285551 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 22000628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14180796 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1905529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2295702 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102943309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1872075 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126931651 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 252428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27053062 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73124308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 373806 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155547085 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.816034 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505599 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155542524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038966 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.251849 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35137982 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92713675 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21969277 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1093477 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4628113 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2313056 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 177631 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122001156 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 574106 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4628113 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37294552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36817406 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49929047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20901153 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5972253 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 113826701 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4400 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118358542 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 40865823 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21982315 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102860212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1874615 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126873317 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 374922 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108904431 70.01% 70.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15118772 9.72% 79.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7542016 4.85% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6525767 4.20% 88.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12768009 8.21% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2736654 1.76% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1396269 0.90% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 422710 0.27% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132457 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12766128 8.21% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2735747 1.76% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155547085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155542524 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45562 0.51% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8415938 94.58% 95.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 436851 4.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45891 0.52% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8417784 94.58% 95.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60109955 47.36% 47.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96551 0.08% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2253 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53954328 42.51% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12662017 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60069483 47.35% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2251 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126931651 # Type of FU issued -system.cpu.iq.rate 0.305182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8898356 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070104 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418652883 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131886553 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87334534 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23945 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10473 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135710724 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12753 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 616189 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126873317 # Type of FU issued +system.cpu.iq.rate 0.305048 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 418533130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87292109 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 135654306 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6319666 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11234 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32604 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2401616 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6301517 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32657 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2389653 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34061863 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1153574 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34061869 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1153605 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4638664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28343669 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 418971 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 105030898 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 476967 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 22000628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14180796 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1225085 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85041 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7449 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32604 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 851635 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 257956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109591 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123477395 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52923959 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3454256 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4628113 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28345943 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 419499 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 104949442 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1228030 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123429780 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 215514 # number of nop insts executed -system.cpu.iew.exec_refs 65415175 # number of memory reference insts executed -system.cpu.iew.exec_branches 11714146 # Number of branches executed -system.cpu.iew.exec_stores 12491216 # Number of stores executed -system.cpu.iew.exec_rate 0.296877 # Inst execution rate -system.cpu.iew.wb_sent 121817988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87345007 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47064551 # num instructions producing a value -system.cpu.iew.wb_consumers 86684992 # num instructions consuming a value +system.cpu.iew.exec_nop 214615 # number of nop insts executed +system.cpu.iew.exec_refs 65401525 # number of memory reference insts executed +system.cpu.iew.exec_branches 11705842 # Number of branches executed +system.cpu.iew.exec_stores 12487221 # Number of stores executed +system.cpu.iew.exec_rate 0.296769 # Inst execution rate +system.cpu.iew.wb_sent 121771134 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87302555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47043389 # num instructions producing a value +system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210004 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.542938 # average fanout of values written-back +system.cpu.iew.wb_rate 0.209906 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.542984 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76941095 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27854412 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1498269 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 978817 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 150990773 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.509575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459429 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 76940388 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27793277 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499693 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 977065 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150996763 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.509550 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459324 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122133629 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14849154 9.83% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4108732 2.72% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2181203 1.44% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1788420 1.18% 96.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1359682 0.90% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1260703 0.83% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 659440 0.44% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2649810 1.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122144480 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14839804 9.83% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4110999 2.72% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2181780 1.44% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1788910 1.18% 96.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1360879 0.90% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1262027 0.84% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 662023 0.44% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2645861 1.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 150990773 # Number of insts commited each cycle -system.cpu.commit.count 76941095 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 150996763 # Number of insts commited each cycle +system.cpu.commit.count 76940388 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27460142 # Number of memory references committed -system.cpu.commit.loads 15680962 # Number of loads committed +system.cpu.commit.refs 27459875 # Number of memory references committed +system.cpu.commit.loads 15680798 # Number of loads committed system.cpu.commit.membars 413062 # Number of memory barriers committed -system.cpu.commit.branches 9891108 # Number of branches committed +system.cpu.commit.branches 9891038 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68494112 # Number of committed integer instructions. +system.cpu.commit.int_insts 68493475 # Number of committed integer instructions. system.cpu.commit.function_calls 995603 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2649810 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2645861 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 251379971 # The number of ROB reads -system.cpu.rob.rob_writes 214361160 # The number of ROB writes -system.cpu.timesIdled 1877573 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260373910 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 76790714 # Number of Instructions Simulated -system.cpu.committedInsts_total 76790714 # Number of Instructions Simulated -system.cpu.cpi 5.416293 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.416293 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184628 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184628 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559837261 # number of integer regfile reads -system.cpu.int_regfile_writes 89743570 # number of integer regfile writes -system.cpu.fp_regfile_reads 8283 # number of floating regfile reads -system.cpu.fp_regfile_writes 2809 # number of floating regfile writes -system.cpu.misc_regfile_reads 137364406 # number of misc regfile reads -system.cpu.misc_regfile_writes 912286 # number of misc regfile writes -system.cpu.icache.replacements 993006 # number of replacements -system.cpu.icache.tagsinuse 511.614815 # Cycle average of tags in use -system.cpu.icache.total_refs 13045370 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 993518 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.130482 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 251328068 # The number of ROB reads +system.cpu.rob.rob_writes 214226863 # The number of ROB writes +system.cpu.timesIdled 1877486 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260369567 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591132146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 76790007 # Number of Instructions Simulated +system.cpu.committedInsts_total 76790007 # Number of Instructions Simulated +system.cpu.cpi 5.416227 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads +system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 559625789 # number of integer regfile reads +system.cpu.int_regfile_writes 89694790 # number of integer regfile writes +system.cpu.fp_regfile_reads 8322 # number of floating regfile reads +system.cpu.fp_regfile_writes 2832 # number of floating regfile writes +system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads +system.cpu.misc_regfile_writes 912282 # number of misc regfile writes +system.cpu.icache.replacements 991618 # number of replacements +system.cpu.icache.tagsinuse 511.615309 # Cycle average of tags in use +system.cpu.icache.total_refs 13036767 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992130 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.140180 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.614815 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999248 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13045370 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13045370 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13045370 # number of demand (read+write) hits +system.cpu.icache.occ_blocks::0 511.615309 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 13036767 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13036767 # number of ReadReq hits +system.cpu.icache.demand_hits::0 13036767 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13045370 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13045370 # number of overall hits +system.cpu.icache.demand_hits::total 13036767 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 13036767 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 13045370 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1080929 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1080929 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1080929 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 13036767 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1079261 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079261 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1079261 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1080929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1080929 # number of overall misses +system.cpu.icache.demand_misses::total 1079261 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1079261 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1080929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15935046488 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15935046488 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15935046488 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14126299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126299 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14126299 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1079261 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15910722989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15910722989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15910722989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 14116028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14116028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 14116028 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126299 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14126299 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 14116028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 14116028 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126299 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076519 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076519 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 14116028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.076456 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.076456 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076519 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.076456 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14741.991831 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14741.991831 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14742.238429 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14741.991831 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14742.238429 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2385493 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2475992 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 357 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 368 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6682.053221 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6728.239130 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57770 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 87373 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 87373 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 87373 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 993556 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 993556 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 993556 # number of overall MSHR misses +system.cpu.icache.writebacks 57161 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 87101 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 87101 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 87101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 992160 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 992160 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 992160 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11874405493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11874405493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11874405493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11856676492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11856676492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11856676492 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070286 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.070334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.070286 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.070334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.070286 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11951.420446 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644346 # number of replacements +system.cpu.dcache.replacements 643915 # number of replacements system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use -system.cpu.dcache.total_refs 22273031 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644858 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.539435 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 22265831 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644427 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.551363 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14419247 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14419247 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7264920 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264920 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 299971 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 299971 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285485 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285485 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21684167 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 14412375 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14412375 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 7264610 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264610 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 299966 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 299966 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 285484 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285484 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 21676985 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21684167 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21684167 # number of overall hits +system.cpu.dcache.demand_hits::total 21676985 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 21676985 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 21684167 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 724263 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 724263 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2966438 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966438 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13488 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13488 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3690701 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 21676985 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 724119 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 724119 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2966647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966647 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 13487 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13487 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 18 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3690766 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3690701 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3690701 # number of overall misses +system.cpu.dcache.demand_misses::total 3690766 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3690766 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3690701 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10889184500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110353624242 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 218944000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 357000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121242808742 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121242808742 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15143510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15143510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10231358 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10231358 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313459 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313459 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285504 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285504 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25374868 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 3690766 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 10885048500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110351571736 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 219032000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 343000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 121236620236 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121236620236 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 15136494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 15136494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10231257 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231257 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 313453 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 313453 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 285502 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285502 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 25367751 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25374868 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25374868 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 25367751 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 25367751 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25374868 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043030 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.145447 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 25367751 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.047839 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.289959 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000063 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.145490 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.145447 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.145490 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15034.848529 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37200.718249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16232.502966 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 18789.473684 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32850.888962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 32848.633654 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32850.888962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 32848.633654 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16719933 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7529000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2957 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5654.356781 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27180.505415 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 16787932 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7490000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2999 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 273 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5597.843281 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 573004 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 337704 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2716896 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1445 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3054600 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3054600 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 386559 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249542 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12043 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 636101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 636101 # number of overall MSHR misses +system.cpu.dcache.writebacks 572720 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 338008 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2717083 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1442 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3055091 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3055091 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 386111 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249564 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 12045 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 18 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 635675 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 635675 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5253783500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8925189433 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161542500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 293500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14178972933 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14178972933 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158793000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258212210 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189417005210 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025526 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 5247540500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8926098932 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161654000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 282500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14173639432 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14173639432 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258178710 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025509 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024390 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038420 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038427 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000063 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025068 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025058 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025068 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025058 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13591.155555 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.281560 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13413.808852 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15447.368421 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -764,8 +765,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1307895610037 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1307895610037 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1307898920918 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses |