SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

5 files changed, 0 insertions, 2605 deletions

diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
deleted file mode 100644
index f406247a4..000000000
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ /dev/null
@@ -1,1537 +0,0 @@
-[root]
-type=Root
-children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-load_addr_mask=18446744073709551615
-mem_mode=timing
-memories=system.physmem
-num_work_ids=16
-physmem=system.physmem
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.port[3]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.bridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-write_ack=false
-master=system.iobus.port[0]
-slave=system.membus.port[1]
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache dtb dtb_walker_cache fuPool icache interrupts itb itb_walker_cache tracer
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-cachePorts=200
-checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=500
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-interrupts=system.cpu.interrupts
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-phase=0
-predType=tournament
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-squashWidth=8
-store_set_clear_period=250000
-system=system
-tracer=system.cpu.tracer
-trapLatency=13
-wbDepth=1
-wbWidth=8
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=4
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.port[2]
-
-[system.cpu.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.dtb.walker
-
-[system.cpu.dtb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.dtb_walker_cache.cpu_side
-
-[system.cpu.dtb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dtb.walker.port
-mem_side=system.toL2Bus.port[4]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-opList=system.cpu.fuPool.FUList0.opList
-
-[system.cpu.fuPool.FUList0.opList]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList4.opList
-
-[system.cpu.fuPool.FUList4.opList]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
-
-[system.cpu.fuPool.FUList5.opList00]
-type=OpDesc
-issueLat=1
-opClass=SimdAdd
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList01]
-type=OpDesc
-issueLat=1
-opClass=SimdAddAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList02]
-type=OpDesc
-issueLat=1
-opClass=SimdAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList03]
-type=OpDesc
-issueLat=1
-opClass=SimdCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList04]
-type=OpDesc
-issueLat=1
-opClass=SimdCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList05]
-type=OpDesc
-issueLat=1
-opClass=SimdMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList06]
-type=OpDesc
-issueLat=1
-opClass=SimdMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList07]
-type=OpDesc
-issueLat=1
-opClass=SimdMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList08]
-type=OpDesc
-issueLat=1
-opClass=SimdShift
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList09]
-type=OpDesc
-issueLat=1
-opClass=SimdShiftAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList10]
-type=OpDesc
-issueLat=1
-opClass=SimdSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList11]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAdd
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList12]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatAlu
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList13]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCmp
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList14]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatCvt
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList15]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatDiv
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList16]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMisc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList17]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMult
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList18]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatMultAcc
-opLat=1
-
-[system.cpu.fuPool.FUList5.opList19]
-type=OpDesc
-issueLat=1
-opClass=SimdFloatSqrt
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList7.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-opList=system.cpu.fuPool.FUList8.opList
-
-[system.cpu.fuPool.FUList8.opList]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=1
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=true
-latency=1000
-max_miss_count=0
-mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=32768
-subblock_size=0
-tgts_per_mshr=20
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.port[1]
-
-[system.cpu.interrupts]
-type=X86LocalApic
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.membus.port[7]
-pio=system.membus.port[6]
-
-[system.cpu.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu.itb.walker
-
-[system.cpu.itb.walker]
-type=X86PagetableWalker
-system=system
-port=system.cpu.itb_walker_cache.cpu_side
-
-[system.cpu.itb_walker_cache]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=2
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=1000
-max_miss_count=0
-mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.itb.walker.port
-mem_side=system.toL2Bus.port[3]
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=2
-size=1048576
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
-[system.iobus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=true
-width=64
-default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-
-[system.iocache]
-type=BaseCache
-addr_range=0:134217727
-assoc=8
-block_size=64
-forward_snoops=false
-hash_delay=1
-is_top_level=false
-latency=50000
-max_miss_count=0
-mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=1024
-subblock_size=0
-tgts_per_mshr=12
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.iobus.port[21]
-mem_side=system.membus.port[4]
-
-[system.l2c]
-type=BaseCache
-addr_range=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
-prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[5]
-
-[system.membus]
-type=Bus
-children=badaddr_responder
-block_size=64
-bus_id=1
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
-
-[system.membus.badaddr_responder]
-type=IsaFake
-fake_mem=false
-pio_addr=0
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[15]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-pio_addr=9223372036854776824
-pio_latency=1000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.port[16]
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[17]
-
-[system.pc.fake_com_3]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[18]
-
-[system.pc.fake_com_4]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=1000
-pio_size=8
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[19]
-
-[system.pc.fake_floppy]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=1000
-pio_size=2
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[20]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=1000
-pio_size=1
-platform=system.pc
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.port[14]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-pio_latency=1
-platform=system.pc
-size=16777216
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pio_latency=1000
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=1000
-platform=system.pc
-system=system
-time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.port[2]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.dma1]
-type=I8237
-pio_addr=9223372036854775808
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[3]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=1000
-platform=system.pc
-system=system
-config=system.iobus.port[5]
-dma=system.iobus.port[6]
-pio=system.iobus.port[4]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=1000
-platform=system.pc
-system=system
-int_port=system.iobus.port[13]
-pio=system.iobus.port[12]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[7]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=1000
-platform=system.pc
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.port[8]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=1000
-platform=system.pc
-slave=Null
-system=system
-pio=system.iobus.port[9]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[10]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=1000
-platform=system.pc
-system=system
-pio=system.iobus.port[11]
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-use_default_range=false
-width=64
-port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
-
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
deleted file mode 100755
index fd09f1faf..000000000
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
+++ /dev/null
@@ -1,9 +0,0 @@
-warn: Sockets disabled, not accepting terminal connections
-warn: Reading current count from inactive timer.
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
-warn: instruction 'fxsave' unimplemented
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
deleted file mode 100755
index 873e1bea2..000000000
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ /dev/null
@@ -1,13 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 08:29:15
-gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
-warning: add_child('terminal'): child 'terminal' already has parent
-Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5161177988500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
deleted file mode 100644
index c62526985..000000000
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ /dev/null
@@ -1,913 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  5.161178                       # Number of seconds simulated
-sim_ticks                                5161177988500                       # Number of ticks simulated
-final_tick                               5161177988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 290092                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1780684720                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 364016                       # Number of bytes of host memory used
-host_seconds                                  2898.42                       # Real time elapsed on the host
-sim_insts                                   840808469                       # Number of instructions simulated
-system.physmem.bytes_read                    16106624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1233856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 12115136                       # Number of bytes written to this memory
-system.physmem.num_reads                       251666                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      189299                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3120726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    239065                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2347359                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5468085                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        169467                       # number of replacements
-system.l2c.tagsinuse                     38339.786444                       # Cycle average of tags in use
-system.l2c.total_refs                         3812924                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        204660                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         18.630529                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 11950.408174                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 26389.378270                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.182349                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.402670                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2335607                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     145488                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2481095                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1594493                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1594493                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     327                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 327                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   150672                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               150672                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2486279                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      145488                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2631767                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2486279                       # number of overall hits
-system.l2c.overall_hits::1                     145488                       # number of overall hits
-system.l2c.overall_hits::total                2631767                       # number of overall hits
-system.l2c.ReadReq_misses::0                    66850                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                      109                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                66959                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  3932                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3932                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 142221                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             142221                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    209071                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                       109                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                209180                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   209071                       # number of overall misses
-system.l2c.overall_misses::1                      109                       # number of overall misses
-system.l2c.overall_misses::total               209180                       # number of overall misses
-system.l2c.ReadReq_miss_latency            3511861000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           38996000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7442399000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            10954260000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           10954260000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2402457                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 145597                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2548054                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1594493                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1594493                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                4259                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            4259                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               292893                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292893                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2695350                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  145597                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2840947                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2695350                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 145597                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2840947                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.027826                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000749                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.028574                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.923221                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.485573                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.077567                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000749                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.078316                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.077567                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000749                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.078316                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52533.448018                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   32218908.256881                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 32271441.704899                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  9917.599186                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52329.817678                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52394.928039                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    100497798.165138                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 100550193.093176                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52394.928039                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   100497798.165138                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 100550193.093176                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          142631                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  66957                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                3932                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               142221                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  209178                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 209178                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       2695362500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     157637000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5708607000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        8403969500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       8403969500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  59978490000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1230737500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  61209227500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.027870                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.459879                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.487749                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.923221                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.485573                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.077607                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.436692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.514299                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.077607                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.436692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.514299                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40255.126424                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40090.793489                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40138.987913                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40176.163363                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40176.163363                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47573                       # number of replacements
-system.iocache.tagsinuse                     0.195398                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47589                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994542788000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.195398                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.012212                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  907                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47627                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47627                       # number of overall misses
-system.iocache.overall_misses::total            47627                       # number of overall misses
-system.iocache.ReadReq_miss_latency         113669932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       6372391160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         6486061092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        6486061092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                907                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47627                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47627                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 125325.173098                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136395.358733                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136184.540114                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136184.540114                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      68679532                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11251                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6104.304684                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46668                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                907                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               47627                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              47627                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     66482982                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3942637876                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    4009120858                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   4009120858                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 73299.869901                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84388.653168                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84177.480379                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84177.480379                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        449878562                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 91189820                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           91189820                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1250253                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              90006318                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 83822675                       # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           28390554                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      451032028                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    91189820                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           83822675                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     171638033                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6092005                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     127923                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               86885537                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                36685                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         38090                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          283                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9866979                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                541048                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    3553                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          291873782                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.039474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.398963                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                120818032     41.39%     41.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1855546      0.64%     42.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72826244     24.95%     66.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1422491      0.49%     67.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1829890      0.63%     68.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4020066      1.38%     69.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1590838      0.55%     70.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1683069      0.58%     70.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85827606     29.41%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            291873782                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.202699                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.002564                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 33589176                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              83124342                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 166020087                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4383500                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4756677                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              883216023                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   571                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4756677                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37852860                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                55892656                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        9911063                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 165583689                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              17876837                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              878703692                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 12652                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12602978                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2126989                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               10                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           880098416                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1724229495                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1724229039                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               456                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             843418783                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 36679626                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             488930                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         489908                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  44000804                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19727758                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10753359                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1338256                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1089668                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  870922009                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1727938                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 867227375                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            177419                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        30993538                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     45221667                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         207753                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     291873782                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.971241                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.381572                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            86148709     29.52%     29.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            24105973      8.26%     37.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            13574297      4.65%     42.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             9676822      3.32%     45.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            79595279     27.27%     73.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             5022101      1.72%     74.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72958833     25.00%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              636421      0.22%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              155347      0.05%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       291873782                       # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  202428      8.97%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1851752     82.02%     90.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                203495      9.01%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            306567      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             831752185     95.91%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25621043      2.95%     98.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9547580      1.10%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              867227375                       # Type of FU issued
-system.cpu.iq.rate                           1.927692                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2257675                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002603                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2028918942                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         903653765                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    856397776                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 194                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                210                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              869178395                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      88                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1343949                       # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4393917                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        17180                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11337                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2321478                       # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7817249                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        160526                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4756677                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                34884624                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6122535                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           872649947                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            301193                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19727758                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10753386                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             894363                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                5389997                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 26295                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11337                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         906001                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       524480                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1430481                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             865094857                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25131798                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2132517                       # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     34436194                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86723634                       # Number of branches executed
-system.cpu.iew.exec_stores                    9304396                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.922952                       # Inst execution rate
-system.cpu.iew.wb_sent                      864455877                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     856397826                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 671292665                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1171999804                       # num instructions consuming a value
-system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.903620                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.572775                       # average fanout of values written-back
-system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      840808469                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        31735206                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1520183                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1254406                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    287133088                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.928288                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.869814                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    107529680     37.45%     37.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13316862      4.64%     42.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3946452      1.37%     43.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76651474     26.70%     70.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4051645      1.41%     71.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1852261      0.65%     72.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1054561      0.37%     72.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71992194     25.07%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6737959      2.35%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    287133088                       # Number of insts commited each cycle
-system.cpu.commit.count                     840808469                       # Number of instructions committed
-system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23765746                       # Number of memory references committed
-system.cpu.commit.loads                      15333838                       # Number of loads committed
-system.cpu.commit.membars                      781579                       # Number of memory barriers committed
-system.cpu.commit.branches                   85539454                       # Number of branches committed
-system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768627958                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6737959                       # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1152856114                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1749856645                       # The number of ROB writes
-system.cpu.timesIdled                         3066243                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       158004780                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9872474852                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   840808469                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             840808469                       # Number of Instructions Simulated
-system.cpu.cpi                               0.535055                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.535055                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.868968                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.868968                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1407444841                       # number of integer regfile reads
-system.cpu.int_regfile_writes               857665866                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               282350765                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 410137                       # number of misc regfile writes
-system.cpu.icache.replacements                1031767                       # number of replacements
-system.cpu.icache.tagsinuse                510.488308                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8766017                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1032279                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   8.491907                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            54591118000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.488308                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.997047                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             8766017                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8766017                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              8766017                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8766017                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             8766017                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
-system.cpu.icache.overall_hits::total         8766017                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1100959                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1100959                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1100959                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1100959                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1100959                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
-system.cpu.icache.overall_misses::total       1100959                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    16475831488                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     16475831488                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    16475831488                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         9866976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9866976                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          9866976                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9866976                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         9866976                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9866976                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.111580                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.111580                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.111580                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14964.981882                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14964.981882                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14964.981882                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2787490                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               276                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 10099.601449                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                     1565                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             66134                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              66134                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             66134                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses         1034825                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses          1034825                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses         1034825                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  12496503490                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  12496503490                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  12496503490                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.104878                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.104878                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.104878                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12075.958244                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12075.958244                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12075.958244                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         8819                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.022437                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          26537                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         8831                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         3.004982                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5118899189000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     6.022437                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.376402                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1        26634                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        26634                       # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1        26637                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        26637                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1        26637                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        26637                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         9699                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         9699                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         9699                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         9699                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         9699                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         9699                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency    124296000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency    124296000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency    124296000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        36333                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        36333                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        36336                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        36336                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        36336                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        36336                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.266947                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.266925                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.266925                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.341788                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.341788                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.341788                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks           1368                       # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.ReadReq_mshr_misses         9699                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses         9699                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses         9699                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency     94849000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency     94849000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency     94849000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.266947                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.266925                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.266925                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9779.255593                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9779.255593                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9779.255593                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       145081                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       13.868389                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         150553                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       145096                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.037610                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5102657828000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1    13.868389                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.866774                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1       150554                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       150554                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1       150554                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       150554                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1       150554                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       150554                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1       146024                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       146024                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1       146024                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       146024                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1       146024                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       146024                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency   2047200500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency   2047200500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency   2047200500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1       296578                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       296578                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1       296578                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       296578                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1       296578                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       296578                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.492363                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.492363                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.492363                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14019.616638                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14019.616638                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14019.616638                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks          42577                       # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses       146024                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses       146024                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses       146024                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1605163000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1605163000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1605163000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.492363                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.492363                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.492363                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10992.460144                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10992.460144                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10992.460144                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1663087                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997625                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 17982371                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1663599                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.809318                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               13135000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.997625                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            11413167                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11413167                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            6547162                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6547162                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             17960329                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         17960329                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            17960329                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
-system.cpu.dcache.overall_hits::total        17960329                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           2492340                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2492340                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          1875398                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1875398                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            4367738                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4367738                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           4367738                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4367738                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    37542071500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   63453033216                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency    100995104716                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   100995104716                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13905507                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13905507                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8422560                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8422560                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         22328067                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     22328067                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        22328067                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     22328067                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.179234                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.222664                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.195616                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.195616                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15062.981576                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33834.435792                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 23122.976863                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 23122.976863                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs   1083233153                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      6672000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             73547                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             391                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 14728.447836                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 17063.938619                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1548983                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1121085                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1578340                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2699425                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2699425                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1371255                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         297058                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1668313                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1668313                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  18154950000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   9754920653                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  27909870653                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  27909870653                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  85210888500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1394917000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  86605805500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098612                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.074718                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.074718                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13239.660019                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32838.437790                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16729.397093                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16729.397093                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
deleted file mode 100644
index 6570dc326..000000000
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ /dev/null
@@ -1,133 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007

-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

-BIOS-provided physical RAM map:

- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)

- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)

-end_pfn_map = 32768

-kernel direct mapping tables up to 8000000 @ 100000-102000

-DMI 2.5 present.

-Zone PFN ranges:

-  DMA           256 ->     4096

-  DMA32        4096 ->  1048576

-  Normal    1048576 ->  1048576

-early_node_map[1] active PFN ranges

-    0:      256 ->    32768

-Intel MultiProcessor Specification v1.4

-MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000

-Processor #0 (Bootup-CPU)

-I/O APIC #1 at 0xFEC00000.

-Setting APIC routing to flat

-Processors: 1

-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)

-Built 1 zonelists.  Total pages: 30458

-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

-Initializing CPU#0

-PID hash table entries: 512 (order: 9, 4096 bytes)

-time.c: Detected 2000.000 MHz processor.

-Console: colour dummy device 80x25

-console handover: boot [earlyser0] -> real [ttyS0]

-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)

-Checking aperture...

-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)

-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset

-Mount-cache hash table entries: 256

-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

-CPU: L2 Cache: 1024K (64 bytes/line)

-CPU: Fake M5 x86_64 CPU stepping 01

-ACPI: Core revision 20070126

-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

-ACPI: Unable to load the System Description Tables

-Using local APIC timer interrupts.

-result 7812497

-Detected 7.812 MHz APIC timer.

-NET: Registered protocol family 16

-PCI: Using configuration type 1

-ACPI: Interpreter disabled.

-Linux Plug and Play Support v0.97 (c) Adam Belay

-pnp: PnP ACPI: disabled

-SCSI subsystem initialized

-usbcore: registered new interface driver usbfs

-usbcore: registered new interface driver hub

-usbcore: registered new device driver usb

-PCI: Probing PCI hardware

-PCI-GART: No AMD northbridge found.

-NET: Registered protocol family 2

-Time: tsc clocksource has been installed.

-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)

-TCP established hash table entries: 4096 (order: 4, 65536 bytes)

-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)

-TCP: Hash tables configured (established 4096 bind 4096)

-TCP reno registered

-Total HugeTLB memory allocated, 0

-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).

-io scheduler noop registered

-io scheduler deadline registered

-io scheduler cfq registered (default)

-Real Time Clock Driver v1.12ac

-Linux agpgart interface v0.102 (c) Dave Jones

-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled

-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250

-floppy0: no floppy controllers found

-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize

-loop: module loaded

-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2

-Copyright (c) 1999-2006 Intel Corporation.

-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI

-e100: Copyright(c) 1999-2006 Intel Corporation

-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.

-tun: Universal TUN/TAP device driver, 1.6

-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>

-netconsole: not configured, aborting

-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2

-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx

-PIIX4: IDE controller at PCI slot 0000:00:04.0

-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)

-PIIX4: chipset revision 0

-PIIX4: not 100% native mode: will probe irqs later

-    ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA

-    ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA

-hda: M5 IDE Disk, ATA DISK drive

-hdb: M5 IDE Disk, ATA DISK drive

-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14

-hda: max request size: 128KiB

-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)

- hda: hda1

-hdb: max request size: 128KiB

-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)

- hdb: unknown partition table

-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)

-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)

-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007

-Fusion MPT base driver 3.04.04

-Copyright (c) 1999-2007 LSI Logic Corporation

-Fusion MPT SPI Host driver 3.04.04

-Fusion MPT SAS Host driver 3.04.04

-ieee1394: raw1394: /dev/raw1394 device initialized

-USB Universal Host Controller Interface driver v3.0

-usbcore: registered new interface driver usblp

-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver

-Initializing USB Mass Storage driver...

-usbcore: registered new interface driver usb-storage

-USB Mass Storage support registered.

-PNP: No PS/2 controller found. Probing ports directly.

-serio: i8042 KBD port at 0x60,0x64 irq 1

-serio: i8042 AUX port at 0x60,0x64 irq 12

-mice: PS/2 mouse device common for all mice

-input: AT Translated Set 2 keyboard as /class/input/input0

-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com

-input: PS/2 Generic Mouse as /class/input/input1

-usbcore: registered new interface driver usbhid

-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver

-oprofile: using timer interrupt.

-TCP cubic registered

-NET: Registered protocol family 1

-NET: Registered protocol family 10

-IPv6 over IPv4 tunneling driver

-NET: Registered protocol family 17

-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended

-VFS: Mounted root (ext2 filesystem).

-Freeing unused kernel memory: 232k freed

-
INIT: version 2.86 booting


-mounting filesystems...

-loading script...