diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 01:23:16 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 01:23:16 -0800 |
| commit | 2107258d24962f979b5f5ec1fd22589b0b49d072 (patch) | |
| tree | 8cb31851318373ee12bffbda1c302bd21ace25d3 /tests/long/10.linux-boot/ref | |
| parent | dd53743797b2c642ef0cf720a9db5a930de2670d (diff) | |
| download | gem5-2107258d24962f979b5f5ec1fd22589b0b49d072.tar.xz | |
X86: Add stats for the new x86 fs regressions.
Diffstat (limited to 'tests/long/10.linux-boot/ref')
10 files changed, 3881 insertions, 0 deletions
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini new file mode 100644 index 000000000..46cc1ee8d --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -0,0 +1,1174 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxX86System +children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus +acpi_description_table_pointer=system.acpi_description_table_pointer +boot_cpu_frequency=500 +boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +e820_table=system.e820_table +init_param=0 +intel_mp_pointer=system.intel_mp_pointer +intel_mp_table=system.intel_mp_table +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +load_addr_mask=18446744073709551615 +mem_mode=atomic +physmem=system.physmem +readfile=tests/halt.sh +smbios_table=system.smbios_table +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 + +[system.acpi_description_table_pointer] +type=X86ACPIRSDP +children=xsdt +oem_id= +revision=2 +rsdt=Null +xsdt=system.acpi_description_table_pointer.xsdt + +[system.acpi_description_table_pointer.xsdt] +type=X86ACPIXSDT +creator_id= +creator_revision=0 +entries= +oem_id= +oem_revision=0 +oem_table_id= + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:1152921504606846975 +filter_ranges_b=0:134217727 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[1] + +[system.cpu] +type=AtomicSimpleCPU +children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.dtb_walker_cache.cpu_side + +[system.cpu.dtb_walker_cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dtb.walker.port +mem_side=system.toL2Bus.port[4] + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +platform=system.pc +system=system +int_port=system.membus.port[5] +pio=system.membus.port[4] + +[system.cpu.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.itb_walker_cache.cpu_side + +[system.cpu.itb_walker_cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.itb.walker.port +mem_side=system.toL2Bus.port[3] + +[system.cpu.tracer] +type=ExeTracer + +[system.e820_table] +type=X86E820Table +children=entries0 entries1 +entries=system.e820_table.entries0 system.e820_table.entries1 + +[system.e820_table.entries0] +type=X86E820Entry +addr=0 +range_type=2 +size=1048576 + +[system.e820_table.entries1] +type=X86E820Entry +addr=1048576 +range_type=1 +size=133169152 + +[system.intel_mp_pointer] +type=X86IntelMPFloatingPointer +default_config=0 +imcr_present=true +spec_rev=4 + +[system.intel_mp_table] +type=X86IntelMPConfigTable +children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries +base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +ext_entries=system.intel_mp_table.ext_entries +local_apic=4276092928 +oem_id= +oem_table_addr=0 +oem_table_size=0 +product_id= +spec_rev=4 + +[system.intel_mp_table.base_entries00] +type=X86IntelMPProcessor +bootstrap=true +enable=true +family=0 +feature_flags=0 +local_apic_id=0 +local_apic_version=20 +model=0 +stepping=0 + +[system.intel_mp_table.base_entries01] +type=X86IntelMPIOAPIC +address=4273995776 +enable=true +id=1 +version=17 + +[system.intel_mp_table.base_entries02] +type=X86IntelMPBus +bus_id=0 +bus_type=ISA + +[system.intel_mp_table.base_entries03] +type=X86IntelMPBus +bus_id=1 +bus_type=PCI + +[system.intel_mp_table.base_entries04] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=16 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=1 +source_bus_irq=16 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries05] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=0 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries06] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=2 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=0 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries07] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=1 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries08] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=1 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=1 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries09] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=3 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries10] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=3 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=3 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries11] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=4 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries12] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=4 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=4 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries13] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=5 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries14] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=5 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=5 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries15] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=6 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries16] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=6 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=6 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries17] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=7 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries18] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=7 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=7 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries19] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=8 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries20] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=8 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=8 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries21] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=9 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries22] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=9 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=9 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries23] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=10 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries24] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=10 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=10 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries25] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=11 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries26] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=11 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=11 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries27] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=12 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries28] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=12 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=12 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries29] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=13 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries30] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=13 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=13 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries31] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=14 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries32] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=14 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=14 +trigger=ConformTrigger + +[system.intel_mp_table.ext_entries] +type=X86IntelMPBusHierarchy +bus_id=0 +parent_bus=1 +subtractive_decode=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=true +width=64 +default=system.pc.pciconfig.pio +port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:134217727 +assoc=8 +block_size=64 +forward_snoops=false +hash_delay=1 +latency=50000 +max_miss_count=0 +mshrs=20 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[18] +mem_side=system.membus.port[2] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=92 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[3] + +[system.membus] +type=Bus +children=badaddr_responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +default=system.membus.badaddr_responder.pio +port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port + +[system.membus.badaddr_responder] +type=IsaFake +pio_addr=0 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.pc] +type=Pc +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +intrctrl=system.intrctrl +system=system + +[system.pc.behind_pci] +type=IsaFake +pio_addr=9223372036854779128 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[12] + +[system.pc.com_1] +type=Uart8250 +pio_addr=9223372036854776824 +pio_latency=1000 +platform=system.pc +system=system +terminal=system.pc.terminal +pio=system.iobus.port[13] + +[system.pc.fake_com_2] +type=IsaFake +pio_addr=9223372036854776568 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[14] + +[system.pc.fake_com_3] +type=IsaFake +pio_addr=9223372036854776808 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[15] + +[system.pc.fake_com_4] +type=IsaFake +pio_addr=9223372036854776552 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[16] + +[system.pc.fake_floppy] +type=IsaFake +pio_addr=9223372036854776818 +pio_latency=1000 +pio_size=2 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[17] + +[system.pc.i_dont_exist] +type=IsaFake +pio_addr=9223372036854775936 +pio_latency=1000 +pio_size=1 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.pc.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.pc +size=16777216 +system=system +pio=system.iobus.default + +[system.pc.south_bridge] +type=SouthBridge +children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker +cmos=system.pc.south_bridge.cmos +dma1=system.pc.south_bridge.dma1 +int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6 +io_apic=system.pc.south_bridge.io_apic +keyboard=system.pc.south_bridge.keyboard +pic1=system.pc.south_bridge.pic1 +pic2=system.pc.south_bridge.pic2 +pio_latency=1000 +pit=system.pc.south_bridge.pit +platform=system.pc +speaker=system.pc.south_bridge.speaker + +[system.pc.south_bridge.cmos] +type=Cmos +int_pin=system.pc.south_bridge.int_lines2.source +pio_addr=9223372036854775920 +pio_latency=1000 +platform=system.pc +system=system +time=Sun Jan 1 00:00:00 2012 +pio=system.iobus.port[1] + +[system.pc.south_bridge.dma1] +type=I8237 +pio_addr=9223372036854775808 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[2] + +[system.pc.south_bridge.ide] +type=IdeController +children=disks0 disks1 +BAR0=496 +BAR0LegacyIO=true +BAR0Size=8 +BAR1=1012 +BAR1LegacyIO=true +BAR1Size=3 +BAR2=368 +BAR2LegacyIO=true +BAR2Size=8 +BAR3=884 +BAR3LegacyIO=true +BAR3Size=3 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=14 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=128 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +ctrl_offset=0 +disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +io_shift=0 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=4 +pci_func=0 +pio_latency=1000 +platform=system.pc +system=system +config=system.iobus.port[19] +dma=system.iobus.port[20] +pio=system.iobus.port[3] + +[system.pc.south_bridge.ide.disks0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.pc.south_bridge.ide.disks0.image + +[system.pc.south_bridge.ide.disks0.image] +type=CowDiskImage +children=child +child=system.pc.south_bridge.ide.disks0.image.child +image_file= +read_only=false +table_size=65536 + +[system.pc.south_bridge.ide.disks0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-x86.img +read_only=true + +[system.pc.south_bridge.ide.disks1] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.pc.south_bridge.ide.disks1.image + +[system.pc.south_bridge.ide.disks1.image] +type=CowDiskImage +children=child +child=system.pc.south_bridge.ide.disks1.image.child +image_file= +read_only=false +table_size=65536 + +[system.pc.south_bridge.ide.disks1.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[system.pc.south_bridge.int_lines0] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines0.sink +source=system.pc.south_bridge.int_lines0.source + +[system.pc.south_bridge.int_lines0.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=0 + +[system.pc.south_bridge.int_lines0.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines1] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines1.sink +source=system.pc.south_bridge.int_lines1.source + +[system.pc.south_bridge.int_lines1.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic1 +number=2 + +[system.pc.south_bridge.int_lines1.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines2] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines2.sink +source=system.pc.south_bridge.int_lines2.source + +[system.pc.south_bridge.int_lines2.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic2 +number=0 + +[system.pc.south_bridge.int_lines2.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines3] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines3.sink +source=system.pc.south_bridge.int_lines3.source + +[system.pc.south_bridge.int_lines3.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic1 +number=0 + +[system.pc.south_bridge.int_lines3.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines4] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines4.sink +source=system.pc.south_bridge.int_lines3.source + +[system.pc.south_bridge.int_lines4.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=2 + +[system.pc.south_bridge.int_lines5] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines5.sink +source=system.pc.south_bridge.int_lines5.source + +[system.pc.south_bridge.int_lines5.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=1 + +[system.pc.south_bridge.int_lines5.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines6] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines6.sink +source=system.pc.south_bridge.int_lines6.source + +[system.pc.south_bridge.int_lines6.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=12 + +[system.pc.south_bridge.int_lines6.source] +type=X86IntSourcePin + +[system.pc.south_bridge.io_apic] +type=I82094AA +apic_id=1 +external_int_pic=system.pc.south_bridge.pic1 +int_latency=1000 +pio_addr=4273995776 +pio_latency=1000 +platform=system.pc +system=system +int_port=system.iobus.port[10] +pio=system.iobus.port[9] + +[system.pc.south_bridge.keyboard] +type=I8042 +command_port=9223372036854775908 +data_port=9223372036854775904 +keyboard_int_pin=system.pc.south_bridge.int_lines5.source +mouse_int_pin=system.pc.south_bridge.int_lines6.source +pio_addr=0 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[4] + +[system.pc.south_bridge.pic1] +type=I8259 +mode=I8259Master +output=system.pc.south_bridge.int_lines0.source +pio_addr=9223372036854775840 +pio_latency=1000 +platform=system.pc +slave=system.pc.south_bridge.pic2 +system=system +pio=system.iobus.port[5] + +[system.pc.south_bridge.pic2] +type=I8259 +mode=I8259Slave +output=system.pc.south_bridge.int_lines1.source +pio_addr=9223372036854775968 +pio_latency=1000 +platform=system.pc +slave=Null +system=system +pio=system.iobus.port[6] + +[system.pc.south_bridge.pit] +type=I8254 +int_pin=system.pc.south_bridge.int_lines3.source +pio_addr=9223372036854775872 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[7] + +[system.pc.south_bridge.speaker] +type=PcSpeaker +i8254=system.pc.south_bridge.pit +pio_addr=9223372036854775905 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[8] + +[system.pc.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + +[system.smbios_table] +type=X86SMBiosSMBiosTable +children=structures +major_version=2 +minor_version=5 +structures=system.smbios_table.structures + +[system.smbios_table.structures] +type=X86SMBiosBiosInformation +characteristic_ext_bytes= +characteristics= +emb_cont_firmware_major=0 +emb_cont_firmware_minor=0 +major=0 +minor=0 +release_date=06/08/2008 +rom_size=0 +starting_addr_segment=0 +vendor= +version= + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side + diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr new file mode 100755 index 000000000..99f9676e9 --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -0,0 +1,17 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Reading current count from inactive timer. +For more information see: http://www.m5sim.org/warn/1ea2be46 +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Don't know what interrupt to clear for console. +For more information see: http://www.m5sim.org/warn/7fe1004f +warn: instruction 'fxsave' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: Tried to clear PCI interrupt 14 +For more information see: http://www.m5sim.org/warn/77378d57 +warn: Unknown mouse command 0xe1. +For more information see: http://www.m5sim.org/warn/2447512a +warn: instruction 'wbinvd' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout new file mode 100755 index 000000000..1d5316147 --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 7 2011 01:04:06 +M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch +M5 started Feb 7 2011 01:04:09 +M5 executing on burrito +command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 5112051463500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt new file mode 100644 index 000000000..1cabd6a2d --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -0,0 +1,547 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2329852 # Simulator instruction rate (inst/s) +host_mem_usage 370744 # Number of bytes of host memory used +host_seconds 174.53 # Real time elapsed on the host +host_tick_rate 29290692573 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 406624453 # Number of instructions simulated +sim_seconds 5.112051 # Number of seconds simulated +sim_ticks 5112051463500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses::0 13367989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13367989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 12053700 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12053700 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.098316 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1314289 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1314289 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses::0 8403116 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8403116 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 8087096 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8087096 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 316020 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316020 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 12.424940 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::0 21771105 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21771105 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 20140796 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20140796 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.074884 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 1630309 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1630309 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999963 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.980804 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 21771105 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21771105 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 20140796 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 20140796 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.074884 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 1630309 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1630309 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1620657 # number of replacements +system.cpu.dcache.sampled_refs 1621150 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.980804 # Cycle average of tags in use +system.cpu.dcache.total_refs 20142691 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1525412 # number of writebacks +system.cpu.dtb_walker_cache.ReadExReq_accesses::1 21821 # number of ReadExReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadExReq_accesses::total 21821 # number of ReadExReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadExReq_hits::1 8119 # number of ReadExReq hits +system.cpu.dtb_walker_cache.ReadExReq_hits::total 8119 # number of ReadExReq hits +system.cpu.dtb_walker_cache.ReadExReq_miss_rate::1 0.627927 # miss rate for ReadExReq accesses +system.cpu.dtb_walker_cache.ReadExReq_misses::1 13702 # number of ReadExReq misses +system.cpu.dtb_walker_cache.ReadExReq_misses::total 13702 # number of ReadExReq misses +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_refs 1.289175 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 21821 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21821 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 8119 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 8119 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.627927 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 13702 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 13702 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.occ_%::1 0.312845 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_blocks::1 5.005513 # Average occupied blocks per context +system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::1 21821 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21821 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::1 8119 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 8119 # number of overall hits +system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.627927 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::1 13702 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 13702 # number of overall misses +system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dtb_walker_cache.replacements 7920 # number of replacements +system.cpu.dtb_walker_cache.sampled_refs 7926 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.tagsinuse 5.005513 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 10218 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101233174000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.writebacks 7801 # number of writebacks +system.cpu.icache.ReadReq_accesses::0 254189384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 254189384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 253396963 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 253396963 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.003117 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 792421 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792421 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 319.778503 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::0 254189384 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 254189384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.demand_hits::0 253396963 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 253396963 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.003117 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 792421 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792421 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.997320 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 510.627884 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 254189384 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 254189384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 253396963 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 253396963 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.003117 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 792421 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 792421 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 791902 # number of replacements +system.cpu.icache.sampled_refs 792414 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 510.627884 # Cycle average of tags in use +system.cpu.icache.total_refs 253396963 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 148756026000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 809 # number of writebacks +system.cpu.idle_fraction 0.955646 # Percentage of idle cycles +system.cpu.itb_walker_cache.ReadExReq_accesses::1 12217 # number of ReadExReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadExReq_accesses::total 12217 # number of ReadExReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadExReq_hits::1 3753 # number of ReadExReq hits +system.cpu.itb_walker_cache.ReadExReq_hits::total 3753 # number of ReadExReq hits +system.cpu.itb_walker_cache.ReadExReq_miss_rate::1 0.692805 # miss rate for ReadExReq accesses +system.cpu.itb_walker_cache.ReadExReq_misses::1 8464 # number of ReadExReq misses +system.cpu.itb_walker_cache.ReadExReq_misses::total 8464 # number of ReadExReq misses +system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits +system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits +system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.avg_refs 1.580645 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 12219 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 3755 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 3755 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.692692 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 8464 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8464 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.itb_walker_cache.occ_%::1 0.063695 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_blocks::1 1.019121 # Average occupied blocks per context +system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::1 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::1 3755 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 3755 # number of overall hits +system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.692692 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::1 8464 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8464 # number of overall misses +system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.itb_walker_cache.replacements 3371 # number of replacements +system.cpu.itb_walker_cache.sampled_refs 3379 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.itb_walker_cache.tagsinuse 1.019121 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 5341 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5105336019500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.writebacks 3369 # number of writebacks +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles +system.cpu.numCycles 10224102950 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 453482138.002058 # Number of busy cycles +system.cpu.num_conditional_control_insts 42460206 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 9770620811.997942 # Number of idle cycles +system.cpu.num_insts 406624453 # Number of instructions executed +system.cpu.num_int_alu_accesses 391833833 # Number of integer alu accesses +system.cpu.num_int_insts 391833833 # number of integer instructions +system.cpu.num_int_register_reads 1007515486 # number of times the integer registers were read +system.cpu.num_int_register_writes 419160860 # number of times the integer registers were written +system.cpu.num_load_insts 29720540 # Number of load instructions +system.cpu.num_mem_refs 38133606 # number of memory refs +system.cpu.num_store_insts 8413066 # Number of store instructions +system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.occ_%::1 0.002653 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.042448 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 47574 # number of replacements +system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.042448 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 4994772176509 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 46667 # number of writebacks +system.l2c.ReadExReq_accesses::0 314094 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 10676 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 324770 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 169175 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 9794 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 178969 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.461387 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.082615 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.544003 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 144919 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 882 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 145801 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2100004 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2100004 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 2043710 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2043710 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.026807 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 56294 # number of ReadReq misses +system.l2c.ReadReq_misses::total 56294 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 33 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 3893 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3926 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_rate::0 0.939394 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.999743 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 1.939137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3892 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3923 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 1537391 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1537391 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 1537391 # number of Writeback hits +system.l2c.Writeback_hits::total 1537391 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_refs 16.898474 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::0 2414098 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 10676 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2424774 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.demand_hits::0 2212885 # number of demand (read+write) hits +system.l2c.demand_hits::1 9794 # number of demand (read+write) hits +system.l2c.demand_hits::total 2222679 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.083349 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.082615 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165964 # miss rate for demand accesses +system.l2c.demand_misses::0 201213 # number of demand (read+write) misses +system.l2c.demand_misses::1 882 # number of demand (read+write) misses +system.l2c.demand_misses::total 202095 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.occ_%::0 0.147969 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.414145 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 9697.290249 # Average occupied blocks per context +system.l2c.occ_blocks::1 27141.433510 # Average occupied blocks per context +system.l2c.overall_accesses::0 2414098 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 10676 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2424774 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.overall_hits::0 2212885 # number of overall hits +system.l2c.overall_hits::1 9794 # number of overall hits +system.l2c.overall_hits::total 2222679 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.083349 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.082615 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165964 # miss rate for overall accesses +system.l2c.overall_misses::0 201213 # number of overall misses +system.l2c.overall_misses::1 882 # number of overall misses +system.l2c.overall_misses::total 202095 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 164866 # number of replacements +system.l2c.sampled_refs 196728 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 36838.723760 # Cycle average of tags in use +system.l2c.total_refs 3324403 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 144396 # number of writebacks +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal new file mode 100644 index 000000000..ab8215fe1 --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal @@ -0,0 +1,133 @@ +Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+BIOS-provided physical RAM map:
+ BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+end_pfn_map = 32768
+kernel direct mapping tables up to 8000000 @ 100000-102000
+DMI 2.5 present.
+Zone PFN ranges:
+ DMA 256 -> 4096
+ DMA32 4096 -> 1048576
+ Normal 1048576 -> 1048576
+early_node_map[1] active PFN ranges
+ 0: 256 -> 32768
+Intel MultiProcessor Specification v1.4
+MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
+Processor #0 (Bootup-CPU)
+I/O APIC #1 at 0xFEC00000.
+Setting APIC routing to flat
+Processors: 1
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
+Built 1 zonelists. Total pages: 30458
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+Initializing CPU#0
+PID hash table entries: 512 (order: 9, 4096 bytes)
+time.c: Detected 1999.998 MHz processor.
+Console: colour dummy device 80x25
+console handover: boot [earlyser0] -> real [ttyS0]
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Checking aperture...
+Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
+Mount-cache hash table entries: 256
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
+CPU: L2 Cache: 1024K (64 bytes/line)
+CPU: Fake M5 x86_64 CPU stepping 01
+ACPI: Core revision 20070126
+ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
+ACPI: Unable to load the System Description Tables
+Using local APIC timer interrupts.
+result 7812490
+Detected 7.812 MHz APIC timer.
+NET: Registered protocol family 16
+PCI: Using configuration type 1
+ACPI: Interpreter disabled.
+Linux Plug and Play Support v0.97 (c) Adam Belay
+pnp: PnP ACPI: disabled
+SCSI subsystem initialized
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+PCI: Probing PCI hardware
+PCI-GART: No AMD northbridge found.
+NET: Registered protocol family 2
+Time: tsc clocksource has been installed.
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
+TCP established hash table entries: 4096 (order: 4, 65536 bytes)
+TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
+TCP: Hash tables configured (established 4096 bind 4096)
+TCP reno registered
+Total HugeTLB memory allocated, 0
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+io scheduler noop registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+Real Time Clock Driver v1.12ac
+Linux agpgart interface v0.102 (c) Dave Jones
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+floppy0: no floppy controllers found
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
+Copyright (c) 1999-2006 Intel Corporation.
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
+e100: Copyright(c) 1999-2006 Intel Corporation
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
+tun: Universal TUN/TAP device driver, 1.6
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+netconsole: not configured, aborting
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PIIX4: IDE controller at PCI slot 0000:00:04.0
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
+PIIX4: chipset revision 0
+PIIX4: not 100% native mode: will probe irqs later
+ ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
+ ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
+hda: M5 IDE Disk, ATA DISK drive
+hdb: M5 IDE Disk, ATA DISK drive
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
+hda: max request size: 128KiB
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
+ hda: hda1
+hdb: max request size: 128KiB
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+ hdb: unknown partition table
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
+Fusion MPT base driver 3.04.04
+Copyright (c) 1999-2007 LSI Logic Corporation
+Fusion MPT SPI Host driver 3.04.04
+Fusion MPT SAS Host driver 3.04.04
+ieee1394: raw1394: /dev/raw1394 device initialized
+USB Universal Host Controller Interface driver v3.0
+usbcore: registered new interface driver usblp
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
+Initializing USB Mass Storage driver...
+usbcore: registered new interface driver usb-storage
+USB Mass Storage support registered.
+PNP: No PS/2 controller found. Probing ports directly.
+serio: i8042 KBD port at 0x60,0x64 irq 1
+serio: i8042 AUX port at 0x60,0x64 irq 12
+mice: PS/2 mouse device common for all mice
+input: AT Translated Set 2 keyboard as /class/input/input0
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
+input: PS/2 Generic Mouse as /class/input/input1
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
+oprofile: using timer interrupt.
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 10
+IPv6 over IPv4 tunneling driver
+NET: Registered protocol family 17
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 232k freed
+
INIT: version 2.86 booting
+mounting filesystems...
+loading script...
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini new file mode 100644 index 000000000..0541c10f2 --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -0,0 +1,1171 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxX86System +children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus +acpi_description_table_pointer=system.acpi_description_table_pointer +boot_cpu_frequency=500 +boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 +e820_table=system.e820_table +init_param=0 +intel_mp_pointer=system.intel_mp_pointer +intel_mp_table=system.intel_mp_table +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +load_addr_mask=18446744073709551615 +mem_mode=timing +physmem=system.physmem +readfile=tests/halt.sh +smbios_table=system.smbios_table +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 + +[system.acpi_description_table_pointer] +type=X86ACPIRSDP +children=xsdt +oem_id= +revision=2 +rsdt=Null +xsdt=system.acpi_description_table_pointer.xsdt + +[system.acpi_description_table_pointer.xsdt] +type=X86ACPIXSDT +creator_id= +creator_revision=0 +entries= +oem_id= +oem_revision=0 +oem_table_id= + +[system.bridge] +type=Bridge +delay=50000 +filter_ranges_a=0:1152921504606846975 +filter_ranges_b=0:134217727 +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[1] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.dtb_walker_cache.cpu_side + +[system.cpu.dtb_walker_cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dtb.walker.port +mem_side=system.toL2Bus.port[4] + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=4 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +platform=system.pc +system=system +int_port=system.membus.port[5] +pio=system.membus.port[4] + +[system.cpu.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.itb_walker_cache.cpu_side + +[system.cpu.itb_walker_cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.itb.walker.port +mem_side=system.toL2Bus.port[3] + +[system.cpu.tracer] +type=ExeTracer + +[system.e820_table] +type=X86E820Table +children=entries0 entries1 +entries=system.e820_table.entries0 system.e820_table.entries1 + +[system.e820_table.entries0] +type=X86E820Entry +addr=0 +range_type=2 +size=1048576 + +[system.e820_table.entries1] +type=X86E820Entry +addr=1048576 +range_type=1 +size=133169152 + +[system.intel_mp_pointer] +type=X86IntelMPFloatingPointer +default_config=0 +imcr_present=true +spec_rev=4 + +[system.intel_mp_table] +type=X86IntelMPConfigTable +children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries +base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 +ext_entries=system.intel_mp_table.ext_entries +local_apic=4276092928 +oem_id= +oem_table_addr=0 +oem_table_size=0 +product_id= +spec_rev=4 + +[system.intel_mp_table.base_entries00] +type=X86IntelMPProcessor +bootstrap=true +enable=true +family=0 +feature_flags=0 +local_apic_id=0 +local_apic_version=20 +model=0 +stepping=0 + +[system.intel_mp_table.base_entries01] +type=X86IntelMPIOAPIC +address=4273995776 +enable=true +id=1 +version=17 + +[system.intel_mp_table.base_entries02] +type=X86IntelMPBus +bus_id=0 +bus_type=ISA + +[system.intel_mp_table.base_entries03] +type=X86IntelMPBus +bus_id=1 +bus_type=PCI + +[system.intel_mp_table.base_entries04] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=16 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=1 +source_bus_irq=16 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries05] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=0 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries06] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=2 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=0 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries07] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=1 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries08] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=1 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=1 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries09] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=3 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries10] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=3 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=3 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries11] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=4 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries12] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=4 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=4 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries13] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=5 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries14] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=5 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=5 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries15] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=6 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries16] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=6 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=6 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries17] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=7 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries18] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=7 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=7 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries19] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=8 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries20] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=8 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=8 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries21] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=9 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries22] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=9 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=9 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries23] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=10 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries24] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=10 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=10 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries25] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=11 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries26] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=11 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=11 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries27] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=12 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries28] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=12 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=12 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries29] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=13 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries30] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=13 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=13 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries31] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=0 +interrupt_type=ExtInt +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=14 +trigger=ConformTrigger + +[system.intel_mp_table.base_entries32] +type=X86IntelMPIOIntAssignment +dest_io_apic_id=1 +dest_io_apic_intin=14 +interrupt_type=INT +polarity=ConformPolarity +source_bus_id=0 +source_bus_irq=14 +trigger=ConformTrigger + +[system.intel_mp_table.ext_entries] +type=X86IntelMPBusHierarchy +bus_id=0 +parent_bus=1 +subtractive_decode=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=true +width=64 +default=system.pc.pciconfig.pio +port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma + +[system.iocache] +type=BaseCache +addr_range=0:134217727 +assoc=8 +block_size=64 +forward_snoops=false +hash_delay=1 +latency=50000 +max_miss_count=0 +mshrs=20 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=500000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=1024 +subblock_size=0 +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.port[18] +mem_side=system.membus.port[2] + +[system.l2c] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=10000 +max_miss_count=0 +mshrs=92 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[3] + +[system.membus] +type=Bus +children=badaddr_responder +block_size=64 +bus_id=1 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +default=system.membus.badaddr_responder.pio +port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port + +[system.membus.badaddr_responder] +type=IsaFake +pio_addr=0 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.pc] +type=Pc +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal +intrctrl=system.intrctrl +system=system + +[system.pc.behind_pci] +type=IsaFake +pio_addr=9223372036854779128 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[12] + +[system.pc.com_1] +type=Uart8250 +pio_addr=9223372036854776824 +pio_latency=1000 +platform=system.pc +system=system +terminal=system.pc.terminal +pio=system.iobus.port[13] + +[system.pc.fake_com_2] +type=IsaFake +pio_addr=9223372036854776568 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[14] + +[system.pc.fake_com_3] +type=IsaFake +pio_addr=9223372036854776808 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[15] + +[system.pc.fake_com_4] +type=IsaFake +pio_addr=9223372036854776552 +pio_latency=1000 +pio_size=8 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[16] + +[system.pc.fake_floppy] +type=IsaFake +pio_addr=9223372036854776818 +pio_latency=1000 +pio_size=2 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[17] + +[system.pc.i_dont_exist] +type=IsaFake +pio_addr=9223372036854775936 +pio_latency=1000 +pio_size=1 +platform=system.pc +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[11] + +[system.pc.pciconfig] +type=PciConfigAll +bus=0 +pio_latency=1 +platform=system.pc +size=16777216 +system=system +pio=system.iobus.default + +[system.pc.south_bridge] +type=SouthBridge +children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker +cmos=system.pc.south_bridge.cmos +dma1=system.pc.south_bridge.dma1 +int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6 +io_apic=system.pc.south_bridge.io_apic +keyboard=system.pc.south_bridge.keyboard +pic1=system.pc.south_bridge.pic1 +pic2=system.pc.south_bridge.pic2 +pio_latency=1000 +pit=system.pc.south_bridge.pit +platform=system.pc +speaker=system.pc.south_bridge.speaker + +[system.pc.south_bridge.cmos] +type=Cmos +int_pin=system.pc.south_bridge.int_lines2.source +pio_addr=9223372036854775920 +pio_latency=1000 +platform=system.pc +system=system +time=Sun Jan 1 00:00:00 2012 +pio=system.iobus.port[1] + +[system.pc.south_bridge.dma1] +type=I8237 +pio_addr=9223372036854775808 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[2] + +[system.pc.south_bridge.ide] +type=IdeController +children=disks0 disks1 +BAR0=496 +BAR0LegacyIO=true +BAR0Size=8 +BAR1=1012 +BAR1LegacyIO=true +BAR1Size=3 +BAR2=368 +BAR2LegacyIO=true +BAR2Size=8 +BAR3=884 +BAR3LegacyIO=true +BAR3Size=3 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=14 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=128 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +ctrl_offset=0 +disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 +io_shift=0 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=4 +pci_func=0 +pio_latency=1000 +platform=system.pc +system=system +config=system.iobus.port[19] +dma=system.iobus.port[20] +pio=system.iobus.port[3] + +[system.pc.south_bridge.ide.disks0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.pc.south_bridge.ide.disks0.image + +[system.pc.south_bridge.ide.disks0.image] +type=CowDiskImage +children=child +child=system.pc.south_bridge.ide.disks0.image.child +image_file= +read_only=false +table_size=65536 + +[system.pc.south_bridge.ide.disks0.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-x86.img +read_only=true + +[system.pc.south_bridge.ide.disks1] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.pc.south_bridge.ide.disks1.image + +[system.pc.south_bridge.ide.disks1.image] +type=CowDiskImage +children=child +child=system.pc.south_bridge.ide.disks1.image.child +image_file= +read_only=false +table_size=65536 + +[system.pc.south_bridge.ide.disks1.image.child] +type=RawDiskImage +image_file=/dist/m5/system/disks/linux-bigswap2.img +read_only=true + +[system.pc.south_bridge.int_lines0] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines0.sink +source=system.pc.south_bridge.int_lines0.source + +[system.pc.south_bridge.int_lines0.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=0 + +[system.pc.south_bridge.int_lines0.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines1] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines1.sink +source=system.pc.south_bridge.int_lines1.source + +[system.pc.south_bridge.int_lines1.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic1 +number=2 + +[system.pc.south_bridge.int_lines1.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines2] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines2.sink +source=system.pc.south_bridge.int_lines2.source + +[system.pc.south_bridge.int_lines2.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic2 +number=0 + +[system.pc.south_bridge.int_lines2.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines3] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines3.sink +source=system.pc.south_bridge.int_lines3.source + +[system.pc.south_bridge.int_lines3.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.pic1 +number=0 + +[system.pc.south_bridge.int_lines3.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines4] +type=X86IntLine +children=sink +sink=system.pc.south_bridge.int_lines4.sink +source=system.pc.south_bridge.int_lines3.source + +[system.pc.south_bridge.int_lines4.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=2 + +[system.pc.south_bridge.int_lines5] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines5.sink +source=system.pc.south_bridge.int_lines5.source + +[system.pc.south_bridge.int_lines5.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=1 + +[system.pc.south_bridge.int_lines5.source] +type=X86IntSourcePin + +[system.pc.south_bridge.int_lines6] +type=X86IntLine +children=sink source +sink=system.pc.south_bridge.int_lines6.sink +source=system.pc.south_bridge.int_lines6.source + +[system.pc.south_bridge.int_lines6.sink] +type=X86IntSinkPin +device=system.pc.south_bridge.io_apic +number=12 + +[system.pc.south_bridge.int_lines6.source] +type=X86IntSourcePin + +[system.pc.south_bridge.io_apic] +type=I82094AA +apic_id=1 +external_int_pic=system.pc.south_bridge.pic1 +int_latency=1000 +pio_addr=4273995776 +pio_latency=1000 +platform=system.pc +system=system +int_port=system.iobus.port[10] +pio=system.iobus.port[9] + +[system.pc.south_bridge.keyboard] +type=I8042 +command_port=9223372036854775908 +data_port=9223372036854775904 +keyboard_int_pin=system.pc.south_bridge.int_lines5.source +mouse_int_pin=system.pc.south_bridge.int_lines6.source +pio_addr=0 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[4] + +[system.pc.south_bridge.pic1] +type=I8259 +mode=I8259Master +output=system.pc.south_bridge.int_lines0.source +pio_addr=9223372036854775840 +pio_latency=1000 +platform=system.pc +slave=system.pc.south_bridge.pic2 +system=system +pio=system.iobus.port[5] + +[system.pc.south_bridge.pic2] +type=I8259 +mode=I8259Slave +output=system.pc.south_bridge.int_lines1.source +pio_addr=9223372036854775968 +pio_latency=1000 +platform=system.pc +slave=Null +system=system +pio=system.iobus.port[6] + +[system.pc.south_bridge.pit] +type=I8254 +int_pin=system.pc.south_bridge.int_lines3.source +pio_addr=9223372036854775872 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[7] + +[system.pc.south_bridge.speaker] +type=PcSpeaker +i8254=system.pc.south_bridge.pit +pio_addr=9223372036854775905 +pio_latency=1000 +platform=system.pc +system=system +pio=system.iobus.port[8] + +[system.pc.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + +[system.smbios_table] +type=X86SMBiosSMBiosTable +children=structures +major_version=2 +minor_version=5 +structures=system.smbios_table.structures + +[system.smbios_table.structures] +type=X86SMBiosBiosInformation +characteristic_ext_bytes= +characteristics= +emb_cont_firmware_major=0 +emb_cont_firmware_minor=0 +major=0 +minor=0 +release_date=06/08/2008 +rom_size=0 +starting_addr_segment=0 +vendor= +version= + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side + diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr new file mode 100755 index 000000000..99f9676e9 --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -0,0 +1,17 @@ +warn: Sockets disabled, not accepting terminal connections +For more information see: http://www.m5sim.org/warn/8742226b +warn: Reading current count from inactive timer. +For more information see: http://www.m5sim.org/warn/1ea2be46 +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Don't know what interrupt to clear for console. +For more information see: http://www.m5sim.org/warn/7fe1004f +warn: instruction 'fxsave' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +warn: Tried to clear PCI interrupt 14 +For more information see: http://www.m5sim.org/warn/77378d57 +warn: Unknown mouse command 0xe1. +For more information see: http://www.m5sim.org/warn/2447512a +warn: instruction 'wbinvd' unimplemented +For more information see: http://www.m5sim.org/warn/437d5238 +hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout new file mode 100755 index 000000000..6d191e20f --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -0,0 +1,17 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Feb 7 2011 01:04:06 +M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch +M5 started Feb 7 2011 01:04:09 +M5 executing on burrito +command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 5187506658000 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt new file mode 100644 index 000000000..b4552b7b7 --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -0,0 +1,655 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1700985 # Simulator instruction rate (inst/s) +host_mem_usage 367580 # Number of bytes of host memory used +host_seconds 155.42 # Real time elapsed on the host +host_tick_rate 33377224644 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 264367743 # Number of instructions simulated +sim_seconds 5.187507 # Number of seconds simulated +sim_ticks 5187506658000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses::0 13293064 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13293064 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15104.781562 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12104.746605 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits::0 11977155 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11977155 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 19876518000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.098992 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1315909 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1315909 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 15928745000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098992 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1315909 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_accesses::0 8350799 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350799 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29942.780036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 26942.753048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits::0 8035839 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035839 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 9430778000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.037716 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 314960 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314960 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 8485889500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037716 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 314960 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379632500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 12.342068 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::0 21643863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21643863 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 17970.355682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 14970.322264 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 20012994 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20012994 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 29307296000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.075350 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 1630869 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1630869 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24414634500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.075350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1630869 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_%::0 0.999904 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.950602 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 21643863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21643863 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 17970.355682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 14970.322264 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 20012994 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 20012994 # number of overall hits +system.cpu.dcache.overall_miss_latency 29307296000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.075350 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 1630869 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1630869 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24414634500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.075350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1630869 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 77304957000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 1621186 # number of replacements +system.cpu.dcache.sampled_refs 1621682 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.950602 # Cycle average of tags in use +system.cpu.dcache.total_refs 20014909 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 44516000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1527886 # number of writebacks +system.cpu.dtb_walker_cache.ReadExReq_accesses::1 22048 # number of ReadExReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadExReq_accesses::total 22048 # number of ReadExReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadExReq_avg_miss_latency::0 inf # average ReadExReq miss latency +system.cpu.dtb_walker_cache.ReadExReq_avg_miss_latency::1 20286.289721 # average ReadExReq miss latency +system.cpu.dtb_walker_cache.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.cpu.dtb_walker_cache.ReadExReq_avg_mshr_miss_latency 17286.289721 # average ReadExReq mshr miss latency +system.cpu.dtb_walker_cache.ReadExReq_hits::1 8642 # number of ReadExReq hits +system.cpu.dtb_walker_cache.ReadExReq_hits::total 8642 # number of ReadExReq hits +system.cpu.dtb_walker_cache.ReadExReq_miss_latency 271958000 # number of ReadExReq miss cycles +system.cpu.dtb_walker_cache.ReadExReq_miss_rate::1 0.608037 # miss rate for ReadExReq accesses +system.cpu.dtb_walker_cache.ReadExReq_misses::1 13406 # number of ReadExReq misses +system.cpu.dtb_walker_cache.ReadExReq_misses::total 13406 # number of ReadExReq misses +system.cpu.dtb_walker_cache.ReadExReq_mshr_miss_latency 231740000 # number of ReadExReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadExReq_mshr_miss_rate::0 inf # mshr miss rate for ReadExReq accesses +system.cpu.dtb_walker_cache.ReadExReq_mshr_miss_rate::1 0.608037 # mshr miss rate for ReadExReq accesses +system.cpu.dtb_walker_cache.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.cpu.dtb_walker_cache.ReadExReq_mshr_misses 13406 # number of ReadExReq MSHR misses +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_refs 1.469166 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 22048 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22048 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 20286.289721 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 17286.289721 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 8642 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 8642 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_miss_latency 271958000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.608037 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 13406 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 13406 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 231740000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.608037 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_misses 13406 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.occ_%::1 0.313997 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_blocks::1 5.023950 # Average occupied blocks per context +system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::1 22048 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22048 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 20286.289721 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 17286.289721 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::1 8642 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 8642 # number of overall hits +system.cpu.dtb_walker_cache.overall_miss_latency 271958000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.608037 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::1 13406 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 13406 # number of overall misses +system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 231740000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.608037 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_misses 13406 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dtb_walker_cache.replacements 7434 # number of replacements +system.cpu.dtb_walker_cache.sampled_refs 7443 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.tagsinuse 5.023950 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 10935 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5162123916000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.writebacks 7169 # number of writebacks +system.cpu.icache.ReadReq_accesses::0 159240089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 159240089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14814.295997 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11812.979122 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 158449581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 158449581 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11710819500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.004964 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 790508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 790508 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 9338254500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004964 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 790508 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 200.441974 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::0 159240089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 159240089 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14814.295997 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11812.979122 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 158449581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 158449581 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11710819500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.004964 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 790508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 790508 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 9338254500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.004964 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 790508 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_%::0 0.996794 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 510.358748 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 159240089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 159240089 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14814.295997 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11812.979122 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 158449581 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 158449581 # number of overall hits +system.cpu.icache.overall_miss_latency 11710819500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.004964 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 790508 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 790508 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 9338254500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.004964 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 790508 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 789989 # number of replacements +system.cpu.icache.sampled_refs 790501 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 510.358748 # Cycle average of tags in use +system.cpu.icache.total_refs 158449581 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 160047217000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 806 # number of writebacks +system.cpu.idle_fraction 0.941812 # Percentage of idle cycles +system.cpu.itb_walker_cache.ReadExReq_accesses::1 12331 # number of ReadExReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadExReq_accesses::total 12331 # number of ReadExReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadExReq_avg_miss_latency::0 inf # average ReadExReq miss latency +system.cpu.itb_walker_cache.ReadExReq_avg_miss_latency::1 19730.086428 # average ReadExReq miss latency +system.cpu.itb_walker_cache.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.cpu.itb_walker_cache.ReadExReq_avg_mshr_miss_latency 16730.086428 # average ReadExReq mshr miss latency +system.cpu.itb_walker_cache.ReadExReq_hits::1 3769 # number of ReadExReq hits +system.cpu.itb_walker_cache.ReadExReq_hits::total 3769 # number of ReadExReq hits +system.cpu.itb_walker_cache.ReadExReq_miss_latency 168929000 # number of ReadExReq miss cycles +system.cpu.itb_walker_cache.ReadExReq_miss_rate::1 0.694348 # miss rate for ReadExReq accesses +system.cpu.itb_walker_cache.ReadExReq_misses::1 8562 # number of ReadExReq misses +system.cpu.itb_walker_cache.ReadExReq_misses::total 8562 # number of ReadExReq misses +system.cpu.itb_walker_cache.ReadExReq_mshr_miss_latency 143243000 # number of ReadExReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadExReq_mshr_miss_rate::0 inf # mshr miss rate for ReadExReq accesses +system.cpu.itb_walker_cache.ReadExReq_mshr_miss_rate::1 0.694348 # mshr miss rate for ReadExReq accesses +system.cpu.itb_walker_cache.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.cpu.itb_walker_cache.ReadExReq_mshr_misses 8562 # number of ReadExReq MSHR misses +system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits +system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits +system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.avg_refs 1.515714 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 19730.086428 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 16730.086428 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 3771 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 3771 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_miss_latency 168929000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.694235 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 8562 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8562 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.itb_walker_cache.demand_mshr_miss_latency 143243000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.694235 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_misses 8562 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.itb_walker_cache.occ_%::1 0.065229 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_blocks::1 1.043665 # Average occupied blocks per context +system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::1 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 19730.086428 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 16730.086428 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::1 3771 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 3771 # number of overall hits +system.cpu.itb_walker_cache.overall_miss_latency 168929000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.694235 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::1 8562 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8562 # number of overall misses +system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.itb_walker_cache.overall_mshr_miss_latency 143243000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.694235 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_misses 8562 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.itb_walker_cache.replacements 3493 # number of replacements +system.cpu.itb_walker_cache.sampled_refs 3500 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.itb_walker_cache.tagsinuse 1.043665 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 5305 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5175757784000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.writebacks 3491 # number of writebacks +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.not_idle_fraction 0.058188 # Percentage of non-idle cycles +system.cpu.numCycles 10375013316 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 603697441.873884 # Number of busy cycles +system.cpu.num_conditional_control_insts 24882902 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_idle_cycles 9771315874.126116 # Number of idle cycles +system.cpu.num_insts 264367743 # Number of instructions executed +system.cpu.num_int_alu_accesses 249584659 # Number of integer alu accesses +system.cpu.num_int_insts 249584659 # number of integer instructions +system.cpu.num_int_register_reads 660399505 # number of times the integer registers were read +system.cpu.num_int_register_writes 266062505 # number of times the integer registers were written +system.cpu.num_load_insts 14817593 # Number of load instructions +system.cpu.num_mem_refs 23178416 # number of memory refs +system.cpu.num_store_insts 8360823 # Number of store instructions +system.iocache.ReadReq_accesses::1 838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 126350.754177 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 74325.749403 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 105881932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 838 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 62284978 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_misses 838 # number of ReadReq MSHR misses +system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136919.759418 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84914.276498 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 6396891160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses +system.iocache.WriteReq_mshr_miss_latency 3967194998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses +system.iocache.avg_blocked_cycles::no_mshrs 6173.065841 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.blocked::no_mshrs 11300 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 69755644 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47558 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136733.527314 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency +system.iocache.demand_avg_mshr_miss_latency 84727.700408 # average overall mshr miss latency +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.demand_miss_latency 6502773092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 47558 # number of demand (read+write) misses +system.iocache.demand_misses::total 47558 # number of demand (read+write) misses +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.demand_mshr_miss_latency 4029479976 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_misses 47558 # number of demand (read+write) MSHR misses +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.occ_%::1 0.006011 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.096172 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47558 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136733.527314 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.overall_avg_mshr_miss_latency 84727.700408 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.overall_miss_latency 6502773092 # number of overall miss cycles +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 47558 # number of overall misses +system.iocache.overall_misses::total 47558 # number of overall misses +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.overall_mshr_miss_latency 4029479976 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_misses 47558 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.replacements 47503 # number of replacements +system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.tagsinuse 0.096172 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.warmup_cycle 5048756216000 # Cycle when the warmup percentage was hit. +system.iocache.writebacks 46667 # number of writebacks +system.l2c.ReadExReq_accesses::0 312990 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 10347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 323337 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52450.939745 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 6116197.957198 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 6168648.896943 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40004.929653 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 193117 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 9319 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 202436 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6287451500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.382993 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.099352 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.482346 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 119873 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 1028 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120901 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4836636000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.386278 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 11.684643 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 12.070920 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 120901 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2099667 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2099667 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52255.661117 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40255.279138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits::0 2048617 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2048617 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 2667651500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.024313 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 51050 # number of ReadReq misses +system.l2c.ReadReq_misses::total 51050 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 2055032000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.024313 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 51050 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 69 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 3915 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3984 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 29000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 507.071227 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29507.071227 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40103.613849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 27 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 1972000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.985507 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.993359 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 1.978866 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 68 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3889 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3957 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 158690000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 57.347826 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 1.010728 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 58.358554 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 3957 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency 1218002000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 1539352 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1539352 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 1539352 # number of Writeback hits +system.l2c.Writeback_hits::total 1539352 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.avg_refs 19.863119 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::0 2412657 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 10347 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2423004 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52392.615388 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 8711189.688716 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 8763582.304104 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40079.255137 # average overall mshr miss latency +system.l2c.demand_hits::0 2241734 # number of demand (read+write) hits +system.l2c.demand_hits::1 9319 # number of demand (read+write) hits +system.l2c.demand_hits::total 2251053 # number of demand (read+write) hits +system.l2c.demand_miss_latency 8955103000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.070844 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.099352 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170197 # miss rate for demand accesses +system.l2c.demand_misses::0 170923 # number of demand (read+write) misses +system.l2c.demand_misses::1 1028 # number of demand (read+write) misses +system.l2c.demand_misses::total 171951 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 6891668000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.071270 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 16.618440 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 16.689711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 171951 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.occ_%::0 0.120535 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.358282 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 7899.412034 # Average occupied blocks per context +system.l2c.occ_blocks::1 23480.375714 # Average occupied blocks per context +system.l2c.overall_accesses::0 2412657 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 10347 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2423004 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52392.615388 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 8711189.688716 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 8763582.304104 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40079.255137 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.overall_hits::0 2241734 # number of overall hits +system.l2c.overall_hits::1 9319 # number of overall hits +system.l2c.overall_hits::total 2251053 # number of overall hits +system.l2c.overall_miss_latency 8955103000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.070844 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.099352 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170197 # miss rate for overall accesses +system.l2c.overall_misses::0 170923 # number of overall misses +system.l2c.overall_misses::1 1028 # number of overall misses +system.l2c.overall_misses::total 171951 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 6891668000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.071270 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 16.618440 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 16.689711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 171951 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 57269787000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.replacements 135636 # number of replacements +system.l2c.sampled_refs 168555 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 31379.787748 # Cycle average of tags in use +system.l2c.total_refs 3348028 # Total number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 115407 # number of writebacks +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal new file mode 100644 index 000000000..a1c03790e --- /dev/null +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal @@ -0,0 +1,133 @@ +Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+BIOS-provided physical RAM map:
+ BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+end_pfn_map = 32768
+kernel direct mapping tables up to 8000000 @ 100000-102000
+DMI 2.5 present.
+Zone PFN ranges:
+ DMA 256 -> 4096
+ DMA32 4096 -> 1048576
+ Normal 1048576 -> 1048576
+early_node_map[1] active PFN ranges
+ 0: 256 -> 32768
+Intel MultiProcessor Specification v1.4
+MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000
+Processor #0 (Bootup-CPU)
+I/O APIC #1 at 0xFEC00000.
+Setting APIC routing to flat
+Processors: 1
+Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
+Built 1 zonelists. Total pages: 30458
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+Initializing CPU#0
+PID hash table entries: 512 (order: 9, 4096 bytes)
+time.c: Detected 1999.998 MHz processor.
+Console: colour dummy device 80x25
+console handover: boot [earlyser0] -> real [ttyS0]
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Checking aperture...
+Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
+Mount-cache hash table entries: 256
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
+CPU: L2 Cache: 1024K (64 bytes/line)
+CPU: Fake M5 x86_64 CPU stepping 01
+ACPI: Core revision 20070126
+ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
+ACPI: Unable to load the System Description Tables
+Using local APIC timer interrupts.
+result 7812489
+Detected 7.812 MHz APIC timer.
+NET: Registered protocol family 16
+PCI: Using configuration type 1
+ACPI: Interpreter disabled.
+Linux Plug and Play Support v0.97 (c) Adam Belay
+pnp: PnP ACPI: disabled
+SCSI subsystem initialized
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+PCI: Probing PCI hardware
+PCI-GART: No AMD northbridge found.
+Time: tsc clocksource has been installed.
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)
+TCP established hash table entries: 4096 (order: 4, 65536 bytes)
+TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
+TCP: Hash tables configured (established 4096 bind 4096)
+TCP reno registered
+Total HugeTLB memory allocated, 0
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+io scheduler noop registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+Real Time Clock Driver v1.12ac
+Linux agpgart interface v0.102 (c) Dave Jones
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250
+floppy0: no floppy controllers found
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2
+Copyright (c) 1999-2006 Intel Corporation.
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI
+e100: Copyright(c) 1999-2006 Intel Corporation
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.
+tun: Universal TUN/TAP device driver, 1.6
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+netconsole: not configured, aborting
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PIIX4: IDE controller at PCI slot 0000:00:04.0
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)
+PIIX4: chipset revision 0
+PIIX4: not 100% native mode: will probe irqs later
+ ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA
+ ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA
+hda: M5 IDE Disk, ATA DISK drive
+hdb: M5 IDE Disk, ATA DISK drive
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
+hda: max request size: 128KiB
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)
+ hda: hda1
+hdb: max request size: 128KiB
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
+ hdb: unknown partition table
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007
+Fusion MPT base driver 3.04.04
+Copyright (c) 1999-2007 LSI Logic Corporation
+Fusion MPT SPI Host driver 3.04.04
+Fusion MPT SAS Host driver 3.04.04
+ieee1394: raw1394: /dev/raw1394 device initialized
+USB Universal Host Controller Interface driver v3.0
+usbcore: registered new interface driver usblp
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver
+Initializing USB Mass Storage driver...
+usbcore: registered new interface driver usb-storage
+USB Mass Storage support registered.
+PNP: No PS/2 controller found. Probing ports directly.
+serio: i8042 KBD port at 0x60,0x64 irq 1
+serio: i8042 AUX port at 0x60,0x64 irq 12
+mice: PS/2 mouse device common for all mice
+input: AT Translated Set 2 keyboard as /class/input/input0
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com
+input: PS/2 Generic Mouse as /class/input/input1
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver
+oprofile: using timer interrupt.
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 10
+IPv6 over IPv4 tunneling driver
+NET: Registered protocol family 17
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 232k freed
+
INIT: version 2.86 booting
+mounting filesystems...
+loading script...
|