diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:06 -0500 |
| commit | f125ef22b997d5ba6173d9d3f0d07ae741e279bd (patch) | |
| tree | d3d103939211116d7f8ed7e04db73fbac0b9e9be /tests/long/10.linux-boot/ref | |
| parent | d0e04859023702ec23c97683700c638949a1dad1 (diff) | |
| download | gem5-f125ef22b997d5ba6173d9d3f0d07ae741e279bd.tar.xz | |
O3: Update stats for LSQ changes.
Diffstat (limited to 'tests/long/10.linux-boot/ref')
13 files changed, 2875 insertions, 2843 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 298e17d0f..ce4b09a6a 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/arm/scratch/sysexplr/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/dist/m5/system/binaries/ts_osfpal +pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -931,7 +931,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -951,7 +951,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1080,7 +1080,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index b594e76f7..e8efa0522 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 9 2011 03:11:31 -gem5 started Aug 9 2011 03:11:36 -gem5 executing on burrito +gem5 compiled Aug 15 2011 20:24:21 +gem5 started Aug 15 2011 20:25:29 +gem5 executing on nadc-0270 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107915000 -Exiting @ tick 1897528709500 because m5_exit instruction encountered +info: Launching CPU 1 @ 98887000 +Exiting @ tick 1899411597500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 669f31e44..2eeafd392 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897529 # Number of seconds simulated -sim_ticks 1897528709500 # Number of ticks simulated +sim_seconds 1.899412 # Number of seconds simulated +sim_ticks 1899411597500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133002 # Simulator instruction rate (inst/s) -host_tick_rate 4420145385 # Simulator tick rate (ticks/s) -host_mem_usage 318652 # Number of bytes of host memory used -host_seconds 429.29 # Real time elapsed on the host -sim_insts 57096369 # Number of instructions simulated -system.l2c.replacements 396849 # number of replacements -system.l2c.tagsinuse 35842.640466 # Cycle average of tags in use -system.l2c.total_refs 2454377 # Total number of references to valid blocks. -system.l2c.sampled_refs 435040 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.641727 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9253572000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12439.136290 # Average occupied blocks per context -system.l2c.occ_blocks::1 328.499708 # Average occupied blocks per context -system.l2c.occ_blocks::2 23075.004468 # Average occupied blocks per context -system.l2c.occ_percent::0 0.189806 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.005013 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.352097 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1462245 # number of ReadReq hits -system.l2c.ReadReq_hits::1 390216 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1852461 # number of ReadReq hits -system.l2c.Writeback_hits::0 805889 # number of Writeback hits -system.l2c.Writeback_hits::total 805889 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 158 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 388 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 546 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 42 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 131406 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 39589 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 170995 # number of ReadExReq hits -system.l2c.demand_hits::0 1593651 # number of demand (read+write) hits -system.l2c.demand_hits::1 429805 # number of demand (read+write) hits +host_inst_rate 123946 # Simulator instruction rate (inst/s) +host_tick_rate 4137994790 # Simulator tick rate (ticks/s) +host_mem_usage 343492 # Number of bytes of host memory used +host_seconds 459.02 # Real time elapsed on the host +sim_insts 56893410 # Number of instructions simulated +system.l2c.replacements 397094 # number of replacements +system.l2c.tagsinuse 35529.229053 # Cycle average of tags in use +system.l2c.total_refs 2438232 # Total number of references to valid blocks. +system.l2c.sampled_refs 432488 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.637687 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9244135000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 10221.529700 # Average occupied blocks per context +system.l2c.occ_blocks::1 2327.457536 # Average occupied blocks per context +system.l2c.occ_blocks::2 22980.241816 # Average occupied blocks per context +system.l2c.occ_percent::0 0.155968 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.035514 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.350651 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1442413 # number of ReadReq hits +system.l2c.ReadReq_hits::1 407625 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1850038 # number of ReadReq hits +system.l2c.Writeback_hits::0 800001 # number of Writeback hits +system.l2c.Writeback_hits::total 800001 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 188 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 71 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 148509 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 19811 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168320 # number of ReadExReq hits +system.l2c.demand_hits::0 1590922 # number of demand (read+write) hits +system.l2c.demand_hits::1 427436 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2023456 # number of demand (read+write) hits -system.l2c.overall_hits::0 1593651 # number of overall hits -system.l2c.overall_hits::1 429805 # number of overall hits +system.l2c.demand_hits::total 2018358 # number of demand (read+write) hits +system.l2c.overall_hits::0 1590922 # number of overall hits +system.l2c.overall_hits::1 427436 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2023456 # number of overall hits -system.l2c.ReadReq_misses::0 304910 # number of ReadReq misses -system.l2c.ReadReq_misses::1 5378 # number of ReadReq misses -system.l2c.ReadReq_misses::total 310288 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2801 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1482 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4283 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 670 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 687 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1357 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 114075 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 11670 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125745 # number of ReadExReq misses -system.l2c.demand_misses::0 418985 # number of demand (read+write) misses -system.l2c.demand_misses::1 17048 # number of demand (read+write) misses +system.l2c.overall_hits::total 2018358 # number of overall hits +system.l2c.ReadReq_misses::0 301840 # number of ReadReq misses +system.l2c.ReadReq_misses::1 7227 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309067 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3348 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 792 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4140 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 439 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 492 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 931 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 106737 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 17826 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124563 # number of ReadExReq misses +system.l2c.demand_misses::0 408577 # number of demand (read+write) misses +system.l2c.demand_misses::1 25053 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 436033 # number of demand (read+write) misses -system.l2c.overall_misses::0 418985 # number of overall misses -system.l2c.overall_misses::1 17048 # number of overall misses +system.l2c.demand_misses::total 433630 # number of demand (read+write) misses +system.l2c.overall_misses::0 408577 # number of overall misses +system.l2c.overall_misses::1 25053 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 436033 # number of overall misses -system.l2c.ReadReq_miss_latency 16152594500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 19106500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 3089000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6595991500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22748586000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22748586000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1767155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 395594 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2162749 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 805889 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 805889 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2959 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 1870 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4829 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 712 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 716 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1428 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 245481 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 51259 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296740 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2012636 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 446853 # number of demand (read+write) accesses +system.l2c.overall_misses::total 433630 # number of overall misses +system.l2c.ReadReq_miss_latency 16078822000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 5852000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 5401500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6533699500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22612521500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22612521500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1744253 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 414852 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2159105 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 800001 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 800001 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3536 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 863 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4399 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 474 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 527 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1001 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 255246 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 37637 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292883 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1999499 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 452489 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2459489 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2012636 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 446853 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2451988 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1999499 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 452489 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2459489 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.172543 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.013595 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.946604 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.792513 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.941011 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.959497 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.464700 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.227667 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.208177 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.038151 # miss rate for demand accesses +system.l2c.overall_accesses::total 2451988 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.173048 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.017421 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.946833 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.917729 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.926160 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.933586 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.418173 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.473630 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.204340 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.055367 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.208177 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.038151 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.204340 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.055367 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52974.958184 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3003457.512086 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 53269.354625 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 2224826.622388 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 6821.313816 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12892.375169 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1747.909200 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7388.888889 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 4610.447761 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 4496.360990 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 12304.100228 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 10978.658537 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 57821.534078 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 565209.211654 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 61213.070444 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 366526.394031 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 54294.511737 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1334384.443923 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 55344.577644 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 902587.374765 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 54294.511737 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1334384.443923 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 55344.577644 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 902587.374765 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,100 +138,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 121454 # number of writebacks +system.l2c.writebacks 122463 # number of writebacks system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 310271 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 4283 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1357 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 125745 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 436016 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 436016 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 309050 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4140 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 931 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124563 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 433613 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 433613 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12421352000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 171391500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 54292500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5066425000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17487777000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17487777000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838216000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1556318498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2394534498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.175577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.784317 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12366985500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 165615000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 37241500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5018687000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17385672500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17385672500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838004500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1515144998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2353149498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.177182 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.744964 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.447448 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.290374 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.170814 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.797219 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.905899 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.895251 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.964135 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.766603 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.512239 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.453130 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.488012 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 3.309589 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.216639 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.975748 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.216861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.958284 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.216639 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.975748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.216861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.958284 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40033.880060 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.693906 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40009.211496 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40291.264066 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40108.108418 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40108.108418 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.131694 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.623188 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40001.611171 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40290.351067 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40094.906057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40094.906057 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.465119 # Cycle average of tags in use +system.iocache.replacements 41701 # number of replacements +system.iocache.tagsinuse 0.379564 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708345431000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.465119 # Average occupied blocks per context -system.iocache.occ_percent::1 0.029070 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708346603000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.379564 # Average occupied blocks per context +system.iocache.occ_percent::1 0.023723 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses +system.iocache.ReadReq_misses::1 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.demand_misses::1 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency 20503998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5720495806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5740999804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5740999804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses +system.iocache.ReadReq_miss_latency 20618998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5720800806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741419804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741419804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -241,37 +241,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115191 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115189.932961 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137670.769301 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137678.109501 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137574.881476 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137581.649230 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137574.881476 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137581.649230 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64616068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64641068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6178.625741 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6181.607344 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41520 # number of writebacks +system.iocache.writebacks 41522 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses +system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11247998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3559637996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3570885994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3570885994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11310998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3559941996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571252994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571252994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63191 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85667.067674 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85571.195639 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85571.195639 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63189.932961 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85674.383808 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85577.939517 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85577.939517 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8560359 # DTB read hits -system.cpu0.dtb.read_misses 29048 # DTB read misses -system.cpu0.dtb.read_acv 513 # DTB read access violations -system.cpu0.dtb.read_accesses 619639 # DTB read accesses -system.cpu0.dtb.write_hits 5419292 # DTB write hits -system.cpu0.dtb.write_misses 5351 # DTB write misses -system.cpu0.dtb.write_acv 235 # DTB write access violations -system.cpu0.dtb.write_accesses 205704 # DTB write accesses -system.cpu0.dtb.data_hits 13979651 # DTB hits -system.cpu0.dtb.data_misses 34399 # DTB misses -system.cpu0.dtb.data_acv 748 # DTB access violations -system.cpu0.dtb.data_accesses 825343 # DTB accesses -system.cpu0.itb.fetch_hits 968518 # ITB hits -system.cpu0.itb.fetch_misses 28074 # ITB misses -system.cpu0.itb.fetch_acv 865 # ITB acv -system.cpu0.itb.fetch_accesses 996592 # ITB accesses +system.cpu0.dtb.read_hits 8691348 # DTB read hits +system.cpu0.dtb.read_misses 30841 # DTB read misses +system.cpu0.dtb.read_acv 585 # DTB read access violations +system.cpu0.dtb.read_accesses 626526 # DTB read accesses +system.cpu0.dtb.write_hits 5727483 # DTB write hits +system.cpu0.dtb.write_misses 5665 # DTB write misses +system.cpu0.dtb.write_acv 282 # DTB write access violations +system.cpu0.dtb.write_accesses 212486 # DTB write accesses +system.cpu0.dtb.data_hits 14418831 # DTB hits +system.cpu0.dtb.data_misses 36506 # DTB misses +system.cpu0.dtb.data_acv 867 # DTB access violations +system.cpu0.dtb.data_accesses 839012 # DTB accesses +system.cpu0.itb.fetch_hits 1018007 # ITB hits +system.cpu0.itb.fetch_misses 28254 # ITB misses +system.cpu0.itb.fetch_acv 951 # ITB acv +system.cpu0.itb.fetch_accesses 1046261 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,275 +337,275 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 103762975 # number of cpu cycles simulated +system.cpu0.numCycles 103036446 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12289120 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10322639 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 425623 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 11096319 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5846860 # Number of BTB hits +system.cpu0.BPredUnit.lookups 12345310 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 10395868 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 412413 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 11143165 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5756291 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 811980 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 29936 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 23947551 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63604775 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12289120 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6658840 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12410125 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1977970 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32452881 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 32113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 186103 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 333368 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 97 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7852316 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 261746 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 70661432 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.900134 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.212081 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 808447 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 32944 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 25643568 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63130050 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12345310 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6564738 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12229123 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1931790 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 31463202 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31044 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 192852 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 226876 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7797411 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 265802 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 71034720 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.888721 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.206546 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 58251307 82.44% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 861864 1.22% 83.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1790389 2.53% 86.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 838279 1.19% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2691367 3.81% 91.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 597435 0.85% 92.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 679704 0.96% 92.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 792267 1.12% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4158820 5.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 58805597 82.78% 82.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 896633 1.26% 84.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1683822 2.37% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 790380 1.11% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2590451 3.65% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578678 0.81% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 651939 0.92% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 969955 1.37% 94.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4067265 5.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 70661432 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.118435 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612981 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25283379 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31920291 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11354348 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 836358 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1267055 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507127 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32392 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62175948 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 94044 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1267055 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 26303467 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12206310 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16544701 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10563376 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3776521 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58802666 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6783 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 552005 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1306234 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39659853 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71942390 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71601283 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 341107 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33288864 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6370981 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1352745 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 204336 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10335573 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9033738 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5759436 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1575901 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1714897 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51649014 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1711174 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50034185 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 62931 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7150176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3852149 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1166094 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 70661432 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.708083 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.331294 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 71034720 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.119815 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.612696 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26620678 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 31169441 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11195503 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 833782 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1215315 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 497181 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32875 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61799188 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 97991 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1215315 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27633845 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 10392034 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17602675 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10482679 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3708170 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58338786 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6838 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 387997 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1347242 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39031988 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 70900966 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 70475489 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 425477 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33170605 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5861375 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1485068 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 227968 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10243220 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9180149 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6097470 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1603652 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1903642 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51204618 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1864754 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49739725 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 70469 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6805118 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3728302 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1267762 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 71034720 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.700217 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.322322 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 48300171 68.35% 68.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9930839 14.05% 82.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4875287 6.90% 89.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3134712 4.44% 93.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2288875 3.24% 96.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1259030 1.78% 98.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 656858 0.93% 99.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 168442 0.24% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 47218 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 48628565 68.46% 68.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10107628 14.23% 82.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4889823 6.88% 89.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3044033 4.29% 93.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2225901 3.13% 96.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1246231 1.75% 98.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 700109 0.99% 99.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 154501 0.22% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 37929 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 70661432 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 71034720 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 64961 14.10% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 14.10% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 248589 53.97% 68.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 147038 31.92% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 52156 10.93% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 267781 56.13% 67.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 157153 32.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3305 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34793099 69.54% 69.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56077 0.11% 69.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.66% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 13836 0.03% 69.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1652 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8926243 17.84% 87.53% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5486267 10.97% 98.49% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 753706 1.51% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 33971995 68.30% 68.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53580 0.11% 68.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15560 0.03% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.45% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9077168 18.25% 86.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5791424 11.64% 98.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 825016 1.66% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50034185 # Type of FU issued -system.cpu0.iq.rate 0.482197 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 460588 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.009205 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 170766492 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60297186 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48772869 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 486828 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 236130 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 232978 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50238035 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 253433 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 485739 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49739725 # Type of FU issued +system.cpu0.iq.rate 0.482739 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 477090 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.009592 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 170451707 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59601257 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48417922 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 610021 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 293075 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 290010 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 49893944 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 319543 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 495668 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1334836 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17971 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 25456 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 519571 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1332465 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15476 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20341 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 527918 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18977 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 164713 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 14091 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 218656 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1267055 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8486951 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 577503 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 56521315 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 733695 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9033738 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5759436 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1510903 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 459190 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7711 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 25456 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 319028 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 300441 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 619469 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49457194 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8612039 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 576990 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1215315 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6999311 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 544202 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 56199276 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 754553 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9180149 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6097470 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1645846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 470730 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6896 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20341 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 291584 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 326384 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 617968 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49204821 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8748371 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 534903 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3161127 # number of nop insts executed -system.cpu0.iew.exec_refs 14049434 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7908844 # Number of branches executed -system.cpu0.iew.exec_stores 5437395 # Number of stores executed -system.cpu0.iew.exec_rate 0.476636 # Inst execution rate -system.cpu0.iew.wb_sent 49114578 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49005847 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24510505 # num instructions producing a value -system.cpu0.iew.wb_consumers 32850763 # num instructions consuming a value +system.cpu0.iew.exec_nop 3129904 # number of nop insts executed +system.cpu0.iew.exec_refs 14495988 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7765506 # Number of branches executed +system.cpu0.iew.exec_stores 5747617 # Number of stores executed +system.cpu0.iew.exec_rate 0.477548 # Inst execution rate +system.cpu0.iew.wb_sent 48811342 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48707932 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23956930 # num instructions producing a value +system.cpu0.iew.wb_consumers 32092147 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.472286 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.746117 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.472725 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.746504 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 48687390 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 7735637 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 545080 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 563607 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 69394377 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.701604 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.587762 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 48759720 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 7342909 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 596992 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 565842 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 69819405 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.698369 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.595257 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 50596179 72.91% 72.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7970613 11.49% 84.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4358860 6.28% 90.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2336816 3.37% 94.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1278043 1.84% 95.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 512868 0.74% 96.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 404165 0.58% 97.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 607557 0.88% 98.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1329276 1.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 51124042 73.22% 73.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8032267 11.50% 84.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4140271 5.93% 90.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2329968 3.34% 93.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1273302 1.82% 95.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 518646 0.74% 96.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 361032 0.52% 97.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 714639 1.02% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1325238 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 69394377 # Number of insts commited each cycle -system.cpu0.commit.count 48687390 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 69819405 # Number of insts commited each cycle +system.cpu0.commit.count 48759720 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12938767 # Number of memory references committed -system.cpu0.commit.loads 7698902 # Number of loads committed -system.cpu0.commit.membars 184242 # Number of memory barriers committed -system.cpu0.commit.branches 7372386 # Number of branches committed -system.cpu0.commit.fp_insts 230446 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45102183 # Number of committed integer instructions. -system.cpu0.commit.function_calls 618802 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1329276 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13417236 # Number of memory references committed +system.cpu0.commit.loads 7847684 # Number of loads committed +system.cpu0.commit.membars 202015 # Number of memory barriers committed +system.cpu0.commit.branches 7296729 # Number of branches committed +system.cpu0.commit.fp_insts 287598 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45136958 # Number of committed integer instructions. +system.cpu0.commit.function_calls 626830 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1325238 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124302463 # The number of ROB reads -system.cpu0.rob.rob_writes 114114055 # The number of ROB writes -system.cpu0.timesIdled 1107408 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33101543 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 45891664 # Number of Instructions Simulated -system.cpu0.committedInsts_total 45891664 # Number of Instructions Simulated -system.cpu0.cpi 2.261042 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.261042 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.442274 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.442274 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65164143 # number of integer regfile reads -system.cpu0.int_regfile_writes 35661718 # number of integer regfile writes -system.cpu0.fp_regfile_reads 113503 # number of floating regfile reads -system.cpu0.fp_regfile_writes 115176 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1562482 # number of misc regfile reads -system.cpu0.misc_regfile_writes 761048 # number of misc regfile writes +system.cpu0.rob.rob_reads 124403287 # The number of ROB reads +system.cpu0.rob.rob_writes 113421475 # The number of ROB writes +system.cpu0.timesIdled 1076474 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32001726 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 45967748 # Number of Instructions Simulated +system.cpu0.committedInsts_total 45967748 # Number of Instructions Simulated +system.cpu0.cpi 2.241494 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.241494 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.446131 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.446131 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 64511715 # number of integer regfile reads +system.cpu0.int_regfile_writes 35217125 # number of integer regfile writes +system.cpu0.fp_regfile_reads 141815 # number of floating regfile reads +system.cpu0.fp_regfile_writes 144143 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1768684 # number of misc regfile reads +system.cpu0.misc_regfile_writes 843519 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 795450 # number of replacements -system.cpu0.icache.tagsinuse 509.996584 # Cycle average of tags in use -system.cpu0.icache.total_refs 7012391 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 795959 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.809990 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23368345000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.996584 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996087 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7012391 # 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number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12860430 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.189453 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.317978 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.110140 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.023991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.239880 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 13225697 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.174808 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.310439 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.103445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.016755 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.229734 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.239880 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.229734 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23031.276258 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23135.798695 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32484.113400 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30772.302080 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14742.718191 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14638.447797 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13738.006521 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12533.452808 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 27947.614931 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 27314.739160 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 27947.614931 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 27314.739160 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 874274400 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 238500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 96465 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 855518470 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 221500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 97807 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9063.125486 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 23850 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8747.006554 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 22150 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 701727 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 509168 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1351881 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4474 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1861049 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1861049 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 971332 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 252581 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 14546 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 4294 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1223913 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1223913 # number of overall MSHR misses +system.cpu0.dcache.writebacks 602926 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 516336 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1401114 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4413 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1917450 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1917450 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 859351 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 261593 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 15739 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 3348 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1120944 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1120944 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23290479000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 7870556900 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 149366500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 46100000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 31161035900 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 31161035900 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917406500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1329367998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2246774498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.124297 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 21884756500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 7717990970 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 167906500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 31911000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 29602747470 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 29602747470 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634931500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1090823998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 1725755498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109197 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050057 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.048841 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084232 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.080792 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.023991 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.016755 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.095169 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.084755 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.095169 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.084755 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23977.876771 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 31160.526326 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10268.561804 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10735.910573 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25460.172333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25460.172333 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 25466.609686 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29503.813061 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10668.180952 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 9531.362007 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 26408.765710 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 26408.765710 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2434396 # DTB read hits -system.cpu1.dtb.read_misses 12632 # DTB read misses -system.cpu1.dtb.read_acv 51 # DTB read access violations -system.cpu1.dtb.read_accesses 349555 # DTB read accesses -system.cpu1.dtb.write_hits 1633702 # DTB write hits -system.cpu1.dtb.write_misses 3988 # DTB write misses -system.cpu1.dtb.write_acv 91 # DTB write access violations -system.cpu1.dtb.write_accesses 134749 # DTB write accesses -system.cpu1.dtb.data_hits 4068098 # DTB hits -system.cpu1.dtb.data_misses 16620 # DTB misses -system.cpu1.dtb.data_acv 142 # DTB access violations -system.cpu1.dtb.data_accesses 484304 # DTB accesses -system.cpu1.itb.fetch_hits 488641 # ITB hits -system.cpu1.itb.fetch_misses 8868 # ITB misses -system.cpu1.itb.fetch_acv 207 # ITB acv -system.cpu1.itb.fetch_accesses 497509 # ITB accesses +system.cpu1.dtb.read_hits 2335038 # DTB read hits +system.cpu1.dtb.read_misses 11141 # DTB read misses +system.cpu1.dtb.read_acv 15 # DTB read access violations +system.cpu1.dtb.read_accesses 329726 # DTB read accesses +system.cpu1.dtb.write_hits 1301059 # DTB write hits +system.cpu1.dtb.write_misses 3075 # DTB write misses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_accesses 125932 # DTB write accesses +system.cpu1.dtb.data_hits 3636097 # DTB hits +system.cpu1.dtb.data_misses 14216 # DTB misses +system.cpu1.dtb.data_acv 78 # DTB access violations +system.cpu1.dtb.data_accesses 455658 # DTB accesses +system.cpu1.itb.fetch_hits 423788 # ITB hits +system.cpu1.itb.fetch_misses 7837 # ITB misses +system.cpu1.itb.fetch_acv 166 # ITB acv +system.cpu1.itb.fetch_accesses 431625 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -902,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 20348668 # number of cpu cycles simulated +system.cpu1.numCycles 20152954 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3352403 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2780204 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 112990 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 3035961 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1319312 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3242658 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2662310 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 131441 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2892914 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1375784 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 232566 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 9070 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 8042198 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 15968682 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3352403 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1551878 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2969461 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 549599 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 7368633 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27992 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 74441 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 61172 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1904129 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 71381 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 18894151 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.845165 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.201588 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 235158 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 7774 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 6188689 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16200802 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3242658 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1610942 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3090469 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 613653 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7714239 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65046 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 159598 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1940544 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 74817 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 17655267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.917619 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.257026 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15924690 84.28% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 239855 1.27% 85.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 362060 1.92% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 226098 1.20% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 430016 2.28% 90.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 142596 0.75% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 181045 0.96% 92.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 295229 1.56% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1092562 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 14564798 82.50% 82.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 197815 1.12% 83.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 462974 2.62% 86.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 255072 1.44% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 513820 2.91% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 162072 0.92% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 211046 1.20% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 121453 0.69% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1166217 6.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18894151 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164748 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.784753 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7867478 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7772170 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2762632 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 150042 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 341828 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 143049 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8486 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 15583049 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23483 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 341828 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8134306 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 601370 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6389331 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2635739 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 791575 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 14485157 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 185 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55864 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 183661 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 9468885 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 17315691 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 17110872 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 204819 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7931339 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1537546 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 569619 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 61560 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2500740 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2578124 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1732920 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 321113 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 190156 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12582391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 647000 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 12202318 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 26509 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1926210 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1020296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 460997 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 18894151 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.645825 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.311169 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 17655267 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.160902 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.803892 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6415483 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7821687 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2861971 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 154408 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 401717 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 149324 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8351 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 15726471 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21041 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 401717 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6681295 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2118018 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4943945 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2656010 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 854280 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 14736815 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 186 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 221815 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 138242 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 9911157 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 18088761 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 17988130 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 100631 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7897558 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2013599 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 424269 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 36275 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2592161 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2485755 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1426985 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 360752 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 285996 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12852454 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 484885 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 12271073 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 26221 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2300844 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1315458 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 356394 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 17655267 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.695038 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.354056 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 13531447 71.62% 71.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2408615 12.75% 84.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1089992 5.77% 90.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 719494 3.81% 93.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 600531 3.18% 97.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 311690 1.65% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 155684 0.82% 99.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 53025 0.28% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 23673 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 12407145 70.27% 70.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2235941 12.66% 82.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1035355 5.86% 88.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 796484 4.51% 93.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 626149 3.55% 96.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 333560 1.89% 98.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 156466 0.89% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 49558 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 14609 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 18894151 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 17655267 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4502 1.97% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 121874 53.21% 55.17% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 102674 44.83% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 13105 7.34% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 95150 53.29% 60.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 70292 39.37% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3982 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7613703 62.40% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19536 0.16% 62.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 13122 0.11% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1991 0.02% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2552683 20.92% 83.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1661486 13.62% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 335815 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 8216703 66.96% 66.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 19600 0.16% 67.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11030 0.09% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.02% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2431476 19.81% 87.07% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1328460 10.83% 97.90% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 257837 2.10% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 12202318 # Type of FU issued -system.cpu1.iq.rate 0.599662 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 229050 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.018771 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 43260661 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15016823 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11811979 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 293685 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 142362 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 139746 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12273711 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 153675 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 108256 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 12271073 # Type of FU issued +system.cpu1.iq.rate 0.608897 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 178547 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014550 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 42255695 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15570864 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11866318 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 146486 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 71642 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 70264 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12369614 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 76027 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 105474 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 372523 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7917 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4307 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 156502 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 463598 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 9284 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4789 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 195743 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 333 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 28285 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5212 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 50812 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 341828 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 445544 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 34164 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13910925 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 201807 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2578124 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1732920 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 582063 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 21599 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6281 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4307 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 78974 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 111447 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 190421 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 12072034 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2457890 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 130284 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 401717 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1622444 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 62821 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 14027082 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 177744 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2485755 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1426985 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 441055 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 11459 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3097 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4789 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 106850 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 88794 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 195644 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 12103351 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2352431 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 167722 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 681534 # number of nop insts executed -system.cpu1.iew.exec_refs 4103399 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1804932 # Number of branches executed -system.cpu1.iew.exec_stores 1645509 # Number of stores executed -system.cpu1.iew.exec_rate 0.593259 # Inst execution rate -system.cpu1.iew.wb_sent 11986744 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11951725 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5550831 # num instructions producing a value -system.cpu1.iew.wb_consumers 7770927 # num instructions consuming a value +system.cpu1.iew.exec_nop 689743 # number of nop insts executed +system.cpu1.iew.exec_refs 3661778 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1907962 # Number of branches executed +system.cpu1.iew.exec_stores 1309347 # Number of stores executed +system.cpu1.iew.exec_rate 0.600575 # Inst execution rate +system.cpu1.iew.wb_sent 11974198 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11936582 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5946561 # num instructions producing a value +system.cpu1.iew.wb_consumers 8293064 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.587347 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.714307 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.592299 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.717052 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 11805751 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 2024872 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 186003 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 175934 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 18552323 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.636349 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.571810 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 11515527 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 2436187 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 128491 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 177413 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 17253550 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.667429 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.563448 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 14118650 76.10% 76.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2051209 11.06% 87.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 792595 4.27% 91.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 477671 2.57% 94.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 327821 1.77% 95.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 149583 0.81% 96.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 116875 0.63% 97.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 167462 0.90% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 350457 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12827961 74.35% 74.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1952306 11.32% 85.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 928648 5.38% 91.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 493505 2.86% 93.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 338427 1.96% 95.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 153865 0.89% 96.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 124614 0.72% 97.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119099 0.69% 98.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 315125 1.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 18552323 # Number of insts commited each cycle -system.cpu1.commit.count 11805751 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 17253550 # Number of insts commited each cycle +system.cpu1.commit.count 11515527 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3782019 # Number of memory references committed -system.cpu1.commit.loads 2205601 # Number of loads committed -system.cpu1.commit.membars 61380 # Number of memory barriers committed -system.cpu1.commit.branches 1685692 # Number of branches committed -system.cpu1.commit.fp_insts 138212 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10911872 # Number of committed integer instructions. -system.cpu1.commit.function_calls 184868 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 350457 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3253399 # Number of memory references committed +system.cpu1.commit.loads 2022157 # Number of loads committed +system.cpu1.commit.membars 41280 # Number of memory barriers committed +system.cpu1.commit.branches 1729331 # Number of branches committed +system.cpu1.commit.fp_insts 68665 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 10682634 # Number of committed integer instructions. +system.cpu1.commit.function_calls 174972 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 315125 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 31928567 # The number of ROB reads -system.cpu1.rob.rob_writes 28001823 # The number of ROB writes -system.cpu1.timesIdled 205057 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1454517 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 11204705 # Number of Instructions Simulated -system.cpu1.committedInsts_total 11204705 # Number of Instructions Simulated -system.cpu1.cpi 1.816082 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816082 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550636 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550636 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 15543323 # number of integer regfile reads -system.cpu1.int_regfile_writes 8446180 # number of integer regfile writes -system.cpu1.fp_regfile_reads 74822 # number of floating regfile reads -system.cpu1.fp_regfile_writes 74815 # number of floating regfile writes -system.cpu1.misc_regfile_reads 675670 # number of misc regfile reads -system.cpu1.misc_regfile_writes 285692 # number of misc regfile writes -system.cpu1.icache.replacements 294345 # number of replacements -system.cpu1.icache.tagsinuse 471.340417 # Cycle average of tags in use -system.cpu1.icache.total_refs 1598818 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 294856 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.422369 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874432600000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 471.340417 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.920587 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 1598818 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1598818 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 1598818 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 30796624 # The number of ROB reads +system.cpu1.rob.rob_writes 28304513 # The number of ROB writes +system.cpu1.timesIdled 230784 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2497687 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 10925662 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10925662 # Number of Instructions Simulated +system.cpu1.cpi 1.844552 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.844552 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.542137 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.542137 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15857410 # number of integer regfile reads +system.cpu1.int_regfile_writes 8648406 # number of integer regfile writes +system.cpu1.fp_regfile_reads 40377 # number of floating regfile reads +system.cpu1.fp_regfile_writes 39511 # number of floating regfile writes +system.cpu1.misc_regfile_reads 441161 # number of misc regfile reads +system.cpu1.misc_regfile_writes 195544 # number of misc regfile writes +system.cpu1.icache.replacements 205961 # number of replacements +system.cpu1.icache.tagsinuse 502.866762 # Cycle average of tags in use +system.cpu1.icache.total_refs 1723284 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 206473 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.346292 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1708291874000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 502.866762 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.982162 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 1723284 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1723284 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 1723284 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1598818 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 1598818 # number of overall hits +system.cpu1.icache.demand_hits::total 1723284 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 1723284 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1598818 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 305311 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 305311 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 305311 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 1723284 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 217260 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 217260 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 217260 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 305311 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 305311 # number of overall misses +system.cpu1.icache.demand_misses::total 217260 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 217260 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 305311 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 4483412500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 4483412500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 4483412500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1904129 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1904129 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1904129 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 217260 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 3300371999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 3300371999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 3300371999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1940544 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1940544 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1940544 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1904129 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1904129 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1940544 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1940544 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1904129 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.160342 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.160342 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1940544 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.111958 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.111958 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.160342 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.111958 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14684.739495 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15190.886491 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14684.739495 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15190.886491 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14684.739495 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15190.886491 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 116500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 349000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6472.222222 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10575.757576 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 49 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 10391 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 10391 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 10391 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 294920 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 294920 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 294920 # number of overall MSHR misses +system.cpu1.icache.writebacks 52 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 10723 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 10723 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 10723 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 206537 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 206537 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 206537 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 3431981500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 3431981500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 3431981500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 2520725000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 2520725000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 2520725000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.154884 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.106433 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.154884 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.106433 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.154884 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.106433 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11636.991387 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11636.991387 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11636.991387 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12204.713925 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12204.713925 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12204.713925 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 154143 # number of replacements -system.cpu1.dcache.tagsinuse 476.574727 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3264047 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 154464 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 21.131442 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874646667000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 476.574727 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.930810 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1976745 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1976745 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 1193181 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1193181 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 47069 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47069 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 45973 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 45973 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 3169926 # 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number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 25812 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 24969 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 24969 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 2789010 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3169926 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 3169926 # number of overall hits +system.cpu1.dcache.demand_hits::total 2789010 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 2789010 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 3169926 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 282407 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 282407 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 325995 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 325995 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 7824 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 7824 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 4577 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 4577 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 608402 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 2789010 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 315850 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 315850 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 245510 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 245510 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 5339 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5339 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 3179 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3179 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 561360 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 608402 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 608402 # number of overall misses +system.cpu1.dcache.demand_misses::total 561360 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 561360 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 608402 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 4155262000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 7647875941 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 85879000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 62313500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 11803137941 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 11803137941 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 2259152 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2259152 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 1519176 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1519176 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 54893 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 54893 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 50550 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 50550 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 3778328 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 561360 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 4714821500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 8024030885 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 65075500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 42948000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 12738852385 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 12738852385 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 2154725 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2154725 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 1195645 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1195645 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 31151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 31151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 28148 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 28148 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 3350370 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3778328 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 3778328 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3350370 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 3350370 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3778328 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.125006 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.214587 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.142532 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.090544 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.161024 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 3350370 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.146585 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.205337 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.171391 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.112939 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.167552 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.161024 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.167552 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14713.735849 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 14927.406997 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 23460.101968 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32683.112236 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10976.354806 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12188.705750 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13614.485471 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13509.908776 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 19400.228699 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 22692.839506 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 19400.228699 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 22692.839506 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 94033995 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7725 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12172.685437 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 135872392 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 106000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 10757 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12631.067398 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 26500 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 103879 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 174324 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 267778 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 757 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 442102 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 442102 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 108083 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 58217 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 7067 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 4577 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 166300 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 166300 # number of overall MSHR misses +system.cpu1.dcache.writebacks 196815 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 98942 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 203211 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 1094 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 302153 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 302153 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 216908 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 42299 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 4245 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 3179 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 259207 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 259207 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 1297456000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1215847490 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 55744000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 48574500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 2513303490 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 2513303490 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 393979500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 412601000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.047842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2649753500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 1268849871 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 33277000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 33400500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 3918603371 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 3918603371 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 300850000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 586892500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 887742500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.100666 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.038321 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.035378 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128741 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136272 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.090544 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.112939 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.044014 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.077367 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.044014 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.077367 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12004.255988 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20884.749987 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7887.929815 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10612.737601 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15113.069693 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15113.069693 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12216.024766 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29997.160004 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7839.104829 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10506.605851 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 15117.660291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 15117.660291 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1403,164 +1403,160 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6679 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 170123 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 59613 40.27% 40.27% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.16% 40.44% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1922 1.30% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 309 0.21% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 85934 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 148015 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 58855 49.10% 49.10% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 237 0.20% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1922 1.60% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 309 0.26% 51.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 58546 48.84% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 119869 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860434296000 98.05% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90872000 0.00% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 391830000 0.02% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 123760000 0.01% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36487097000 1.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897527855000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.987285 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 5037 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186073 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65315 40.13% 40.13% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.15% 40.27% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.18% 41.46% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 222 0.14% 41.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 95069 58.41% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162766 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63957 49.17% 49.17% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.18% 49.35% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 1.48% 50.83% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 222 0.17% 51.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63735 49.00% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130074 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863353937000 98.10% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90928000 0.00% 98.11% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 390512500 0.02% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 85006500 0.00% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35490372000 1.87% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1899410756000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.979208 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681290 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.44% 12.92% # number of syscalls executed -system.cpu0.kern.syscall::6 31 14.83% 27.75% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 28.23% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.83% 32.06% # number of syscalls executed -system.cpu0.kern.syscall::19 9 4.31% 36.36% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.87% 39.23% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.48% 39.71% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.44% 41.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.87% 44.02% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.96% 44.98% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.79% 60.77% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.44% 62.20% # number of syscalls executed -system.cpu0.kern.syscall::48 9 4.31% 66.51% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.78% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 71.77% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.39% 74.16% # number of syscalls executed -system.cpu0.kern.syscall::71 23 11.00% 85.17% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.44% 86.60% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.87% 89.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 89.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.44% 91.39% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.31% 95.69% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.48% 98.09% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.96% 99.04% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.670408 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.88% 28.37% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 28.84% # number of syscalls executed +system.cpu0.kern.syscall::17 8 3.72% 32.56% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.65% 37.21% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.79% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.47% 40.47% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.40% 41.86% # number of syscalls executed +system.cpu0.kern.syscall::33 6 2.79% 44.65% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.93% 45.58% # number of syscalls executed +system.cpu0.kern.syscall::45 33 15.35% 60.93% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.40% 62.33% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.65% 66.98% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.65% 71.63% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 72.09% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.79% 74.88% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.70% 85.58% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.40% 86.98% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.79% 89.77% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 90.23% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.40% 91.63% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.19% 95.81% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.47% 98.14% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.93% 99.07% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 406 0.26% 0.26% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.26% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.26% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.26% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3167 2.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::tbi 45 0.03% 2.32% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed -system.cpu0.kern.callpal::swpipl 141170 90.48% 92.80% # number of callpals executed -system.cpu0.kern.callpal::rdps 6359 4.08% 96.88% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.88% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed -system.cpu0.kern.callpal::rti 4376 2.80% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 348 0.22% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 134 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 156029 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6806 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1160 # number of protection mode switches +system.cpu0.kern.callpal::wripir 307 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3778 2.20% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155399 90.68% 93.10% # number of callpals executed +system.cpu0.kern.callpal::rdps 6322 3.69% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rti 4984 2.91% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 369 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 171369 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7417 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1246 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1159 -system.cpu0.kern.mode_good::user 1160 +system.cpu0.kern.mode_good::kernel 1245 +system.cpu0.kern.mode_good::user 1246 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170291 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.167858 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895695413000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1832434000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1897486158000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1924590000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3168 # number of times the context was actually changed +system.cpu0.kern.swap_context 3779 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2565 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 71341 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 23380 38.18% 38.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 3.14% 41.31% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 406 0.66% 41.98% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 35533 58.02% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 61239 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 22761 47.98% 47.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 4.05% 52.02% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 406 0.86% 52.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22355 47.12% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 47442 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1868516653000 98.47% 98.47% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343880500 0.02% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 155607500 0.01% 98.50% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28447585000 1.50% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897463726000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.973524 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 4032 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 54228 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17280 37.82% 37.82% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 4.20% 42.02% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 307 0.67% 42.69% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26187 57.31% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45695 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17261 47.36% 47.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 5.27% 52.64% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 307 0.84% 53.48% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16954 46.52% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 36443 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869444423500 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 345691000 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 121909500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29169069500 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1899081093500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998900 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.629133 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.85% 12.82% # number of syscalls executed -system.cpu1.kern.syscall::6 11 9.40% 22.22% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.85% 23.08% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.98% 29.06% # number of syscalls executed -system.cpu1.kern.syscall::19 1 0.85% 29.91% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.56% 32.48% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.56% 35.04% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.27% 39.32% # number of syscalls executed -system.cpu1.kern.syscall::45 21 17.95% 57.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.56% 59.83% # number of syscalls executed -system.cpu1.kern.syscall::48 1 0.85% 60.68% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.71% 62.39% # number of syscalls executed -system.cpu1.kern.syscall::71 31 26.50% 88.89% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.55% 97.44% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.56% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.647420 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.90% 21.62% # number of syscalls executed +system.cpu1.kern.syscall::17 7 6.31% 27.93% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.70% 30.63% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.70% 33.33% # number of syscalls executed +system.cpu1.kern.syscall::33 5 4.50% 37.84% # number of syscalls executed +system.cpu1.kern.syscall::45 21 18.92% 56.76% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.70% 59.46% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.90% 60.36% # number of syscalls executed +system.cpu1.kern.syscall::71 31 27.93% 88.29% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.01% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.70% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 111 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 309 0.49% 0.49% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.49% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.49% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1667 2.62% 3.12% # number of callpals executed -system.cpu1.kern.callpal::tbi 9 0.01% 3.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 55390 87.20% 90.34% # number of callpals executed -system.cpu1.kern.callpal::rdps 2392 3.77% 94.10% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.10% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 94.11% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 94.11% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.12% # number of callpals executed -system.cpu1.kern.callpal::rti 3522 5.54% 99.66% # number of callpals executed -system.cpu1.kern.callpal::callsys 167 0.26% 99.92% # number of callpals executed -system.cpu1.kern.callpal::imb 47 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 222 0.47% 0.47% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.47% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.48% # number of callpals executed +system.cpu1.kern.callpal::swpctx 871 1.85% 2.32% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.33% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.34% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40736 86.30% 88.64% # number of callpals executed +system.cpu1.kern.callpal::rdps 2431 5.15% 93.79% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.79% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.80% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.81% # number of callpals executed +system.cpu1.kern.callpal::rti 2730 5.78% 99.59% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.31% 99.90% # number of callpals executed +system.cpu1.kern.callpal::imb 45 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 63524 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1934 # number of protection mode switches -system.cpu1.kern.mode_switch::user 578 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2650 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 909 -system.cpu1.kern.mode_good::user 578 -system.cpu1.kern.mode_good::idle 331 -system.cpu1.kern.mode_switch_good::kernel 0.470010 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 47204 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1142 # number of protection mode switches +system.cpu1.kern.mode_switch::user 492 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2462 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 761 +system.cpu1.kern.mode_good::user 492 +system.cpu1.kern.mode_good::idle 269 +system.cpu1.kern.mode_switch_good::kernel 0.666375 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.124906 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.594916 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6826914500 0.36% 0.36% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 949063500 0.05% 0.41% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1889043105000 99.59% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1668 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.109261 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.775636 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 35491661500 1.87% 1.87% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 858235500 0.05% 1.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862377378000 98.09% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 872 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 496218c55..4bc0cb36c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/arm/scratch/sysexplr/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/dist/m5/system/binaries/ts_osfpal +pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -496,7 +496,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -516,7 +516,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -645,7 +645,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index df759602b..a2519d6a4 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 9 2011 03:11:31 -gem5 started Aug 9 2011 03:11:36 -gem5 executing on burrito +gem5 compiled Aug 15 2011 20:24:21 +gem5 started Aug 15 2011 20:25:48 +gem5 executing on nadc-0270 command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1858690543500 because m5_exit instruction encountered +Exiting @ tick 1858708914500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 615b7b1c5..eab7f5386 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.858691 # Number of seconds simulated -sim_ticks 1858690543500 # Number of ticks simulated +sim_seconds 1.858709 # Number of seconds simulated +sim_ticks 1858708914500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131020 # Simulator instruction rate (inst/s) -host_tick_rate 4587017100 # Simulator tick rate (ticks/s) -host_mem_usage 315160 # Number of bytes of host memory used -host_seconds 405.21 # Real time elapsed on the host -sim_insts 53090369 # Number of instructions simulated -system.l2c.replacements 391395 # number of replacements -system.l2c.tagsinuse 34960.020004 # Cycle average of tags in use -system.l2c.total_refs 2406151 # Total number of references to valid blocks. -system.l2c.sampled_refs 424265 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.671340 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5621019000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12378.384666 # Average occupied blocks per context -system.l2c.occ_blocks::1 22581.635338 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188879 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.344568 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1801346 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1801346 # number of ReadReq hits -system.l2c.Writeback_hits::0 835143 # number of Writeback hits -system.l2c.Writeback_hits::total 835143 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits +host_inst_rate 124964 # Simulator instruction rate (inst/s) +host_tick_rate 4374927606 # Simulator tick rate (ticks/s) +host_mem_usage 340632 # Number of bytes of host memory used +host_seconds 424.85 # Real time elapsed on the host +sim_insts 53091761 # Number of instructions simulated +system.l2c.replacements 391302 # number of replacements +system.l2c.tagsinuse 34944.632545 # Cycle average of tags in use +system.l2c.total_refs 2405534 # Total number of references to valid blocks. +system.l2c.sampled_refs 424233 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.670313 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12322.596332 # Average occupied blocks per context +system.l2c.occ_blocks::1 22622.036213 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188028 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.345185 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1801216 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1801216 # number of ReadReq hits +system.l2c.Writeback_hits::0 835065 # number of Writeback hits +system.l2c.Writeback_hits::total 835065 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183109 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183109 # number of ReadExReq hits -system.l2c.demand_hits::0 1984455 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183191 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183191 # number of ReadExReq hits +system.l2c.demand_hits::0 1984407 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1984455 # number of demand (read+write) hits -system.l2c.overall_hits::0 1984455 # number of overall hits +system.l2c.demand_hits::total 1984407 # number of demand (read+write) hits +system.l2c.overall_hits::0 1984407 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1984455 # number of overall hits -system.l2c.ReadReq_misses::0 308108 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308108 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 34 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 34 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116921 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116921 # number of ReadExReq misses -system.l2c.demand_misses::0 425029 # number of demand (read+write) misses +system.l2c.overall_hits::total 1984407 # number of overall hits +system.l2c.ReadReq_misses::0 308126 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308126 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116919 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116919 # number of ReadExReq misses +system.l2c.demand_misses::0 425045 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 425029 # number of demand (read+write) misses -system.l2c.overall_misses::0 425029 # number of overall misses +system.l2c.demand_misses::total 425045 # number of demand (read+write) misses +system.l2c.overall_misses::0 425045 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 425029 # number of overall misses -system.l2c.ReadReq_miss_latency 16037313500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 372000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6133457500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22170771000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22170771000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2109454 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109454 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 835143 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835143 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::total 425045 # number of overall misses +system.l2c.ReadReq_miss_latency 16035962500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6137530000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22173492500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22173492500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2109342 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109342 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835065 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835065 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 44 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 44 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300030 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300030 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2409484 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300110 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300110 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2409452 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2409484 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2409484 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2409452 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2409452 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2409484 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146061 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.693878 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389698 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176398 # miss rate for demand accesses +system.l2c.overall_accesses::total 2409452 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146077 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.704545 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389587 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176407 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176398 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176407 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52050.948044 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52043.522780 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 10941.176471 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 13709.677419 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52458.134125 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52493.863273 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52162.960645 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52167.399922 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52162.960645 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52167.399922 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117784 # number of writebacks +system.l2c.writebacks 117722 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308108 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 34 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116921 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 425029 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 425029 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308126 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116919 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 425045 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 425045 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12333770000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1420000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4711661500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17045431500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17045431500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 810039500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1115188998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1925228498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12333217500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4715307000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17048524500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17048524500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 809593500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1114721998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1924315498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146077 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.693878 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.704545 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389587 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176398 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176407 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176398 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176407 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40030.671063 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41764.705882 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40297.820751 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.161128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.161128 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40026.539468 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40329.689785 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40109.928361 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.266648 # Cycle average of tags in use +system.iocache.tagsinuse 1.266801 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708339298000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.266648 # Average occupied blocks per context -system.iocache.occ_percent::1 0.079165 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338851000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.266801 # Average occupied blocks per context +system.iocache.occ_percent::1 0.079175 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -166,10 +166,10 @@ system.iocache.demand_misses::total 41725 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722104806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742044804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742044804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5722275806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742213804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742213804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -189,22 +189,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137709.491866 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137713.607191 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137616.412319 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137620.462648 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137616.412319 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137620.462648 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64599068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64594068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6174.638501 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6170.621704 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -216,10 +216,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561252994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572196992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572196992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561421998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572363996 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572363996 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -233,10 +233,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85705.934588 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85612.869790 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85612.869790 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85710.001877 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85616.872283 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10172213 # DTB read hits -system.cpu.dtb.read_misses 43494 # DTB read misses -system.cpu.dtb.read_acv 580 # DTB read access violations -system.cpu.dtb.read_accesses 956567 # DTB read accesses -system.cpu.dtb.write_hits 6637652 # DTB write hits -system.cpu.dtb.write_misses 9272 # DTB write misses -system.cpu.dtb.write_acv 322 # DTB write access violations -system.cpu.dtb.write_accesses 335213 # DTB write accesses -system.cpu.dtb.data_hits 16809865 # DTB hits -system.cpu.dtb.data_misses 52766 # DTB misses -system.cpu.dtb.data_acv 902 # DTB access violations -system.cpu.dtb.data_accesses 1291780 # DTB accesses -system.cpu.itb.fetch_hits 1342789 # ITB hits -system.cpu.itb.fetch_misses 39758 # ITB misses -system.cpu.itb.fetch_acv 1040 # ITB acv -system.cpu.itb.fetch_accesses 1382547 # ITB accesses +system.cpu.dtb.read_hits 10154080 # DTB read hits +system.cpu.dtb.read_misses 43144 # DTB read misses +system.cpu.dtb.read_acv 557 # DTB read access violations +system.cpu.dtb.read_accesses 952445 # DTB read accesses +system.cpu.dtb.write_hits 6614848 # DTB write hits +system.cpu.dtb.write_misses 9467 # DTB write misses +system.cpu.dtb.write_acv 320 # DTB write access violations +system.cpu.dtb.write_accesses 334339 # DTB write accesses +system.cpu.dtb.data_hits 16768928 # DTB hits +system.cpu.dtb.data_misses 52611 # DTB misses +system.cpu.dtb.data_acv 877 # DTB access violations +system.cpu.dtb.data_accesses 1286784 # DTB accesses +system.cpu.itb.fetch_hits 1336327 # ITB hits +system.cpu.itb.fetch_misses 39787 # ITB misses +system.cpu.itb.fetch_acv 1065 # ITB acv +system.cpu.itb.fetch_accesses 1376114 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,275 +285,275 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 117561370 # number of cpu cycles simulated +system.cpu.numCycles 117237485 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14512096 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12124763 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 534985 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13082442 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6780681 # Number of BTB hits +system.cpu.BPredUnit.lookups 14455551 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12084424 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 532367 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13050115 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6745735 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 985415 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44835 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29301348 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74523128 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14512096 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7766096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14456496 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2475230 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37352483 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32620 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 262284 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 336025 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 123 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9183314 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 332127 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 83379045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.893787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.210786 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 978348 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45278 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29236023 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74164805 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14455551 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7724083 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14385478 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2439202 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37224537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 262840 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335923 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9135306 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 83080083 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.892691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.209867 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68922549 82.66% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1028480 1.23% 83.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2035774 2.44% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 998762 1.20% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2982144 3.58% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 700003 0.84% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 807750 0.97% 92.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1076941 1.29% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4826642 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68694605 82.68% 82.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1023953 1.23% 83.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2033478 2.45% 86.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 975932 1.17% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2976777 3.58% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 700548 0.84% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 794915 0.96% 92.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1072238 1.29% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4807637 5.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 83379045 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123443 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.633908 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30625799 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36960246 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13171913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1025264 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1595822 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 618911 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72819380 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 127184 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1595822 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31874108 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12944384 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19864625 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12330385 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4769719 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68803114 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4210 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 997602 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1469982 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 46108022 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 83655268 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 83175686 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479582 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38259780 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7848234 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700711 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251216 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12962201 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10843547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7060604 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2097425 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2214211 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 60377206 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2118999 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58263583 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82757 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9009938 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4851831 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1451256 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 83379045 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.698780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.313076 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 83080083 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123301 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632603 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30551542 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36838313 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13095678 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034253 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1560296 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 613869 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42144 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72480994 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 127271 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1560296 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31800995 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12812731 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19871114 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12262779 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4772166 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68475649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4094 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 996372 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1464404 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45853535 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 83251938 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82772461 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479477 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38260770 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7592757 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700825 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251533 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12956852 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10812074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7051744 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2165147 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2346616 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 60096918 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2117388 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58031681 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 82818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8738509 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4816872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1449642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 83080083 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.698503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.311149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56881095 68.22% 68.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11965083 14.35% 82.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5985120 7.18% 89.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3573465 4.29% 94.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2606291 3.13% 97.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1333403 1.60% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 786052 0.94% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 188914 0.23% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 59622 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56639169 68.17% 68.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11994103 14.44% 82.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5929931 7.14% 89.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3560683 4.29% 94.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2591551 3.12% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1336446 1.61% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 797054 0.96% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 184259 0.22% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 46887 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 83379045 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 83080083 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66647 11.94% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 311938 55.88% 67.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 179673 32.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 68783 12.83% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 305726 57.04% 69.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161454 30.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39837502 68.37% 68.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 63640 0.11% 68.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25605 0.04% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10651640 18.28% 86.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6721971 11.54% 98.37% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952308 1.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39661101 68.34% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62145 0.11% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25610 0.04% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10623971 18.31% 86.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6695582 11.54% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952355 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58263583 # Type of FU issued -system.cpu.iq.rate 0.495601 # Inst issue rate -system.cpu.iq.fu_busy_cnt 558258 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009582 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 199861715 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 71197744 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56697880 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 685510 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 334104 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327554 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58457489 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 357071 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 546714 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 58031681 # Type of FU issued +system.cpu.iq.rate 0.494993 # Inst issue rate +system.cpu.iq.fu_busy_cnt 535963 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009236 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 199072460 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 70641414 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56449878 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 689765 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 333951 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328040 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58199260 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361103 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 552721 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1730283 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13242 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28963 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 668160 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1698615 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 23451 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 659180 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18982 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 168763 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 200829 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1595822 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9001389 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 625458 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 66156357 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 866739 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10843547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7060604 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1871783 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 491434 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13753 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28963 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 389249 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383472 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 772721 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57555020 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10245935 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 708562 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1560296 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8872665 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 625505 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65852816 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871025 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10812074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7051744 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1870069 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 491565 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7470 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 23451 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 385257 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383183 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 768440 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57350351 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10227555 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 681329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3660152 # number of nop insts executed -system.cpu.iew.exec_refs 16908045 # number of memory reference insts executed -system.cpu.iew.exec_branches 9133755 # Number of branches executed -system.cpu.iew.exec_stores 6662110 # Number of stores executed -system.cpu.iew.exec_rate 0.489574 # Inst execution rate -system.cpu.iew.wb_sent 57159115 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 57025434 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28218942 # num instructions producing a value -system.cpu.iew.wb_consumers 38051860 # num instructions consuming a value +system.cpu.iew.exec_nop 3638510 # number of nop insts executed +system.cpu.iew.exec_refs 16867130 # number of memory reference insts executed +system.cpu.iew.exec_branches 9102477 # Number of branches executed +system.cpu.iew.exec_stores 6639575 # Number of stores executed +system.cpu.iew.exec_rate 0.489181 # Inst execution rate +system.cpu.iew.wb_sent 56909286 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56777918 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28083144 # num instructions producing a value +system.cpu.iew.wb_consumers 37838196 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.485069 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.741592 # average fanout of values written-back +system.cpu.iew.wb_rate 0.484298 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742190 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56284997 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9746037 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667743 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 704725 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 81783223 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.688222 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.561458 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56286421 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9443080 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667746 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 702134 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 81519787 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.690463 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.566765 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59869495 73.21% 73.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9271272 11.34% 84.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5260342 6.43% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2449132 2.99% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1675900 2.05% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 634046 0.78% 96.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 464374 0.57% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 783725 0.96% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1374937 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59658965 73.18% 73.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9249179 11.35% 84.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5213125 6.39% 90.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2451549 3.01% 93.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1701758 2.09% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 617367 0.76% 96.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 434350 0.53% 97.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 791574 0.97% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1401920 1.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 81783223 # Number of insts commited each cycle -system.cpu.commit.count 56284997 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 81519787 # Number of insts commited each cycle +system.cpu.commit.count 56286421 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15505708 # Number of memory references committed -system.cpu.commit.loads 9113264 # Number of loads committed -system.cpu.commit.membars 227891 # Number of memory barriers committed -system.cpu.commit.branches 8461884 # Number of branches committed -system.cpu.commit.fp_insts 324250 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52123418 # Number of committed integer instructions. -system.cpu.commit.function_calls 744517 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1374937 # number cycles where commit BW limit reached +system.cpu.commit.refs 15506023 # Number of memory references committed +system.cpu.commit.loads 9113459 # Number of loads committed +system.cpu.commit.membars 227879 # Number of memory barriers committed +system.cpu.commit.branches 8462155 # Number of branches committed +system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52124782 # Number of committed integer instructions. +system.cpu.commit.function_calls 744514 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1401920 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 146188247 # The number of ROB reads -system.cpu.rob.rob_writes 133660667 # The number of ROB writes -system.cpu.timesIdled 1252693 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34182325 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53090369 # Number of Instructions Simulated -system.cpu.committedInsts_total 53090369 # Number of Instructions Simulated -system.cpu.cpi 2.214363 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.214363 # CPI: Total CPI of All Threads -system.cpu.ipc 0.451597 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.451597 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75435318 # number of integer regfile reads -system.cpu.int_regfile_writes 41215589 # number of integer regfile writes -system.cpu.fp_regfile_reads 165687 # number of floating regfile reads -system.cpu.fp_regfile_writes 167399 # number of floating regfile writes -system.cpu.misc_regfile_reads 1995946 # number of misc regfile reads -system.cpu.misc_regfile_writes 949866 # number of misc regfile writes +system.cpu.rob.rob_reads 145596309 # The number of ROB reads +system.cpu.rob.rob_writes 133022104 # The number of ROB writes +system.cpu.timesIdled 1258228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34157402 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53091761 # Number of Instructions Simulated +system.cpu.committedInsts_total 53091761 # Number of Instructions Simulated +system.cpu.cpi 2.208205 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.208205 # CPI: Total CPI of All Threads +system.cpu.ipc 0.452857 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.452857 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75150720 # number of integer regfile reads +system.cpu.int_regfile_writes 41017067 # number of integer regfile writes +system.cpu.fp_regfile_reads 166113 # number of floating regfile reads +system.cpu.fp_regfile_writes 167453 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996494 # number of misc regfile reads +system.cpu.misc_regfile_writes 949911 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1005223 # number of replacements -system.cpu.icache.tagsinuse 509.948854 # Cycle average of tags in use -system.cpu.icache.total_refs 8118172 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005732 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.071904 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23367175000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.948854 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995994 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8118173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8118173 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8118173 # number of demand (read+write) hits +system.cpu.icache.replacements 1005090 # number of replacements +system.cpu.icache.tagsinuse 509.951538 # Cycle average of tags in use +system.cpu.icache.total_refs 8070754 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005599 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.025817 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23351335000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.951538 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995999 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8070755 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8070755 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8070755 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8118173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8118173 # number of overall hits +system.cpu.icache.demand_hits::total 8070755 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8070755 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8118173 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1065140 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1065140 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8070755 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1064551 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064551 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1064551 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1065140 # number of overall misses +system.cpu.icache.demand_misses::total 1064551 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1064551 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1065140 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15927800996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15927800996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15927800996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9183313 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9183313 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9183313 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1064551 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15926988994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15926988994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15926988994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9135306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9135306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9135306 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9183313 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9183313 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9135306 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9135306 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9183313 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.115986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.115986 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9135306 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.116532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.116532 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.115986 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.116532 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14953.715940 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14961.226840 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14953.715940 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14961.226840 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14953.715940 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14961.226840 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1340497 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1261996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10987.680328 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10516.633333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 231 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 59195 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 59195 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 59195 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005945 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005945 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005945 # number of overall MSHR misses +system.cpu.icache.writebacks 232 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 58739 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 58739 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 58739 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005812 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005812 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005812 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12050423497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12050423497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12050423497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12051659996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12051659996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12051659996 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.109541 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110102 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.109541 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.110102 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.109541 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.110102 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.207111 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11979.207111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11979.207111 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.020493 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11982.020493 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1403249 # number of replacements -system.cpu.dcache.tagsinuse 511.995942 # Cycle average of tags in use -system.cpu.dcache.total_refs 12177929 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403761 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.675215 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19464000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995942 # Average occupied blocks per context +system.cpu.dcache.replacements 1403296 # number of replacements +system.cpu.dcache.tagsinuse 511.995990 # Cycle average of tags in use +system.cpu.dcache.total_refs 12128638 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403808 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.639813 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.995990 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7541924 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7541924 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4223581 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4223581 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192169 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192169 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220074 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220074 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11765505 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7493448 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7493448 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4222901 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4222901 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192043 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192043 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220080 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220080 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11716349 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11765505 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11765505 # number of overall hits +system.cpu.dcache.demand_hits::total 11716349 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11716349 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11765505 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1785380 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1785380 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1933647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1933647 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 23245 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23245 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11716349 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1778869 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1778869 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1934444 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1934444 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 23262 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23262 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3719027 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3713313 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3719027 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3719027 # number of overall misses +system.cpu.dcache.demand_misses::total 3713313 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3713313 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3719027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38531981000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57348648047 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 361113000 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3713313 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38377192500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57331444318 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 363604000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 95880629047 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 95880629047 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9327304 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9327304 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6157228 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157228 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 215414 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215414 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220076 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220076 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15484532 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 95708636818 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 95708636818 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9272317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9272317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6157345 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157345 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 215305 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215305 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220082 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220082 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15429662 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15484532 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15484532 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15429662 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15429662 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15484532 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.191414 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314045 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.107908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15429662 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.191847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314169 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108042 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.240177 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.240661 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.240177 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.240661 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21581.949501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21573.928434 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29658.282017 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29637.169294 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15535.082814 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15630.814203 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25781.105931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25774.459847 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25781.105931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25774.459847 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 904772827 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 266500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 99710 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9074.042995 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22208.333333 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 916364836 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 209000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 100291 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9137.059517 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23222.222222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834912 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 697810 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1634824 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5710 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2332634 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2332634 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087570 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298823 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17535 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834833 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 691203 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1635634 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5726 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2326837 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2326837 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087666 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298810 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17536 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386393 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386393 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386476 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386476 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24793495000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8488664327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207086500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24813377000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8487477836 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207860000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33282159327 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33282159327 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904509000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234461998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138970998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116601 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33300854836 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33300854836 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904007000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234009498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2138016498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117303 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048529 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081401 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081447 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089534 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089858 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089534 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089858 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22797.148689 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28406.997878 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11809.894497 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22813.416067 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28404.263030 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11853.330292 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24006.294988 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24006.294988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24018.342067 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -818,26 +818,26 @@ system.cpu.dcache.soft_prefetch_mshr_full 0 # n system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211584 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 244 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74884 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 241 0.13% 41.09% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105811 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182814 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 244 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105815 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182822 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73517 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149150 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819958547500 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94089500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384592500 0.02% 97.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38252453500 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1858689683000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73519 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149159 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1820013648500 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 93762000 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384408000 0.02% 97.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38216235500 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858708054000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981745 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694767 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694788 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -873,32 +873,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::swpipl 175485 91.19% 93.39% # number of callpals executed system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5216 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192432 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.callpal::total 192443 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2101 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.320067 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.320349 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080438 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400505 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29488985500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2865820500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826334869000 98.26% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080914 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401263 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29483328500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2787065000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1826437652500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 43cca93f6..4a2cdb533 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -15,7 +15,7 @@ boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 m flags_addr=0 gic_cpu_addr=0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -501,7 +501,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/arm/scratch/sysexplr/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -553,7 +553,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.port[25] -mem_side=system.membus.port[6] +mem_side=system.membus.port[7] [system.l2c] type=BaseCache @@ -585,7 +585,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[7] +mem_side=system.membus.port[8] [system.membus] type=Bus @@ -597,7 +597,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side +port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -628,7 +628,7 @@ port=system.membus.port[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -836,6 +836,18 @@ update_data=false warn_access= pio=system.membus.port[4] +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clock=1000 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=1000 +platform=system.realview +system=system +pio=system.membus.port[6] + [system.realview.mmc_fake] type=AmbaFake amba_id=0 diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 707979289..3ff5b25a6 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 9 2011 03:11:31 -gem5 started Aug 9 2011 03:11:37 -gem5 executing on burrito +gem5 compiled Aug 16 2011 18:25:06 +gem5 started Aug 16 2011 18:26:03 +gem5 executing on nadc-0270 command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 80748998500 because m5_exit instruction encountered +Exiting @ tick 79671140500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index d56f088ea..149a25fba 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,97 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.080749 # Number of seconds simulated -sim_ticks 80748998500 # Number of ticks simulated +sim_seconds 0.079671 # Number of seconds simulated +sim_ticks 79671140500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110010 # Simulator instruction rate (inst/s) -host_tick_rate 171236576 # Simulator tick rate (ticks/s) -host_mem_usage 368976 # Number of bytes of host memory used -host_seconds 471.56 # Real time elapsed on the host -sim_insts 51876948 # Number of instructions simulated -system.l2c.replacements 94981 # number of replacements -system.l2c.tagsinuse 38166.685860 # Cycle average of tags in use -system.l2c.total_refs 1060946 # Total number of references to valid blocks. -system.l2c.sampled_refs 127430 # Sample count of references to valid blocks. -system.l2c.avg_refs 8.325716 # Average number of references to valid blocks. +host_inst_rate 87754 # Simulator instruction rate (inst/s) +host_tick_rate 134768287 # Simulator tick rate (ticks/s) +host_mem_usage 390652 # Number of bytes of host memory used +host_seconds 591.17 # Real time elapsed on the host +sim_insts 51877383 # Number of instructions simulated +system.l2c.replacements 94989 # number of replacements +system.l2c.tagsinuse 38233.191793 # Cycle average of tags in use +system.l2c.total_refs 1049232 # Total number of references to valid blocks. +system.l2c.sampled_refs 127381 # Sample count of references to valid blocks. +system.l2c.avg_refs 8.236958 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6723.855274 # Average occupied blocks per context -system.l2c.occ_blocks::1 31442.830586 # Average occupied blocks per context -system.l2c.occ_percent::0 0.102598 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.479780 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 746399 # number of ReadReq hits -system.l2c.ReadReq_hits::1 123135 # number of ReadReq hits -system.l2c.ReadReq_hits::total 869534 # number of ReadReq hits -system.l2c.Writeback_hits::0 435298 # number of Writeback hits -system.l2c.Writeback_hits::total 435298 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 60890 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60890 # number of ReadExReq hits -system.l2c.demand_hits::0 807289 # number of demand (read+write) hits -system.l2c.demand_hits::1 123135 # number of demand (read+write) hits -system.l2c.demand_hits::total 930424 # number of demand (read+write) hits -system.l2c.overall_hits::0 807289 # number of overall hits -system.l2c.overall_hits::1 123135 # number of overall hits -system.l2c.overall_hits::total 930424 # number of overall hits -system.l2c.ReadReq_misses::0 21130 # number of ReadReq misses -system.l2c.ReadReq_misses::1 101 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21231 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1677 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1677 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 107756 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107756 # number of ReadExReq misses -system.l2c.demand_misses::0 128886 # number of demand (read+write) misses -system.l2c.demand_misses::1 101 # number of demand (read+write) misses -system.l2c.demand_misses::total 128987 # number of demand (read+write) misses -system.l2c.overall_misses::0 128886 # number of overall misses -system.l2c.overall_misses::1 101 # number of overall misses -system.l2c.overall_misses::total 128987 # number of overall misses -system.l2c.ReadReq_miss_latency 1109806000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 780500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 5651942000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 6761748000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 6761748000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 767529 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 123236 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 890765 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 435298 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 435298 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1701 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1701 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 168646 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168646 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 936175 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 123236 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1059411 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 936175 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 123236 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1059411 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027530 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000820 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028349 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.985891 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.638948 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.137673 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000820 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.138493 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.137673 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000820 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.138493 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52522.763843 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 10988178.217822 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 11040700.981665 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 465.414431 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 6845.786735 # Average occupied blocks per context +system.l2c.occ_blocks::1 31387.405058 # Average occupied blocks per context +system.l2c.occ_percent::0 0.104458 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.478934 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 745449 # number of ReadReq hits +system.l2c.ReadReq_hits::1 96884 # number of ReadReq hits +system.l2c.ReadReq_hits::total 842333 # number of ReadReq hits +system.l2c.Writeback_hits::0 434303 # number of Writeback hits +system.l2c.Writeback_hits::total 434303 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 53 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 53 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 11 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 61363 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 61363 # number of ReadExReq hits +system.l2c.demand_hits::0 806812 # number of demand (read+write) hits +system.l2c.demand_hits::1 96884 # number of demand (read+write) hits +system.l2c.demand_hits::total 903696 # number of demand (read+write) hits +system.l2c.overall_hits::0 806812 # number of overall hits +system.l2c.overall_hits::1 96884 # number of overall hits +system.l2c.overall_hits::total 903696 # number of overall hits +system.l2c.ReadReq_misses::0 21092 # number of ReadReq misses +system.l2c.ReadReq_misses::1 91 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21183 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1724 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1724 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 107716 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107716 # number of ReadExReq misses +system.l2c.demand_misses::0 128808 # number of demand (read+write) misses +system.l2c.demand_misses::1 91 # number of demand (read+write) misses +system.l2c.demand_misses::total 128899 # number of demand (read+write) misses +system.l2c.overall_misses::0 128808 # number of overall misses +system.l2c.overall_misses::1 91 # number of overall misses +system.l2c.overall_misses::total 128899 # number of overall misses +system.l2c.ReadReq_miss_latency 1106899000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 5649720000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 6756619000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 6756619000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 766541 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 96975 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 863516 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 434303 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 434303 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1777 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1777 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 11 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 169079 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169079 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 935620 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 96975 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1032595 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 935620 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 96975 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1032595 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027516 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000938 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028454 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.970174 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.637075 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.137671 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000938 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.138610 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.137671 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000938 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.138610 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52479.565712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12163725.274725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12216204.840437 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 392.111369 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52451.297376 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52450.146682 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52463.013826 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 66948000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 67000463.013826 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52463.013826 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 66948000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 67000463.013826 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52454.963977 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 74248560.439560 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 74301015.403538 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52454.963977 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 74248560.439560 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 74301015.403538 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,44 +104,44 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 87796 # number of writebacks -system.l2c.ReadReq_mshr_hits 58 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 58 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 58 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 21173 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1677 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 107756 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 128929 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 128929 # number of overall MSHR misses +system.l2c.writebacks 87788 # number of writebacks +system.l2c.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 54 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 21129 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1724 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 107716 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 128845 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 128845 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 848032500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 67081500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4311568500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 5159601000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 5159601000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 28946618000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 748818447 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 29695436447 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.171809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.199394 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.985891 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 846282000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 68961500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4309813000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 5156095000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 5156095000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 28946860000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 748497446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29695357446 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027564 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.217881 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.245445 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.970174 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.638948 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.637075 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.137719 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.046196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.183915 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.137719 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.046196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.183915 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40052.543333 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.894454 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40012.328780 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.137711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.328641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.466352 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.137711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.328641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.466352 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40053.102371 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.870070 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40010.889747 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -146,27 +150,27 @@ system.l2c.soft_prefetch_mshr_full 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 28177040 # DTB read hits -system.cpu.dtb.read_misses 72386 # DTB read misses -system.cpu.dtb.write_hits 7691310 # DTB write hits -system.cpu.dtb.write_misses 13556 # DTB write misses +system.cpu.dtb.read_hits 13454003 # DTB read hits +system.cpu.dtb.read_misses 56352 # DTB read misses +system.cpu.dtb.write_hits 7087382 # DTB write hits +system.cpu.dtb.write_misses 9992 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 2922 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 4054 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1092 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 2710 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2485 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 940 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 28249426 # DTB read accesses -system.cpu.dtb.write_accesses 7704866 # DTB write accesses +system.cpu.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 13510355 # DTB read accesses +system.cpu.dtb.write_accesses 7097374 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 35868350 # DTB hits -system.cpu.dtb.misses 85942 # DTB misses -system.cpu.dtb.accesses 35954292 # DTB accesses -system.cpu.itb.inst_hits 7355634 # ITB inst hits -system.cpu.itb.inst_misses 7654 # ITB inst misses +system.cpu.dtb.hits 20541385 # DTB hits +system.cpu.dtb.misses 66344 # DTB misses +system.cpu.dtb.accesses 20607729 # DTB accesses +system.cpu.itb.inst_hits 6364119 # ITB inst hits +system.cpu.itb.inst_misses 7846 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -175,502 +179,515 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 1641 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1638 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4616 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4337 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 7363288 # ITB inst accesses -system.cpu.itb.hits 7355634 # DTB hits -system.cpu.itb.misses 7654 # DTB misses -system.cpu.itb.accesses 7363288 # DTB accesses -system.cpu.numCycles 161497998 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 6371965 # ITB inst accesses +system.cpu.itb.hits 6364119 # DTB hits +system.cpu.itb.misses 7846 # DTB misses +system.cpu.itb.accesses 6371965 # DTB accesses +system.cpu.numCycles 159342282 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13590326 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11456360 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 648707 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12127952 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9362916 # Number of BTB hits +system.cpu.BPredUnit.lookups 12557399 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10608534 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 646709 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11154990 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8780554 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 895596 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 148738 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 16866017 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 67484906 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13590326 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 10258512 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17034266 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4123173 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 93207 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 55393473 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 18245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 90602 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7350509 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 337942 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4453 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 92525962 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.899758 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.157294 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 870083 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 147860 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16065730 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 58984795 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12557399 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9650637 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15473829 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2924896 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 92331 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 54317634 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 13079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 97476 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 352 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 6359256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271099 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4481 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 88159945 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.843576 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.082771 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75510639 81.61% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1420262 1.53% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1864587 2.02% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1402898 1.52% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4892259 5.29% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 936046 1.01% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 818442 0.88% 93.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 713663 0.77% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4967166 5.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 72705101 82.47% 82.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1269251 1.44% 83.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1767868 2.01% 85.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1323104 1.50% 87.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4670929 5.30% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 784846 0.89% 93.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 764674 0.87% 94.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 594095 0.67% 95.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4280077 4.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 92525962 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.084152 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.417868 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 18966191 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 54065669 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 15364429 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1171991 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2957682 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1326698 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 73964 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80385244 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 241077 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2957682 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20606631 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33478689 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16542065 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 13879452 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5061443 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 77021348 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458130 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 143873 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2652425 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 147 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 79088993 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 335825078 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335758422 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 66656 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 51887194 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27201798 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 847863 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 665654 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14013888 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 13554810 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9178167 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 336 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 727 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 69117949 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4041398 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 82091279 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 240337 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20597655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41996969 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1078579 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 92525962 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.887224 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.470662 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 88159945 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078808 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.370177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 18165141 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 52904570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13778388 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1284946 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2026900 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1217125 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 74219 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71956332 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 242640 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2026900 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19696589 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 30046666 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18688452 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12532114 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5169224 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 69519785 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458017 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 271395 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2649588 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 136 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 71288380 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 300070248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 300002932 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 67316 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 51888569 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 19399810 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 812076 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 663924 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14280198 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 12080470 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8183550 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3516652 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4162890 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62699092 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4040128 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 64163344 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 176578 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14335802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 27947195 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1077859 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 88159945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.727806 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.267218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58116859 62.81% 62.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14058568 15.19% 78.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6650411 7.19% 85.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4537690 4.90% 90.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6374184 6.89% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1626800 1.76% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 758213 0.82% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 287091 0.31% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 116146 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 57192817 64.87% 64.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14605860 16.57% 81.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7161098 8.12% 89.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4501948 5.11% 94.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2827013 3.21% 97.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1117751 1.27% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 514797 0.58% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 165433 0.19% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 73228 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 92525962 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 88159945 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 27856 0.57% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4535089 92.61% 93.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 334124 6.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31666 2.83% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 952275 85.11% 87.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 134939 12.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2393223 2.92% 2.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 42162127 51.36% 54.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 71788 0.09% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29248881 35.63% 89.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 8214337 10.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2393223 3.73% 3.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39946954 62.26% 65.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 68785 0.11% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 1 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 14271744 22.24% 88.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7481749 11.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 82091279 # Type of FU issued -system.cpu.iq.rate 0.508311 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4897070 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.059654 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 261914662 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 94097771 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 62682872 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16678 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9625 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6496 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 84586375 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8751 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 425783 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 64163344 # Type of FU issued +system.cpu.iq.rate 0.402676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1118882 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017438 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 217833874 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81127166 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 59171315 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14043 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6386 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 62881739 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7264 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 405736 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4375336 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13490 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 405193 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2100755 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2901377 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4794 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 62495 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1106451 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17024856 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9533 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3460272 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8665 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2957682 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 21379595 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 254604 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 73328942 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 354348 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 13554810 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9178167 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4009809 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13226 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41705 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 405193 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 534373 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 174123 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 708496 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 80713996 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28682342 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1377283 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2026900 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18611531 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438534 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 66914101 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 333018 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 12080470 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8183550 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4008088 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 19000 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 218050 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 62495 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 538548 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 174972 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713520 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 63251439 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 13958320 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 911905 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 169595 # number of nop insts executed -system.cpu.iew.exec_refs 36687563 # number of memory reference insts executed -system.cpu.iew.exec_branches 10549834 # Number of branches executed -system.cpu.iew.exec_stores 8005221 # Number of stores executed -system.cpu.iew.exec_rate 0.499783 # Inst execution rate -system.cpu.iew.wb_sent 80082379 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 62689368 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33196620 # num instructions producing a value -system.cpu.iew.wb_consumers 59589146 # num instructions consuming a value +system.cpu.iew.exec_nop 174881 # number of nop insts executed +system.cpu.iew.exec_refs 21351791 # number of memory reference insts executed +system.cpu.iew.exec_branches 10154168 # Number of branches executed +system.cpu.iew.exec_stores 7393471 # Number of stores executed +system.cpu.iew.exec_rate 0.396953 # Inst execution rate +system.cpu.iew.wb_sent 62861793 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 59177701 # cumulative count of insts written-back +system.cpu.iew.wb_producers 31313815 # num instructions producing a value +system.cpu.iew.wb_consumers 56258797 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.388174 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557092 # average fanout of values written-back +system.cpu.iew.wb_rate 0.371387 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.556603 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 52000178 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 19092846 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2962819 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 623054 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 89568308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.580564 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.463287 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 52000613 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 12648879 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2962269 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 619998 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 86133073 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.603724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.472813 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 69902534 78.04% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9240090 10.32% 88.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2668754 2.98% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1387483 1.55% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3444879 3.85% 96.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 818955 0.91% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 553093 0.62% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 352878 0.39% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1199642 1.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 65560207 76.12% 76.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10449932 12.13% 88.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2547278 2.96% 91.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1482527 1.72% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3350826 3.89% 96.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 701267 0.81% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 459898 0.53% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 309587 0.36% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1271551 1.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 89568308 # Number of insts commited each cycle -system.cpu.commit.count 52000178 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 86133073 # Number of insts commited each cycle +system.cpu.commit.count 52000613 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 16256886 # Number of memory references committed -system.cpu.commit.loads 9179474 # Number of loads committed +system.cpu.commit.refs 16256192 # Number of memory references committed +system.cpu.commit.loads 9179093 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.branches 8429121 # Number of branches committed +system.cpu.commit.branches 8429232 # Number of branches committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.int_insts 42423758 # Number of committed integer instructions. -system.cpu.commit.function_calls 530189 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1199642 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 42424073 # Number of committed integer instructions. +system.cpu.commit.function_calls 530211 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1271551 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 158520597 # The number of ROB reads -system.cpu.rob.rob_writes 145188457 # The number of ROB writes -system.cpu.timesIdled 1073623 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68972036 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 51876948 # Number of Instructions Simulated -system.cpu.committedInsts_total 51876948 # Number of Instructions Simulated -system.cpu.cpi 3.113098 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.113098 # CPI: Total CPI of All Threads -system.cpu.ipc 0.321223 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.321223 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 356113054 # number of integer regfile reads -system.cpu.int_regfile_writes 64703490 # number of integer regfile writes -system.cpu.fp_regfile_reads 5644 # number of floating regfile reads -system.cpu.fp_regfile_writes 1932 # number of floating regfile writes -system.cpu.misc_regfile_reads 88421211 # number of misc regfile reads -system.cpu.misc_regfile_writes 512467 # number of misc regfile writes -system.cpu.icache.replacements 513097 # number of replacements -system.cpu.icache.tagsinuse 496.956364 # Cycle average of tags in use -system.cpu.icache.total_refs 6781343 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 513609 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.203318 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5987250000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 496.956364 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.970618 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 6781343 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6781343 # number of ReadReq hits -system.cpu.icache.demand_hits::0 6781343 # number of demand (read+write) hits +system.cpu.rob.rob_reads 148569921 # The number of ROB reads +system.cpu.rob.rob_writes 131336271 # The number of ROB writes +system.cpu.timesIdled 1042391 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 71182337 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 51877383 # Number of Instructions Simulated +system.cpu.committedInsts_total 51877383 # Number of Instructions Simulated +system.cpu.cpi 3.071517 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.071517 # CPI: Total CPI of All Threads +system.cpu.ipc 0.325572 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.325572 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 282588210 # number of integer regfile reads +system.cpu.int_regfile_writes 61106256 # number of integer regfile writes +system.cpu.fp_regfile_reads 4893 # number of floating regfile reads +system.cpu.fp_regfile_writes 1856 # number of floating regfile writes +system.cpu.misc_regfile_reads 78190097 # number of misc regfile reads +system.cpu.misc_regfile_writes 511386 # number of misc regfile writes +system.cpu.icache.replacements 514643 # number of replacements +system.cpu.icache.tagsinuse 498.228732 # Cycle average of tags in use +system.cpu.icache.total_refs 5803201 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 515155 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.264961 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 4757853000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 498.228732 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.973103 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 5803201 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5803201 # number of ReadReq hits +system.cpu.icache.demand_hits::0 5803201 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6781343 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 6781343 # number of overall hits +system.cpu.icache.demand_hits::total 5803201 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 5803201 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 6781343 # number of overall hits -system.cpu.icache.ReadReq_misses::0 569051 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 569051 # number of ReadReq misses -system.cpu.icache.demand_misses::0 569051 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 5803201 # number of overall hits +system.cpu.icache.ReadReq_misses::0 555943 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 555943 # number of ReadReq misses +system.cpu.icache.demand_misses::0 555943 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 569051 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 569051 # number of overall misses +system.cpu.icache.demand_misses::total 555943 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 555943 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 569051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8379802495 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8379802495 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8379802495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 7350394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7350394 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 7350394 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 555943 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8279205988 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8279205988 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8279205988 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 6359144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6359144 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 6359144 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7350394 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 7350394 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 6359144 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 6359144 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7350394 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.077418 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.077418 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 6359144 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.087424 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.087424 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.077418 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.087424 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14725.925260 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14892.184969 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14725.925260 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14892.184969 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14725.925260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14892.184969 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1742497 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1847492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 239 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7813.887892 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7730.092050 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 42974 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 55439 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 55439 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 55439 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 513612 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 513612 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 513612 # number of overall MSHR misses +system.cpu.icache.writebacks 43333 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 40711 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 40711 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 40711 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 515232 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 515232 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 515232 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6212945497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6212945497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6212945497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 6216481992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6216481992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6216481992 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 5831500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 5831500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069875 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.081022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.069875 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.081022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.069875 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.081022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12096.573867 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12096.573867 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12096.573867 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12065.403531 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12065.403531 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12065.403531 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 424539 # number of replacements -system.cpu.dcache.tagsinuse 511.742336 # Cycle average of tags in use -system.cpu.dcache.total_refs 14092021 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 425051 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.153718 # Average number of references to valid blocks. +system.cpu.dcache.replacements 422430 # number of replacements +system.cpu.dcache.tagsinuse 511.738850 # Cycle average of tags in use +system.cpu.dcache.total_refs 13008876 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 422942 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.758061 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48622000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.742336 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 9263117 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 9263117 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4618459 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4618459 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 103676 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 103676 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 104941 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 104941 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 13881576 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.738850 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999490 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 8178281 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8178281 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4620670 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4620670 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 103371 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 103371 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 104399 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 104399 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 12798951 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13881576 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 13881576 # number of overall hits +system.cpu.dcache.demand_hits::total 12798951 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 12798951 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13881576 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 533393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 533393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2044461 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2044461 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 6632 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6632 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 2577854 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 12798951 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 482976 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 482976 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2042377 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2042377 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 6546 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6546 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 11 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 2525353 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2577854 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2577854 # number of overall misses +system.cpu.dcache.demand_misses::total 2525353 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2525353 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2577854 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 7849628500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 81637522770 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 99339500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 89487151270 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 89487151270 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9796510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9796510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6662920 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6662920 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 110308 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 110308 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 104941 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 104941 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 16459430 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 2525353 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 7135135000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 80554552279 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 99000500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 159000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 87689687279 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 87689687279 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 8661257 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8661257 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6663047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6663047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 109917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 109917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 104410 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 104410 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15324304 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16459430 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 16459430 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15324304 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15324304 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16459430 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.054447 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.306842 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.156619 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 15324304 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.055763 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.306523 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059554 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000105 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.164794 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.156619 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.164794 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14716.407039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 14773.270307 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 39931.073652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 39441.568466 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14978.814837 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15123.816071 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34713.816713 # average overall miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14454.545455 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34723.734575 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34713.816713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34723.734575 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9881489 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 841000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1354 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.997784 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 7890493 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 750500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1025 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7698.041951 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 30020 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 392324 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 282537 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1874151 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1046 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2156688 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2156688 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 250856 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 170310 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 5586 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 421166 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 421166 # number of overall MSHR misses +system.cpu.dcache.writebacks 390970 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 234674 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1871578 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 927 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2106252 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2106252 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 248302 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 170799 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5619 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 419101 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 419101 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3355794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 6558107489 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66303500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9913901489 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9913901489 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199628000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 946945664 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 39146573664 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025607 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3306153500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 6559898993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66534000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 121000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9866052493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9866052493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199897500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 945697168 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 39145594668 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.028668 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025561 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025634 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051120 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025588 # mshr miss rate for demand accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000105 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.027349 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025588 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.027349 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13377.371879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.884440 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11869.584676 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13315.049818 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38407.127635 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11840.896957 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 334b73543..97c12ec46 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 70d5b6fa2..3bb35a882 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -1300,7 +1300,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/chips/pd/randd/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1320,7 +1320,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index cf1d2e1e5..1778e84dc 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 14 2011 17:50:33 -gem5 started Aug 14 2011 17:50:50 -gem5 executing on burrito +gem5 compiled Aug 15 2011 11:12:24 +gem5 started Aug 15 2011 11:17:26 +gem5 executing on u200439-lin.austin.arm.com command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /chips/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5147635094500 because m5_exit instruction encountered +Exiting @ tick 5151638875500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 220e5eac6..34270b518 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.147635 # Number of seconds simulated -sim_ticks 5147635094500 # Number of ticks simulated +sim_seconds 5.151639 # Number of seconds simulated +sim_ticks 5151638875500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 351632 # Simulator instruction rate (inst/s) -host_tick_rate 2155130798 # Simulator tick rate (ticks/s) -host_mem_usage 384428 # Number of bytes of host memory used -host_seconds 2388.55 # Real time elapsed on the host -sim_insts 839890138 # Number of instructions simulated -system.l2c.replacements 168889 # number of replacements -system.l2c.tagsinuse 38220.032298 # Cycle average of tags in use -system.l2c.total_refs 3756292 # Total number of references to valid blocks. -system.l2c.sampled_refs 202498 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.549773 # Average number of references to valid blocks. +host_inst_rate 136272 # Simulator instruction rate (inst/s) +host_tick_rate 835912815 # Simulator tick rate (ticks/s) +host_mem_usage 404376 # Number of bytes of host memory used +host_seconds 6162.89 # Real time elapsed on the host +sim_insts 839831731 # Number of instructions simulated +system.l2c.replacements 168782 # number of replacements +system.l2c.tagsinuse 38205.196893 # Cycle average of tags in use +system.l2c.total_refs 3762867 # Total number of references to valid blocks. +system.l2c.sampled_refs 202558 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.576739 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11771.329873 # Average occupied blocks per context -system.l2c.occ_blocks::1 26448.702425 # Average occupied blocks per context -system.l2c.occ_percent::0 0.179616 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403575 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2324685 # number of ReadReq hits -system.l2c.ReadReq_hits::1 121813 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2446498 # number of ReadReq hits -system.l2c.Writeback_hits::0 1589010 # number of Writeback hits -system.l2c.Writeback_hits::total 1589010 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 347 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150926 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150926 # number of ReadExReq hits -system.l2c.demand_hits::0 2475611 # number of demand (read+write) hits -system.l2c.demand_hits::1 121813 # number of demand (read+write) hits -system.l2c.demand_hits::total 2597424 # number of demand (read+write) hits -system.l2c.overall_hits::0 2475611 # number of overall hits -system.l2c.overall_hits::1 121813 # number of overall hits -system.l2c.overall_hits::total 2597424 # number of overall hits -system.l2c.ReadReq_misses::0 64844 # number of ReadReq misses -system.l2c.ReadReq_misses::1 78 # number of ReadReq misses -system.l2c.ReadReq_misses::total 64922 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3952 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3952 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 141925 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141925 # number of ReadExReq misses -system.l2c.demand_misses::0 206769 # number of demand (read+write) misses -system.l2c.demand_misses::1 78 # number of demand (read+write) misses -system.l2c.demand_misses::total 206847 # number of demand (read+write) misses -system.l2c.overall_misses::0 206769 # number of overall misses -system.l2c.overall_misses::1 78 # number of overall misses -system.l2c.overall_misses::total 206847 # number of overall misses -system.l2c.ReadReq_miss_latency 3405563500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 38740500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7426067500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10831631000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10831631000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2389529 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 121891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2511420 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1589010 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1589010 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4299 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4299 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292851 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292851 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2682380 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 121891 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2804271 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2682380 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 121891 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2804271 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027137 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000640 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027777 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.919284 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.484632 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.077084 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000640 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.077724 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.077084 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000640 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.077724 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52519.331010 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 43661070.512821 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 43713589.843830 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 9802.758097 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11735.089031 # Average occupied blocks per context +system.l2c.occ_blocks::1 26470.107863 # Average occupied blocks per context +system.l2c.occ_percent::0 0.179063 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.403902 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2331067 # number of ReadReq hits +system.l2c.ReadReq_hits::1 125887 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2456954 # number of ReadReq hits +system.l2c.Writeback_hits::0 1588356 # number of Writeback hits +system.l2c.Writeback_hits::total 1588356 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 357 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 357 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150454 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150454 # number of ReadExReq hits +system.l2c.demand_hits::0 2481521 # number of demand (read+write) hits +system.l2c.demand_hits::1 125887 # number of demand (read+write) hits +system.l2c.demand_hits::total 2607408 # number of demand (read+write) hits +system.l2c.overall_hits::0 2481521 # number of overall hits +system.l2c.overall_hits::1 125887 # number of overall hits +system.l2c.overall_hits::total 2607408 # number of overall hits +system.l2c.ReadReq_misses::0 64696 # number of ReadReq misses +system.l2c.ReadReq_misses::1 91 # number of ReadReq misses +system.l2c.ReadReq_misses::total 64787 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3960 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3960 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142190 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142190 # number of ReadExReq misses +system.l2c.demand_misses::0 206886 # number of demand (read+write) misses +system.l2c.demand_misses::1 91 # number of demand (read+write) misses +system.l2c.demand_misses::total 206977 # number of demand (read+write) misses +system.l2c.overall_misses::0 206886 # number of overall misses +system.l2c.overall_misses::1 91 # number of overall misses +system.l2c.overall_misses::total 206977 # number of overall misses +system.l2c.ReadReq_miss_latency 3398610000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 37586500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7439728500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10838338500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10838338500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2395763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 125978 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2521741 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1588356 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1588356 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4317 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4317 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292644 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292644 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2688407 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 125978 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2814385 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2688407 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 125978 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2814385 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027004 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000722 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027727 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.917304 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.485880 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.076955 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000722 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.077677 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.076955 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000722 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.077677 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52531.995796 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 37347362.637363 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 37399894.633158 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 9491.540404 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52323.885855 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52322.445320 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52385.178629 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 138867064.102564 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 138919449.281193 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52385.178629 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 138867064.102564 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 138919449.281193 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52387.974537 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 119102620.879121 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 119155008.853658 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52387.974537 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 119102620.879121 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 119155008.853658 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142854 # number of writebacks +system.l2c.writebacks 142964 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 64920 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3952 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 141925 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 206845 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 206845 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 64785 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3960 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142190 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 206975 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 206975 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2614002500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 158446500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5695372500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8309375000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8309375000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61532786000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222293500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62755079500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027169 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.532607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.559776 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.919284 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2608555500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 158748000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5705556000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8314111500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8314111500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61533015500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1222291500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62755307000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027041 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.514256 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.541298 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.917304 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.484632 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.485880 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.077112 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.696967 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.774079 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.077112 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.696967 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.774079 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40264.979975 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.737854 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40129.452175 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40171.988687 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40171.988687 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.076988 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.642946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.719934 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.076988 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.642946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.719934 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40264.806668 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40087.878788 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40126.281736 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40169.641261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40169.641261 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.153668 # Cycle average of tags in use +system.iocache.replacements 47575 # number of replacements +system.iocache.tagsinuse 0.165993 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994556805000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.153668 # Average occupied blocks per context -system.iocache.occ_percent::1 0.009604 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994554828000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.165993 # Average occupied blocks per context +system.iocache.occ_percent::1 0.010375 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.ReadReq_misses::1 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47627 # number of demand (read+write) misses -system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.demand_misses::1 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47627 # number of overall misses -system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency 113709932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6375573160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6489283092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6489283092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency 113908932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6372665160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6486574092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6486574092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125369.274531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125312.356436 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136463.466610 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136401.223459 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136252.190816 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136189.592307 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136252.190816 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136189.592307 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68827406 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68832452 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11262 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11274 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6111.472740 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6105.415292 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks +system.iocache.writebacks 46668 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses +system.iocache.demand_mshr_misses 47629 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47629 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66523980 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3945823756 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4012347736 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4012347736 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66617982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3942909802 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4009527784 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4009527784 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73345.071665 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84456.844092 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84245.233502 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84245.233502 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73287.108911 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84394.473502 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84182.489324 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84182.489324 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -255,140 +255,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449675417 # number of cpu cycles simulated +system.cpu.numCycles 449440116 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91353557 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91353557 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1252427 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 90165441 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83892399 # Number of BTB hits +system.cpu.BPredUnit.lookups 91251942 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91251942 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1248755 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89986362 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83883414 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28404587 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 452020244 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91353557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83892399 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171490466 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6282228 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 138765 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82802558 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39799 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48979 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9973165 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 538692 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4066 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 287848736 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.084298 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403265 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28443020 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 451559426 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91251942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83883414 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171343402 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6212938 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 155361 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82525667 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48486 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9929678 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 556225 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4240 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 287412747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.086350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403158 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116937192 40.62% 40.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1491081 0.52% 41.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72826914 25.30% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1443953 0.50% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1857439 0.65% 67.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4043841 1.40% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1607058 0.56% 69.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2086920 0.73% 70.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85554338 29.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116615067 40.57% 40.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1502902 0.52% 41.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72824785 25.34% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1334009 0.46% 66.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1960992 0.68% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4008264 1.39% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1565099 0.54% 69.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2187101 0.76% 70.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85414528 29.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 287848736 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203154 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.005214 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33515134 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79162809 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165880226 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4367269 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4923298 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 883825801 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 605 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4923298 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37698163 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52621688 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10095648 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165755555 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16754384 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 879127879 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13400 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11681979 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2180375 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 881488672 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1726997540 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1726996684 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 856 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843288974 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38199691 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 489429 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 491577 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43341957 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19857410 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10789691 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3385955 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3355339 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 872068801 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 901279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866609285 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 183699 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32269790 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 48278487 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 149791 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 287848736 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.010641 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.369672 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 287412747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.203035 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.004715 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33501642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 78913894 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165819274 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4318222 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4859715 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 883193903 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 620 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4859715 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37708099 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52423571 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10078562 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165633752 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16709048 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 878518097 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 13834 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11653087 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2148761 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 880915046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1725729327 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1725728311 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1016 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843223982 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 37691057 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 489641 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 492542 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43070507 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19803638 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10755992 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3194647 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3198862 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 871443389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 900411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 866326988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165756 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 31682293 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47289832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 148825 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 287412747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.014226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.369116 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82414213 28.63% 28.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23159181 8.05% 36.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14360314 4.99% 41.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9848044 3.42% 45.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79584318 27.65% 72.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4908294 1.71% 74.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72848439 25.31% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 591496 0.21% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 134437 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82109167 28.57% 28.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23029898 8.01% 36.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14429245 5.02% 41.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9845202 3.43% 45.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79549613 27.68% 72.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4871174 1.69% 74.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72852960 25.35% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 572992 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152496 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 287848736 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 287412747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190888 9.04% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1791204 84.82% 93.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 129613 6.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 198235 9.39% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1790050 84.77% 94.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 123321 5.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 300110 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 831340529 95.93% 95.96% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 300321 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 831068974 95.93% 95.96% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.96% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.96% # Type of FU issued @@ -417,252 +418,252 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.96% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25503279 2.94% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9465367 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25494883 2.94% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9462810 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866609285 # Type of FU issued -system.cpu.iq.rate 1.927188 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2111705 # FU busy when requested +system.cpu.iq.FU_type_0::total 866326988 # Type of FU issued +system.cpu.iq.rate 1.927569 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2111606 # FU busy when requested system.cpu.iq.fu_busy_rate 0.002437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2023502478 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 905270549 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855795997 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 118 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 426 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 39 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868420821 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1311302 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 2022483969 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 904056296 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 855552025 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 163 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 498 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 868138190 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1311048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4519097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14074 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32279 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2365528 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4470522 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13972 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 31558 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2334229 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7816755 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 157456 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7818225 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 154758 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4923298 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33675049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6020092 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 872970080 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 307769 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19857410 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10789736 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 900477 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5569363 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 25535 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32279 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 904299 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 527474 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1431773 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864483471 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25041287 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2125813 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4859715 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33597470 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6022609 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 872343800 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 300494 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19803638 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10756022 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5535817 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26257 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 31558 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 897955 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 529978 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1427933 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 864227296 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25025491 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2099691 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34281165 # number of memory reference insts executed -system.cpu.iew.exec_branches 86747902 # Number of branches executed -system.cpu.iew.exec_stores 9239878 # Number of stores executed -system.cpu.iew.exec_rate 1.922461 # Inst execution rate -system.cpu.iew.wb_sent 863862887 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855796036 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671971409 # num instructions producing a value -system.cpu.iew.wb_consumers 1172569006 # num instructions consuming a value +system.cpu.iew.exec_refs 34264216 # number of memory reference insts executed +system.cpu.iew.exec_branches 86728541 # Number of branches executed +system.cpu.iew.exec_stores 9238725 # Number of stores executed +system.cpu.iew.exec_rate 1.922898 # Inst execution rate +system.cpu.iew.wb_sent 863623792 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 855552085 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671682498 # num instructions producing a value +system.cpu.iew.wb_consumers 1172193952 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903142 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.573076 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903595 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573013 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839890138 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 32974049 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 751486 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1258131 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282941233 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.968426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.859611 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839831731 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 32406647 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 751584 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1254294 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 282568841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.972131 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.859839 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102772882 36.32% 36.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13081684 4.62% 40.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4919909 1.74% 42.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76957003 27.20% 69.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4031247 1.42% 71.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1851904 0.65% 71.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1144492 0.40% 72.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71610729 25.31% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6571383 2.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102495617 36.27% 36.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13009464 4.60% 40.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4878881 1.73% 42.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76962899 27.24% 69.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4022439 1.42% 71.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1857740 0.66% 71.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1158664 0.41% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71619728 25.35% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6563409 2.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282941233 # Number of insts commited each cycle -system.cpu.commit.count 839890138 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 282568841 # Number of insts commited each cycle +system.cpu.commit.count 839831731 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23762518 # Number of memory references committed -system.cpu.commit.loads 15338310 # Number of loads committed +system.cpu.commit.refs 23754906 # Number of memory references committed +system.cpu.commit.loads 15333113 # Number of loads committed system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85528433 # Number of branches committed +system.cpu.commit.branches 85519800 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768507409 # Number of committed integer instructions. +system.cpu.commit.int_insts 768449243 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6571383 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6563409 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1149152761 # The number of ROB reads -system.cpu.rob.rob_writes 1750664129 # The number of ROB writes -system.cpu.timesIdled 3067558 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 161826681 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839890138 # Number of Instructions Simulated -system.cpu.committedInsts_total 839890138 # Number of Instructions Simulated -system.cpu.cpi 0.535398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.535398 # CPI: Total CPI of All Threads -system.cpu.ipc 1.867770 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.867770 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1406887924 # number of integer regfile reads -system.cpu.int_regfile_writes 857851212 # number of integer regfile writes -system.cpu.fp_regfile_reads 39 # number of floating regfile reads -system.cpu.misc_regfile_reads 282323555 # number of misc regfile reads -system.cpu.misc_regfile_writes 407360 # number of misc regfile writes -system.cpu.icache.replacements 1023301 # number of replacements -system.cpu.icache.tagsinuse 510.501366 # Cycle average of tags in use -system.cpu.icache.total_refs 8883561 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1023813 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.676937 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54617484000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.501366 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8883561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8883561 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8883561 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1148162427 # The number of ROB reads +system.cpu.rob.rob_writes 1749350545 # The number of ROB writes +system.cpu.timesIdled 3069835 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162027369 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839831731 # Number of Instructions Simulated +system.cpu.committedInsts_total 839831731 # Number of Instructions Simulated +system.cpu.cpi 0.535155 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535155 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868618 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868618 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1406651660 # number of integer regfile reads +system.cpu.int_regfile_writes 857603051 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.misc_regfile_reads 282221875 # number of misc regfile reads +system.cpu.misc_regfile_writes 407507 # number of misc regfile writes +system.cpu.icache.replacements 1029232 # number of replacements +system.cpu.icache.tagsinuse 510.471706 # Cycle average of tags in use +system.cpu.icache.total_refs 8833811 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029744 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.578648 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54597932000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.471706 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997015 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8833811 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8833811 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8833811 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8883561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8883561 # number of overall hits +system.cpu.icache.demand_hits::total 8833811 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8833811 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8883561 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1089602 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1089602 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1089602 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8833811 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1095865 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1095865 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1095865 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1089602 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1089602 # number of overall misses +system.cpu.icache.demand_misses::total 1095865 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1095865 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1089602 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16315202989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16315202989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16315202989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9973163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9973163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9973163 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1095865 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16411974488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16411974488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16411974488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9929676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9929676 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9929676 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9973163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9973163 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9929676 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9929676 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9973163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.109253 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.109253 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9929676 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.110363 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.110363 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.109253 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.110363 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14973.543541 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14976.273983 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14973.543541 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14976.273983 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14973.543541 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14976.273983 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2502991 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2523491 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 249 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 250 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10052.172691 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10093.964000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1566 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 63225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 63225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 63225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1026377 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1026377 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1026377 # number of overall MSHR misses +system.cpu.icache.writebacks 1562 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 63554 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 63554 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 63554 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1032311 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1032311 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1032311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12387818491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12387818491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12387818491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12460934991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12460934991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12460934991 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.102914 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.103962 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.102914 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.103962 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.102914 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.103962 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12069.462284 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12069.462284 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12069.462284 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12070.911761 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12070.911761 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12070.911761 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10573 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.015451 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 26778 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10582 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.530524 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5110516160500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.015451 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.375966 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 26928 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26928 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 11904 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.021281 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25742 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 11916 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.160289 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5113551809500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 6.021281 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.376330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 25787 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25787 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 26931 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26931 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 25790 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25790 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 26931 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26931 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 11444 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11444 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 25790 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25790 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 12756 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 12756 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 11444 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11444 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 12756 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 12756 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 11444 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11444 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 147254000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 147254000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 147254000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 38372 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38372 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 12756 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 12756 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 165450000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 165450000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 165450000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 38543 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38543 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 38375 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38375 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 38546 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38546 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 38375 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38375 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.298238 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 38546 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38546 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.330955 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.298215 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.330929 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.298215 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.330929 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12867.354072 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12970.366886 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12867.354072 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12970.366886 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12867.354072 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12970.366886 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -672,83 +673,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 1953 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2156 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 11444 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 11444 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 11444 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 12756 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 12756 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 12756 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 112503000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 112503000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 112503000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 126704000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 126704000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 126704000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.298238 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.330955 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.298215 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.330929 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.298215 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.330929 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9830.741000 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9830.741000 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9830.741000 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9932.894324 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9932.894324 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9932.894324 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 121016 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.855490 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 127830 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 121032 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.056167 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101318853000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.855490 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.865968 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 127830 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 127830 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 123389 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.858352 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 128795 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 123405 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.043677 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101298251000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.858352 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866147 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 128795 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 128795 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 127830 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 127830 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 128795 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 128795 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 127830 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 127830 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 121934 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 121934 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 128795 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 128795 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 124284 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 124284 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 121934 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 121934 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 124284 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 124284 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 121934 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 121934 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1683985000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1683985000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1683985000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 249764 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 249764 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 124284 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 124284 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 1723739000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 1723739000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 1723739000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 253079 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 253079 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 249764 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 249764 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 253079 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 253079 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 249764 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 249764 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.488197 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 253079 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 253079 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.491088 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.488197 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.491088 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.488197 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.491088 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13810.627061 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13869.355669 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13810.627061 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13869.355669 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13810.627061 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13869.355669 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -758,136 +759,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 38699 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 38359 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 121934 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 121934 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 121934 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 124284 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 124284 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 124284 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1314199000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1314199000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1314199000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1347076500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1347076500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1347076500 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.488197 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.491088 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.488197 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.491088 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.488197 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.491088 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10777.953647 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10777.953647 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10777.953647 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10838.696051 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10838.696051 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10838.696051 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1658649 # number of replacements -system.cpu.dcache.tagsinuse 511.998343 # Cycle average of tags in use -system.cpu.dcache.total_refs 17949632 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1659161 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.818499 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1658768 # number of replacements +system.cpu.dcache.tagsinuse 511.997453 # Cycle average of tags in use +system.cpu.dcache.total_refs 17937343 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1659280 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.810317 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998343 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11386734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11386734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6540638 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6540638 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17927372 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.997453 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11377605 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11377605 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6537446 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6537446 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17915051 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17927372 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17927372 # number of overall hits +system.cpu.dcache.demand_hits::total 17915051 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17915051 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17927372 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2451014 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2451014 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1874260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1874260 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4325274 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17915051 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2443873 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2443873 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1875033 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1875033 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4318906 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4325274 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4325274 # number of overall misses +system.cpu.dcache.demand_misses::total 4318906 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4318906 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4325274 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 36760499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 62950533530 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 99711033030 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 99711033030 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13837748 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13837748 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8414898 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8414898 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22252646 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4318906 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 36695573000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63002180530 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 99697753530 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 99697753530 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13821478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13821478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8412479 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8412479 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22233957 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22252646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22252646 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22233957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22233957 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22252646 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.177125 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222731 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.194371 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22233957 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.176817 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222887 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.194248 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.194371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.194248 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14998.078142 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15015.335494 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33586.873502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33600.571579 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23053.113636 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23084.029504 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23053.113636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23084.029504 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1060124132 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6661500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 70229 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 395 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15095.247433 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16864.556962 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1066704607 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6645500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 69708 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15302.470405 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16996.163683 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1546792 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1084106 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1577234 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2661340 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2661340 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1366908 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 297026 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1663934 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1663934 # number of overall MSHR misses +system.cpu.dcache.writebacks 1546279 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1076649 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1578166 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2654815 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2654815 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1367224 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 296867 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1664091 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1664091 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18014700500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9717717632 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27732418132 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27732418132 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947187500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385675500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88332863000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098781 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18012012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9730106607 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27742119107 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27742119107 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947466500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385748000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88333214500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098920 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035289 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074775 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074845 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074845 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13179.160924 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32716.723896 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16666.777728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16666.777728 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13174.148859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32775.979166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16671.034882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16671.034882 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency |