diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/long/10.linux-boot | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/long/10.linux-boot')
16 files changed, 3786 insertions, 3797 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index f372f8ce3..51444fd65 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/arm/scratch/sysexplr/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -933,7 +933,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -953,7 +953,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1082,7 +1082,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 72ae91dc7..35487e816 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 16:33:41 -gem5 started Aug 17 2011 16:35:58 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 15:21:47 +gem5 started Aug 20 2011 15:21:55 +gem5 executing on zizzer command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 98887000 -Exiting @ tick 1897470973500 because m5_exit instruction encountered +info: Launching CPU 1 @ 106949500 +Exiting @ tick 1897465263500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d4f86dcbd..d2a095e1d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897471 # Number of seconds simulated -sim_ticks 1897470973500 # Number of ticks simulated +sim_seconds 1.897465 # Number of seconds simulated +sim_ticks 1897465263500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112670 # Simulator instruction rate (inst/s) -host_tick_rate 3808310962 # Simulator tick rate (ticks/s) -host_mem_usage 344004 # Number of bytes of host memory used -host_seconds 498.24 # Real time elapsed on the host -sim_insts 56137023 # Number of instructions simulated -system.l2c.replacements 397425 # number of replacements -system.l2c.tagsinuse 35089.523512 # Cycle average of tags in use -system.l2c.total_refs 2483901 # Total number of references to valid blocks. -system.l2c.sampled_refs 433413 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.731026 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9244135000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11999.654790 # Average occupied blocks per context -system.l2c.occ_blocks::1 233.124353 # Average occupied blocks per context -system.l2c.occ_blocks::2 22856.744369 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183100 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003557 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.348766 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1722706 # number of ReadReq hits -system.l2c.ReadReq_hits::1 146059 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1868765 # number of ReadReq hits -system.l2c.Writeback_hits::0 827102 # number of Writeback hits -system.l2c.Writeback_hits::total 827102 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 226 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 168351 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 11011 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179362 # number of ReadExReq hits -system.l2c.demand_hits::0 1891057 # number of demand (read+write) hits -system.l2c.demand_hits::1 157070 # number of demand (read+write) hits +host_inst_rate 131766 # Simulator instruction rate (inst/s) +host_tick_rate 4454253159 # Simulator tick rate (ticks/s) +host_mem_usage 298700 # Number of bytes of host memory used +host_seconds 425.99 # Real time elapsed on the host +sim_insts 56130966 # Number of instructions simulated +system.l2c.replacements 397795 # number of replacements +system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use +system.l2c.total_refs 2482671 # Total number of references to valid blocks. +system.l2c.sampled_refs 433561 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.726232 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12003.983788 # Average occupied blocks per context +system.l2c.occ_blocks::1 238.395777 # Average occupied blocks per context +system.l2c.occ_blocks::2 22874.505342 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183166 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.003638 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.349037 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1719678 # number of ReadReq hits +system.l2c.ReadReq_hits::1 147350 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1867028 # number of ReadReq hits +system.l2c.Writeback_hits::0 826540 # number of Writeback hits +system.l2c.Writeback_hits::total 826540 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 168225 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 11091 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179316 # number of ReadExReq hits +system.l2c.demand_hits::0 1887903 # number of demand (read+write) hits +system.l2c.demand_hits::1 158441 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2048127 # number of demand (read+write) hits -system.l2c.overall_hits::0 1891057 # number of overall hits -system.l2c.overall_hits::1 157070 # number of overall hits +system.l2c.demand_hits::total 2046344 # number of demand (read+write) hits +system.l2c.overall_hits::0 1887903 # number of overall hits +system.l2c.overall_hits::1 158441 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2048127 # number of overall hits -system.l2c.ReadReq_misses::0 305325 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4048 # number of ReadReq misses -system.l2c.ReadReq_misses::total 309373 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2451 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3007 # number of UpgradeReq misses +system.l2c.overall_hits::total 2046344 # number of overall hits +system.l2c.ReadReq_misses::0 305537 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4057 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309594 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 560 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3013 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::0 48 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 82 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 130 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 113992 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::1 84 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 132 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 113925 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 10735 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124727 # number of ReadExReq misses -system.l2c.demand_misses::0 419317 # number of demand (read+write) misses -system.l2c.demand_misses::1 14783 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::total 124660 # number of ReadExReq misses +system.l2c.demand_misses::0 419462 # number of demand (read+write) misses +system.l2c.demand_misses::1 14792 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434100 # number of demand (read+write) misses -system.l2c.overall_misses::0 419317 # number of overall misses -system.l2c.overall_misses::1 14783 # number of overall misses +system.l2c.demand_misses::total 434254 # number of demand (read+write) misses +system.l2c.overall_misses::0 419462 # number of overall misses +system.l2c.overall_misses::1 14792 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434100 # number of overall misses -system.l2c.ReadReq_miss_latency 16104881500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 3975000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 681000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6543645500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22648527000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22648527000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2028031 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 150107 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2178138 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 827102 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 827102 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2630 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 603 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3233 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 74 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 183 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 282343 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 21746 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304089 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2310374 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 171853 # number of demand (read+write) accesses +system.l2c.overall_misses::total 434254 # number of overall misses +system.l2c.ReadReq_miss_latency 16116451000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 3978500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 680500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6538718500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22655169500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22655169500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2025215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 151407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2176622 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 826540 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 826540 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3231 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 76 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 282150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21826 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 303976 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2307365 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 173233 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2482227 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2310374 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 171853 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2480598 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2307365 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 173233 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2482227 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.026967 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.931939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.922056 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.648649 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.752294 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.403736 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.493654 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.181493 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086021 # miss rate for demand accesses +system.l2c.overall_accesses::total 2480598 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.150866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.026795 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.924092 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.631579 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.750000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.403775 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.491845 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.181793 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.085388 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.181493 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086021 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.181793 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.085388 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52746.684680 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3978478.631423 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52747.951967 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3972504.560020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1621.787026 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 7149.280576 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 1621.891561 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 7104.464286 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 14187.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 8304.878049 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 14177.083333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 8101.190476 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 57404.427504 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 609561.760596 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57394.939653 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 609102.794597 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 54012.899549 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1532065.683555 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 54010.064082 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1531582.578421 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 54012.899549 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1532065.683555 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 54010.064082 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1531582.578421 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -138,100 +138,100 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 122219 # number of writebacks -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 309356 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3007 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 130 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 124727 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 434083 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 434083 # number of overall MSHR misses +system.l2c.writebacks 122051 # number of writebacks +system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 18 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 309576 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3013 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 132 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124660 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434236 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434236 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12384389500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 120345500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 5200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5026892500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17411282000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17411282000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 838237000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1420706998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2258943998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.152540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.060903 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12393243000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 120589000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 5280000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5022395000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17415638000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17415638000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838122500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1421433998 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2259556498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.152861 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.044661 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.143346 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.986733 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.147810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.971947 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.756757 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.192661 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.736842 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.178571 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.441757 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 5.735630 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.441822 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 5.711537 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.187884 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 2.525897 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.188196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 2.506659 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.187884 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 2.525897 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.188196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 2.506659 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40032.808480 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.782507 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40032.957981 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.900763 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40303.162106 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40110.490390 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40288.745387 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40106.389152 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41699 # number of replacements -system.iocache.tagsinuse 0.463134 # Cycle average of tags in use +system.iocache.replacements 41697 # number of replacements +system.iocache.tagsinuse 0.463240 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1709323096000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.463134 # Average occupied blocks per context -system.iocache.occ_percent::1 0.028946 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1709322874000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.463240 # Average occupied blocks per context +system.iocache.occ_percent::1 0.028953 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.ReadReq_misses::1 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.demand_misses::1 41729 # number of demand (read+write) misses +system.iocache.demand_misses::total 41729 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency 20616998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5721081806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5741698804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5741698804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.overall_misses::1 41729 # number of overall misses +system.iocache.overall_misses::total 41729 # number of overall misses +system.iocache.ReadReq_miss_latency 20390998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5721236806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741627804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741627804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41729 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41729 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -241,37 +241,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115178.759777 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115203.378531 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137684.872112 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137688.602378 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137588.334907 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137593.227827 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137588.334907 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137593.227827 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64637068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64620068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6180.633773 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.008223 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks 41520 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses +system.iocache.demand_mshr_misses 41729 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41729 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11308998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560223994 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571532992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571532992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 11186998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560378000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571564998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571564998 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -285,10 +285,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63178.759777 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85681.170437 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85584.649110 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63203.378531 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85684.876781 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85589.518033 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -309,22 +309,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9537119 # DTB read hits -system.cpu0.dtb.read_misses 35694 # DTB read misses -system.cpu0.dtb.read_acv 589 # DTB read access violations -system.cpu0.dtb.read_accesses 644456 # DTB read accesses -system.cpu0.dtb.write_hits 6201700 # DTB write hits -system.cpu0.dtb.write_misses 7404 # DTB write misses -system.cpu0.dtb.write_acv 340 # DTB write access violations -system.cpu0.dtb.write_accesses 219479 # DTB write accesses -system.cpu0.dtb.data_hits 15738819 # DTB hits -system.cpu0.dtb.data_misses 43098 # DTB misses -system.cpu0.dtb.data_acv 929 # DTB access violations -system.cpu0.dtb.data_accesses 863935 # DTB accesses -system.cpu0.itb.fetch_hits 1065001 # ITB hits -system.cpu0.itb.fetch_misses 28395 # ITB misses -system.cpu0.itb.fetch_acv 959 # ITB acv -system.cpu0.itb.fetch_accesses 1093396 # ITB accesses +system.cpu0.dtb.read_hits 9507417 # DTB read hits +system.cpu0.dtb.read_misses 35968 # DTB read misses +system.cpu0.dtb.read_acv 598 # DTB read access violations +system.cpu0.dtb.read_accesses 640032 # DTB read accesses +system.cpu0.dtb.write_hits 6191307 # DTB write hits +system.cpu0.dtb.write_misses 8160 # DTB write misses +system.cpu0.dtb.write_acv 353 # DTB write access violations +system.cpu0.dtb.write_accesses 218604 # DTB write accesses +system.cpu0.dtb.data_hits 15698724 # DTB hits +system.cpu0.dtb.data_misses 44128 # DTB misses +system.cpu0.dtb.data_acv 951 # DTB access violations +system.cpu0.dtb.data_accesses 858636 # DTB accesses +system.cpu0.itb.fetch_hits 1059111 # ITB hits +system.cpu0.itb.fetch_misses 28345 # ITB misses +system.cpu0.itb.fetch_acv 951 # ITB acv +system.cpu0.itb.fetch_accesses 1087456 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -337,147 +337,147 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112251413 # number of cpu cycles simulated +system.cpu0.numCycles 112078637 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 13715156 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 11502951 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 484161 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 12377728 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 6363664 # Number of BTB hits +system.cpu0.BPredUnit.lookups 13676513 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 11471993 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 481224 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 12342117 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 6355141 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 918279 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 37972 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 28099564 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69844028 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13715156 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 7281943 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 13538078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2172072 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 34812736 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 193219 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 330912 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 98 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8567969 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 303515 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 78411579 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.890736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.207630 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 915334 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 37832 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 28007609 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69419364 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13676513 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 7270475 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 13464854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2130456 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34838342 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 29311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 192876 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 330870 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 82 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8508842 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 295697 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 78241728 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.887242 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.203788 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64873501 82.73% 82.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 956509 1.22% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1906420 2.43% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 900643 1.15% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2836490 3.62% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 653196 0.83% 91.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 748865 0.96% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1020020 1.30% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4515935 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64776874 82.79% 82.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 958993 1.23% 84.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1895458 2.42% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 896557 1.15% 87.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2826529 3.61% 91.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 644193 0.82% 92.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 736181 0.94% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019927 1.30% 94.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4487016 5.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78411579 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.122182 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.622211 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 29218734 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 34518564 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12397503 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 907653 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1369124 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 565623 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 38130 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68326357 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115471 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1369124 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 30359966 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12420002 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18653448 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11559609 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4049428 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64489639 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6675 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 459269 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1452522 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 43185187 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 78281955 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77849999 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 431956 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36504578 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6680601 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1578071 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 238750 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11394232 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10044360 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6546770 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1193752 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 777018 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56531127 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2009866 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55005856 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 111558 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7605242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3895552 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1371310 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78411579 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.701502 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.348295 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 78241728 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.122026 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619381 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 29114965 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34547748 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12317154 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 921824 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1340036 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 563514 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 37992 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 67952438 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 114909 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1340036 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 30246504 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12447336 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18631420 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11494424 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4082006 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64196257 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6719 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 464674 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1470831 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 42946380 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 77900777 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77469173 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 431604 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36477108 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6469264 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1576496 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 238440 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11483101 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10008373 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6527102 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1185571 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 771360 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56320474 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2007436 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 54875963 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 110266 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7429207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3754226 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1369428 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 78241728 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.701364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.347589 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54224531 69.15% 69.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10651966 13.58% 82.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 5211873 6.65% 89.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3322855 4.24% 93.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2518388 3.21% 96.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1465679 1.87% 98.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 653633 0.83% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 263398 0.34% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 99256 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54100520 69.15% 69.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10639232 13.60% 82.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 5191485 6.64% 89.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3321136 4.24% 93.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2520069 3.22% 96.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1468713 1.88% 98.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 637402 0.81% 99.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263268 0.34% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 99903 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78411579 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 78241728 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 63058 8.97% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 343865 48.92% 57.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 295935 42.10% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61581 8.74% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 342929 48.66% 57.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 300261 42.60% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37799296 68.72% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60344 0.11% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.86% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.86% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3329 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37711302 68.72% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60327 0.11% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15682 0.03% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 1654 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.87% # Type of FU issued @@ -500,112 +500,112 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.87% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.87% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9967542 18.12% 86.99% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6280275 11.42% 98.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 877731 1.60% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9937545 18.11% 86.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6268980 11.42% 98.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 877144 1.60% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55005856 # Type of FU issued -system.cpu0.iq.rate 0.490024 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 702858 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.012778 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 188615716 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65871549 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53572345 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 621990 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 297473 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 294666 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55378554 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 326832 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 547956 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 54875963 # Type of FU issued +system.cpu0.iq.rate 0.489620 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 704772 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.012843 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 188187092 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65472775 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53463452 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 621599 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 297101 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 294471 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55250754 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326652 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 544032 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1439562 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 14656 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 23453 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 541104 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1411765 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 14119 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13054 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 526523 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 167543 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 19033 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 166880 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1369124 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8683441 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 605421 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 62052001 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 831027 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10044360 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6546770 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1774362 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 483184 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10442 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 23453 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 350905 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 357470 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 708375 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54360123 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9599991 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 645732 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1340036 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8692237 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 606269 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 61830785 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 830784 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10008373 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6527102 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1772467 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 482817 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10549 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13054 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 346528 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358003 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 704531 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54241616 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9570533 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 634346 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3511008 # number of nop insts executed -system.cpu0.iew.exec_refs 15823517 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8665836 # Number of branches executed -system.cpu0.iew.exec_stores 6223526 # Number of stores executed -system.cpu0.iew.exec_rate 0.484271 # Inst execution rate -system.cpu0.iew.wb_sent 53987864 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 53867011 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26614200 # num instructions producing a value -system.cpu0.iew.wb_consumers 35806994 # num instructions consuming a value +system.cpu0.iew.exec_nop 3502875 # number of nop insts executed +system.cpu0.iew.exec_refs 15784325 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8657029 # Number of branches executed +system.cpu0.iew.exec_stores 6213792 # Number of stores executed +system.cpu0.iew.exec_rate 0.483960 # Inst execution rate +system.cpu0.iew.wb_sent 53872827 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 53757923 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26542591 # num instructions producing a value +system.cpu0.iew.wb_consumers 35724968 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.479878 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.743268 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.479645 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742970 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 53695815 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 8260876 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638556 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 645745 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77042455 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.696964 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608185 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 53656716 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 8078010 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638008 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 642783 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76901692 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.697731 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.609209 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 56792844 73.72% 73.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8505609 11.04% 84.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4528626 5.88% 90.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2490278 3.23% 93.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1477167 1.92% 95.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 617055 0.80% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444256 0.58% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 490319 0.64% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1696301 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56673915 73.70% 73.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8488315 11.04% 84.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4528829 5.89% 90.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2497024 3.25% 93.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1465718 1.91% 95.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 614414 0.80% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 447034 0.58% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 489019 0.64% 97.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1697424 2.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77042455 # Number of insts commited each cycle -system.cpu0.commit.count 53695815 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 76901692 # Number of insts commited each cycle +system.cpu0.commit.count 53656716 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14610464 # Number of memory references committed -system.cpu0.commit.loads 8604798 # Number of loads committed -system.cpu0.commit.membars 217772 # Number of memory barriers committed -system.cpu0.commit.branches 8097271 # Number of branches committed -system.cpu0.commit.fp_insts 292136 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49674100 # Number of committed integer instructions. -system.cpu0.commit.function_calls 705369 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1696301 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14597187 # Number of memory references committed +system.cpu0.commit.loads 8596608 # Number of loads committed +system.cpu0.commit.membars 217615 # Number of memory barriers committed +system.cpu0.commit.branches 8092300 # Number of branches committed +system.cpu0.commit.fp_insts 291990 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 49637924 # Number of committed integer instructions. +system.cpu0.commit.function_calls 704482 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1697424 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 137112360 # The number of ROB reads -system.cpu0.rob.rob_writes 125284104 # The number of ROB writes -system.cpu0.timesIdled 1232970 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 33839834 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 50579161 # Number of Instructions Simulated -system.cpu0.committedInsts_total 50579161 # Number of Instructions Simulated -system.cpu0.cpi 2.219321 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.219321 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.450588 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.450588 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71273377 # number of integer regfile reads -system.cpu0.int_regfile_writes 38974201 # number of integer regfile writes -system.cpu0.fp_regfile_reads 144005 # number of floating regfile reads -system.cpu0.fp_regfile_writes 146400 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1864820 # number of misc regfile reads -system.cpu0.misc_regfile_writes 888952 # number of misc regfile writes +system.cpu0.rob.rob_reads 136748495 # The number of ROB reads +system.cpu0.rob.rob_writes 124811050 # The number of ROB writes +system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 50542242 # Number of Instructions Simulated +system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated +system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.217524 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.450953 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.450953 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71124780 # number of integer regfile reads +system.cpu0.int_regfile_writes 38876207 # number of integer regfile writes +system.cpu0.fp_regfile_reads 143910 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146325 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1863327 # number of misc regfile reads +system.cpu0.misc_regfile_writes 888204 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -637,233 +637,233 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 972255 # number of replacements -system.cpu0.icache.tagsinuse 509.997473 # Cycle average of tags in use -system.cpu0.icache.total_refs 7540990 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 972767 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.752103 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23351428000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 509.997473 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.996089 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 7540990 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7540990 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 7540990 # number of demand (read+write) hits +system.cpu0.icache.replacements 970482 # number of replacements +system.cpu0.icache.tagsinuse 510.008508 # Cycle average of tags in use +system.cpu0.icache.total_refs 7483994 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 970994 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.707559 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23358720000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 510.008508 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996110 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 7483994 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7483994 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 7483994 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7540990 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 7540990 # number of overall hits +system.cpu0.icache.demand_hits::total 7483994 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 7483994 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 7540990 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 1026979 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1026979 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 1026979 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 7483994 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 1024848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1024848 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 1024848 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1026979 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 1026979 # number of overall misses +system.cpu0.icache.demand_misses::total 1024848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 1024848 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 1026979 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 15345865496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 15345865496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 15345865496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 8567969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8567969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 8567969 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 1024848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 15319794498 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 15319794498 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 15319794498 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 8508842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8508842 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 8508842 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8567969 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 8567969 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 8508842 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 8508842 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8567969 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.119863 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.119863 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 8508842 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.120445 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.120445 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.119863 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.120445 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14942.725699 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14948.357706 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14942.725699 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14948.357706 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14942.725699 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14948.357706 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1169997 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1225998 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 103 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11584.128713 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11902.893204 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 201 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 54044 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 54044 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 54044 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 972935 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 972935 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 972935 # number of overall MSHR misses +system.cpu0.icache.writebacks 218 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 53716 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 53716 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 53716 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 971132 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 971132 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 971132 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 11633224497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 11633224497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 11633224497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 11617050998 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 11617050998 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 11617050998 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113555 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.114132 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.113555 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.114132 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.113555 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.114132 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11956.836271 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11956.836271 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11962.381013 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11962.381013 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1341445 # number of replacements -system.cpu0.dcache.tagsinuse 503.508011 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11371142 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1341956 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.473558 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1339905 # number of replacements +system.cpu0.dcache.tagsinuse 503.729057 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11343106 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1340416 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.462377 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.508011 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 504.729057 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.985367 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::0 0.985799 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7002154 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7002154 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 3971242 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3971242 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 182799 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 182799 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 208802 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208802 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 10973396 # number of demand (read+write) hits +system.cpu0.dcache.ReadReq_hits::0 6978274 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6978274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 3967577 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3967577 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 182488 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 182488 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 208558 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208558 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 10945851 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10973396 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 10973396 # number of overall hits +system.cpu0.dcache.demand_hits::total 10945851 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 10945851 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10973396 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1698188 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1698188 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1810110 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1810110 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 21696 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21696 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 665 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 665 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 3508298 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 10945851 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1696520 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1696520 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1808915 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1808915 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 21731 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21731 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 693 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 693 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 3505435 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3508298 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 3508298 # number of overall misses +system.cpu0.dcache.demand_misses::total 3505435 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 3505435 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 3508298 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 37024597500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 55205693695 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 326548500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 6352500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 92230291195 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 92230291195 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8700342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8700342 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5781352 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5781352 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 204495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 209467 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 209467 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14481694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 3505435 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 37036233000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 55166183811 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 327139500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 6516000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 92202416811 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 92202416811 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8674794 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8674794 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 5776492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5776492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 204219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 204219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 209251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 209251 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14451286 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14481694 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14481694 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14451286 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14451286 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14481694 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.195186 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.313095 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106096 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003175 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.242257 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14451286 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.195569 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.313151 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003312 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.242569 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.242257 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.242569 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 21802.413808 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 21830.708156 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 30498.529755 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 30496.835844 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15051.092367 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15054.047214 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9552.631579 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9402.597403 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26289.183871 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 26302.703320 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26289.183871 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 26302.703320 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 889959290 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 192000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 98831 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9004.859710 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 886352311 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 210500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 100011 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8862.548230 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23388.888889 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 791115 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 651520 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1525368 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 4914 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 2176888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 2176888 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1046668 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 284742 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16782 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 665 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1331410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1331410 # number of overall MSHR misses +system.cpu0.dcache.writebacks 790429 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 651194 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1524352 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 4898 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 2175546 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 2175546 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 1045326 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 284563 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 16833 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 693 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 1329889 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 1329889 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 24224955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8301968289 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194959000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4349000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 32526923289 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 32526923289 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 917419500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1254211998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2171631498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120302 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 24217800500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 8294565311 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 195726500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 4430000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 32512365811 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 32512365811 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 916795000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1253240498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 2170035498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.120502 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049252 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049262 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.082426 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003175 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.003312 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091937 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.092026 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091937 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.092026 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23144.831981 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29156.107244 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11617.149327 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6539.849624 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 24430.433367 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23167.701272 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29148.432196 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11627.547080 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6392.496392 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 24447.428177 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -874,22 +874,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1324275 # DTB read hits -system.cpu1.dtb.read_misses 10298 # DTB read misses +system.cpu1.dtb.read_hits 1326048 # DTB read hits +system.cpu1.dtb.read_misses 10245 # DTB read misses system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 333543 # DTB read accesses -system.cpu1.dtb.write_hits 770562 # DTB write hits -system.cpu1.dtb.write_misses 3363 # DTB write misses -system.cpu1.dtb.write_acv 49 # DTB write access violations -system.cpu1.dtb.write_accesses 128416 # DTB write accesses -system.cpu1.dtb.data_hits 2094837 # DTB hits -system.cpu1.dtb.data_misses 13661 # DTB misses -system.cpu1.dtb.data_acv 53 # DTB access violations -system.cpu1.dtb.data_accesses 461959 # DTB accesses -system.cpu1.itb.fetch_hits 370005 # ITB hits -system.cpu1.itb.fetch_misses 7545 # ITB misses -system.cpu1.itb.fetch_acv 134 # ITB acv -system.cpu1.itb.fetch_accesses 377550 # ITB accesses +system.cpu1.dtb.read_accesses 331667 # DTB read accesses +system.cpu1.dtb.write_hits 775032 # DTB write hits +system.cpu1.dtb.write_misses 3356 # DTB write misses +system.cpu1.dtb.write_acv 50 # DTB write access violations +system.cpu1.dtb.write_accesses 128144 # DTB write accesses +system.cpu1.dtb.data_hits 2101080 # DTB hits +system.cpu1.dtb.data_misses 13601 # DTB misses +system.cpu1.dtb.data_acv 54 # DTB access violations +system.cpu1.dtb.data_accesses 459811 # DTB accesses +system.cpu1.itb.fetch_hits 367550 # ITB hits +system.cpu1.itb.fetch_misses 7752 # ITB misses +system.cpu1.itb.fetch_acv 129 # ITB acv +system.cpu1.itb.fetch_accesses 375302 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -902,500 +902,500 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 9912659 # number of cpu cycles simulated +system.cpu1.numCycles 9966962 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 1745252 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 1443345 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 65834 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1584413 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 702878 # Number of BTB hits +system.cpu1.BPredUnit.lookups 1746608 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 1443175 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 66232 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1579747 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 700902 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 119333 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 5152 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 3326193 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 8368967 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1745252 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 822211 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1597560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 342353 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3930227 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65364 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 47873 # Number of stall cycles due to pending quiesce instructions +system.cpu1.BPredUnit.usedRAS 120007 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 5197 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 3352188 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 8389538 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1746608 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 820909 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1600088 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 340649 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3953742 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24318 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65300 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48169 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1048710 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 37506 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 9217508 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.907942 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.250031 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1052111 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 37387 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 9268453 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.905171 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.248228 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 7619948 82.67% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 115536 1.25% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 231432 2.51% 86.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 132066 1.43% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 251396 2.73% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 87805 0.95% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 105965 1.15% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 72910 0.79% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 600450 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 7668365 82.74% 82.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 115994 1.25% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 231226 2.49% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 132329 1.43% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 251751 2.72% 90.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 85931 0.93% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 105894 1.14% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 73622 0.79% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 603341 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 9217508 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.176063 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.844271 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3400940 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 4036286 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1484850 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 73785 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 221646 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 74292 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4556 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8102747 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 13778 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 221646 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3537754 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 421646 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3194279 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1408453 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 433728 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 7527296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45933 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 92379 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 5035349 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9221754 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9169185 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52569 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3992895 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1042454 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 304748 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 22314 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1288706 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1415531 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 837109 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 144169 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 91214 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 6583258 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 323533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6259296 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22632 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1284449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 724409 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 248666 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 9217508 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.679066 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.329101 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 9268453 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.175240 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.841735 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 3426888 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 4059985 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1487039 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 74425 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 220115 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 74752 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 4586 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 8123817 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 13801 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 220115 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 3563676 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 426586 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3211249 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1411283 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 435542 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 7548530 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 46052 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 92764 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 5048861 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 9245845 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 9192898 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52947 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 4017246 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1031615 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 305905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 22528 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1292369 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1416426 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 841512 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 141179 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 90021 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 6602199 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 325316 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 6284355 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22621 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1273450 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 716539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 249793 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 9268453 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.678037 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.328780 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 6458729 70.07% 70.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1222372 13.26% 83.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 577704 6.27% 89.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 392327 4.26% 93.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 292985 3.18% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 159359 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 73107 0.79% 99.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 30242 0.33% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10683 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 6498051 70.11% 70.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1227525 13.24% 83.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 582679 6.29% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 391581 4.22% 93.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 294983 3.18% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 158395 1.71% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 72456 0.78% 99.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 32178 0.35% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10605 0.11% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 9217508 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 9268453 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2814 1.95% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 81545 56.44% 58.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 60126 41.61% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2859 1.97% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 82047 56.45% 58.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 60446 41.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3976 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3873185 61.88% 61.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10062 0.16% 62.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10067 0.16% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1379075 22.03% 84.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 790293 12.63% 96.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 190650 3.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3978 0.06% 0.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3890788 61.91% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 10226 0.16% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10071 0.16% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1988 0.03% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1381194 21.98% 84.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 794695 12.65% 96.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 191415 3.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6259296 # Type of FU issued -system.cpu1.iq.rate 0.631445 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 144485 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023083 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 21824812 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 8155075 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6057514 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 78405 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 38858 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 37639 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6359227 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 40578 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 60856 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 6284355 # Type of FU issued +system.cpu1.iq.rate 0.630519 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 145352 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023129 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 21926150 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 8163461 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 6082297 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 78986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 39141 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 37853 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 6384800 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 40929 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 61528 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 266775 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6711 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3171 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 114531 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 262809 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1750 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 113415 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 348 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 21986 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 366 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 22210 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 221646 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 305727 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 11882 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7168806 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98535 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1415531 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 837109 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301857 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4025 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4971 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3171 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 47886 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 59778 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 107664 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6180810 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1338159 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 78486 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 220115 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 309272 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12037 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 7192077 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99271 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1416426 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 841512 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 303434 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3996 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4977 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1750 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 48213 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60062 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 108275 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 6205529 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1339876 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 78826 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 262015 # number of nop insts executed -system.cpu1.iew.exec_refs 2115427 # number of memory reference insts executed -system.cpu1.iew.exec_branches 905329 # Number of branches executed -system.cpu1.iew.exec_stores 777268 # Number of stores executed -system.cpu1.iew.exec_rate 0.623527 # Inst execution rate -system.cpu1.iew.wb_sent 6122723 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6095153 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2947422 # num instructions producing a value -system.cpu1.iew.wb_consumers 4027218 # num instructions consuming a value +system.cpu1.iew.exec_nop 264562 # number of nop insts executed +system.cpu1.iew.exec_refs 2121617 # number of memory reference insts executed +system.cpu1.iew.exec_branches 906286 # Number of branches executed +system.cpu1.iew.exec_stores 781741 # Number of stores executed +system.cpu1.iew.exec_rate 0.622610 # Inst execution rate +system.cpu1.iew.wb_sent 6147670 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 6120150 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2958458 # num instructions producing a value +system.cpu1.iew.wb_consumers 4045224 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614886 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.731875 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614044 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.731346 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 5779093 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 1316908 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 74867 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 99712 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 8995862 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.642417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.546372 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 5812223 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 1307029 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 75523 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 100285 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 9048338 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642353 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.547343 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6736606 74.89% 74.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1094915 12.17% 87.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 391523 4.35% 91.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 242834 2.70% 94.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 155077 1.72% 95.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 75617 0.84% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76298 0.85% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 67487 0.75% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 155505 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6777327 74.90% 74.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1099919 12.16% 87.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 394591 4.36% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 244546 2.70% 94.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 155405 1.72% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 74689 0.83% 96.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 76341 0.84% 97.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 67787 0.75% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 157733 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 8995862 # Number of insts commited each cycle -system.cpu1.commit.count 5779093 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 9048338 # Number of insts commited each cycle +system.cpu1.commit.count 5812223 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1871334 # Number of memory references committed -system.cpu1.commit.loads 1148756 # Number of loads committed -system.cpu1.commit.membars 20308 # Number of memory barriers committed -system.cpu1.commit.branches 819762 # Number of branches committed -system.cpu1.commit.fp_insts 36255 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5407958 # Number of committed integer instructions. -system.cpu1.commit.function_calls 88494 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 155505 # number cycles where commit BW limit reached +system.cpu1.commit.refs 1881714 # Number of memory references committed +system.cpu1.commit.loads 1153617 # Number of loads committed +system.cpu1.commit.membars 20508 # Number of memory barriers committed +system.cpu1.commit.branches 821256 # Number of branches committed +system.cpu1.commit.fp_insts 36401 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 5437919 # Number of committed integer instructions. +system.cpu1.commit.function_calls 89388 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 157733 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 15845699 # The number of ROB reads -system.cpu1.rob.rob_writes 14412433 # The number of ROB writes -system.cpu1.timesIdled 81222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 695151 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 5557862 # Number of Instructions Simulated -system.cpu1.committedInsts_total 5557862 # Number of Instructions Simulated -system.cpu1.cpi 1.783538 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.783538 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.560683 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.560683 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8056762 # number of integer regfile reads -system.cpu1.int_regfile_writes 4390923 # number of integer regfile writes -system.cpu1.fp_regfile_reads 24497 # number of floating regfile reads -system.cpu1.fp_regfile_writes 23023 # number of floating regfile writes -system.cpu1.misc_regfile_reads 283037 # number of misc regfile reads -system.cpu1.misc_regfile_writes 133939 # number of misc regfile writes -system.cpu1.icache.replacements 109497 # number of replacements -system.cpu1.icache.tagsinuse 452.896457 # Cycle average of tags in use -system.cpu1.icache.total_refs 933398 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 110009 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 8.484742 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1874842259000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 452.896457 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.884563 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 933398 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 933398 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 933398 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 15919184 # The number of ROB reads +system.cpu1.rob.rob_writes 14457399 # The number of ROB writes +system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 5588724 # Number of Instructions Simulated +system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated +system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.783406 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.560725 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.560725 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 8091693 # number of integer regfile reads +system.cpu1.int_regfile_writes 4410635 # number of integer regfile writes +system.cpu1.fp_regfile_reads 24636 # number of floating regfile reads +system.cpu1.fp_regfile_writes 23087 # number of floating regfile writes +system.cpu1.misc_regfile_reads 284786 # number of misc regfile reads +system.cpu1.misc_regfile_writes 134830 # number of misc regfile writes +system.cpu1.icache.replacements 110610 # number of replacements +system.cpu1.icache.tagsinuse 452.934793 # Cycle average of tags in use +system.cpu1.icache.total_refs 935676 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 111121 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.420335 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1874818206000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 452.934793 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.884638 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 935676 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 935676 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 935676 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 933398 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 933398 # number of overall hits +system.cpu1.icache.demand_hits::total 935676 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 935676 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 933398 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 115312 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 115312 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 115312 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 935676 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 116435 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 116435 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 116435 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 115312 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 115312 # number of overall misses +system.cpu1.icache.demand_misses::total 116435 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 116435 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 115312 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1734763499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1734763499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1734763499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 1048710 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1048710 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 1048710 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 116435 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 1751730499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 1751730499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 1751730499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 1052111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1052111 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 1052111 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1048710 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 1048710 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 1052111 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 1052111 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1048710 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.109956 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.109956 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 1052111 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.110668 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.110668 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.109956 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.110668 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.084735 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 15044.707339 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 15044.084735 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 15044.707339 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 15044.084735 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 15044.707339 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 115999 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 93999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6444.388889 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7230.692308 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 32 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 5233 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 5233 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 5233 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 110079 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 110079 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 110079 # number of overall MSHR misses +system.cpu1.icache.writebacks 37 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 5243 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 5243 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 5243 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 111192 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 111192 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 111192 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 1320813499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 1320813499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 1320813499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 1333669999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 1333669999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 1333669999 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.104966 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.105685 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.104966 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.105685 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.104966 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.105685 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11998.778141 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11998.778141 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11994.298142 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11994.298142 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62178 # number of replacements -system.cpu1.dcache.tagsinuse 392.683341 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1692677 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62506 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 27.080232 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1874637412500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 392.683341 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.766960 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1125457 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1125457 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 544800 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 544800 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 16569 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 16569 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 14697 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 14697 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1670257 # number of demand (read+write) hits +system.cpu1.dcache.replacements 62429 # number of replacements +system.cpu1.dcache.tagsinuse 392.995073 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1698421 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62755 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 27.064314 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1874613639500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 392.995073 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.767569 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 1125916 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1125916 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 549554 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 549554 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 16796 # 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number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1934149 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 264505 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 1790096000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 5171682833 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 19414000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 8395500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 6961778833 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 6961778833 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 1232610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1232610 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 707365 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 707365 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 18276 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 18276 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 15623 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 15623 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 1939975 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1934149 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1934149 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1939975 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 1939975 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1934149 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.086517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.224041 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081541 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044719 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.136438 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 1939975 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.086559 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.223097 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.080981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044806 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.136345 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.136438 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.136345 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 16690.725470 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 16777.850676 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 32806.910800 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 32771.371026 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13181.509177 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13117.567568 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11962.936047 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 11993.571429 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 26297.154753 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 26320.027345 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 26297.154753 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 26320.027345 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 86924497 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 86579997 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6880 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6823 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12634.374564 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12689.432361 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 35754 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 63001 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 133631 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 299 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 196632 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 196632 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 43592 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 23668 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 1172 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 688 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 67260 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 67260 # number of overall MSHR misses +system.cpu1.dcache.writebacks 35856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 62883 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 134026 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 196909 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 196909 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 43811 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 23785 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 1185 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 699 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 67596 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 67596 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 554109500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 750522486 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11597500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6158000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 1304631986 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 1304631986 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 18620500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 319072500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 337693000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035382 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 556154000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 752491985 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6289000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 1308645985 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 1308645985 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19117500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320801000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 339918500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035543 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033710 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033625 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064967 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064839 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044719 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044742 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034775 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.034844 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034775 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.034844 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12711.265829 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31710.431215 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9895.477816 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8950.581395 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19396.847844 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.391819 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31637.249737 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9819.831224 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 8997.138770 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19359.813968 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1403,31 +1403,31 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 199477 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71613 40.63% 40.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 237 0.13% 40.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1921 1.09% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 102492 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 176271 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 70248 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6372 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 199307 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71537 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.13% 40.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.09% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 102421 58.15% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 176125 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 70172 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 237 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1921 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 70240 49.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 142654 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1858831999000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90898500 0.00% 97.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 391654500 0.02% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4204500 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 38151374000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897470130500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980939 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 70164 49.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 142503 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1858853057000 97.97% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90805500 0.00% 97.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 391568500 0.02% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4023000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 38125490000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897464944000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980919 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685055 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.72% 3.72% # number of syscalls executed system.cpu0.kern.syscall::3 18 8.37% 12.09% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.40% 13.49% # number of syscalls executed @@ -1459,59 +1459,59 @@ system.cpu0.kern.syscall::144 2 0.93% 99.07% # nu system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 105 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3842 2.08% 2.14% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3840 2.08% 2.14% # number of callpals executed system.cpu0.kern.callpal::tbi 50 0.03% 2.16% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal::swpipl 169337 91.54% 93.71% # number of callpals executed -system.cpu0.kern.callpal::rdps 6360 3.44% 97.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 169189 91.54% 93.71% # number of callpals executed +system.cpu0.kern.callpal::rdps 6337 3.43% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::wrusp 2 0.00% 97.14% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.15% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rti 4767 2.58% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4768 2.58% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 135 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 184989 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7265 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1246 # number of protection mode switches +system.cpu0.kern.callpal::total 184818 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7264 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1248 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1245 -system.cpu0.kern.mode_good::user 1246 +system.cpu0.kern.mode_good::kernel 1247 +system.cpu0.kern.mode_good::user 1248 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.171370 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.171669 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895606727500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1863395000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1895604498000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1860438000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3843 # number of times the context was actually changed +system.cpu0.kern.swap_context 3841 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2270 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 38355 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10172 33.29% 33.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 6.28% 39.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.34% 39.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18361 60.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30557 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10160 45.68% 45.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 8.63% 54.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.47% 54.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10056 45.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22240 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871109076500 98.61% 98.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 343280000 0.02% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 41782500 0.00% 98.63% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 25970941500 1.37% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897465080500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998820 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2274 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 38564 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10256 33.36% 33.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 6.25% 39.61% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.34% 39.95% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18460 60.05% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30741 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10244 45.72% 45.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 8.57% 54.28% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.47% 54.75% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10139 45.25% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22408 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871092276500 98.61% 98.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 343292500 0.02% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42130500 0.00% 98.63% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 25986985000 1.37% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897464684500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998830 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.547683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.549242 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 12 10.81% 10.81% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.90% 11.71% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.01% 20.72% # number of syscalls executed @@ -1531,32 +1531,32 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.03% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 391 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::swpctx 393 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.28% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.31% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26005 82.46% 83.77% # number of callpals executed -system.cpu1.kern.callpal::rdps 2390 7.58% 91.35% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.35% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.02% 91.37% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.38% # number of callpals executed -system.cpu1.kern.callpal::rti 2527 8.01% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.46% 99.85% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.30% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26187 82.50% 83.80% # number of callpals executed +system.cpu1.kern.callpal::rdps 2413 7.60% 91.40% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.02% 91.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2528 7.96% 99.40% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.46% 99.86% # number of callpals executed system.cpu1.kern.callpal::imb 45 0.14% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 31535 # number of callpals executed +system.cpu1.kern.callpal::total 31743 # number of callpals executed system.cpu1.kern.mode_switch::kernel 869 # number of protection mode switches system.cpu1.kern.mode_switch::user 492 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 521 +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 522 system.cpu1.kern.mode_good::user 492 -system.cpu1.kern.mode_good::idle 29 -system.cpu1.kern.mode_switch_good::kernel 0.599540 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 30 +system.cpu1.kern.mode_switch_good::kernel 0.600690 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.014139 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.613679 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2030212000 0.11% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 852485500 0.04% 0.15% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893908030500 99.85% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 392 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.014606 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.615296 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2061638000 0.11% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 848590000 0.04% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893876047000 99.85% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 394 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index a8911f6cc..2cd4054d5 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,13 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/arm/scratch/sysexplr/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -497,7 +497,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -517,7 +517,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -646,7 +646,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index b71599069..636c32218 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/ts gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 16:33:41 -gem5 started Aug 17 2011 16:35:09 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 15:21:47 +gem5 started Aug 20 2011 15:21:55 +gem5 executing on zizzer command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1857897393500 because m5_exit instruction encountered +Exiting @ tick 1858873594500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index c17b9a135..f8131be53 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.857897 # Number of seconds simulated -sim_ticks 1857897393500 # Number of ticks simulated +sim_seconds 1.858874 # Number of seconds simulated +sim_ticks 1858873594500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111366 # Simulator instruction rate (inst/s) -host_tick_rate 3896929552 # Simulator tick rate (ticks/s) -host_mem_usage 340840 # Number of bytes of host memory used -host_seconds 476.76 # Real time elapsed on the host -sim_insts 53094627 # Number of instructions simulated -system.l2c.replacements 391325 # number of replacements -system.l2c.tagsinuse 34942.141711 # Cycle average of tags in use -system.l2c.total_refs 2407783 # Total number of references to valid blocks. -system.l2c.sampled_refs 424213 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.675882 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5611809000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12320.874417 # Average occupied blocks per context -system.l2c.occ_blocks::1 22621.267294 # Average occupied blocks per context -system.l2c.occ_percent::0 0.188002 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.345173 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1800422 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1800422 # number of ReadReq hits -system.l2c.Writeback_hits::0 834998 # number of Writeback hits -system.l2c.Writeback_hits::total 834998 # number of Writeback hits +host_inst_rate 131543 # Simulator instruction rate (inst/s) +host_tick_rate 4605131786 # Simulator tick rate (ticks/s) +host_mem_usage 295252 # Number of bytes of host memory used +host_seconds 403.65 # Real time elapsed on the host +sim_insts 53097697 # Number of instructions simulated +system.l2c.replacements 391354 # number of replacements +system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use +system.l2c.total_refs 2410581 # Total number of references to valid blocks. +system.l2c.sampled_refs 424231 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.682237 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12293.296692 # Average occupied blocks per context +system.l2c.occ_blocks::1 22604.789448 # Average occupied blocks per context +system.l2c.occ_percent::0 0.187581 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.344922 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1801188 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1801188 # number of ReadReq hits +system.l2c.Writeback_hits::0 835090 # number of Writeback hits +system.l2c.Writeback_hits::total 835090 # number of Writeback hits system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 16 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 183185 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183185 # number of ReadExReq hits -system.l2c.demand_hits::0 1983607 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::0 183163 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183163 # number of ReadExReq hits +system.l2c.demand_hits::0 1984351 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1983607 # number of demand (read+write) hits -system.l2c.overall_hits::0 1983607 # number of overall hits +system.l2c.demand_hits::total 1984351 # number of demand (read+write) hits +system.l2c.overall_hits::0 1984351 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1983607 # number of overall hits -system.l2c.ReadReq_misses::0 308136 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308136 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 36 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 116850 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116850 # number of ReadExReq misses -system.l2c.demand_misses::0 424986 # number of demand (read+write) misses +system.l2c.overall_hits::total 1984351 # number of overall hits +system.l2c.ReadReq_misses::0 308072 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308072 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 33 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 33 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116926 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116926 # number of ReadExReq misses +system.l2c.demand_misses::0 424998 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424986 # number of demand (read+write) misses -system.l2c.overall_misses::0 424986 # number of overall misses +system.l2c.demand_misses::total 424998 # number of demand (read+write) misses +system.l2c.overall_misses::0 424998 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424986 # number of overall misses -system.l2c.ReadReq_miss_latency 16038372500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 424998 # number of overall misses +system.l2c.ReadReq_miss_latency 16035098000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 425000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6129219000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22167591500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22167591500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2108558 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108558 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 834998 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 834998 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 52 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency 6133668000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22168766000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22168766000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2109260 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109260 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835090 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835090 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 49 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 300035 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300035 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2408593 # number of demand (read+write) accesses +system.l2c.ReadExReq_accesses::0 300089 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300089 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2409349 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2408593 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2408593 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2409349 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2409349 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2408593 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.146136 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.692308 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.389455 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.176446 # miss rate for demand accesses +system.l2c.overall_accesses::total 2409349 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146057 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.673469 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389638 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176395 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.176446 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.176395 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52049.655022 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52049.838999 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 11805.555556 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 12878.787879 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52453.735558 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52457.691189 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52160.757060 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52162.047821 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52160.757060 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52162.047821 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -99,43 +99,43 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117715 # number of writebacks +system.l2c.writebacks 117760 # number of writebacks system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 308136 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 116850 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 424986 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 424986 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 308072 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116926 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 424998 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 424998 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12334391000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 1500000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4708487500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17042878500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17042878500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 810033000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1115131998 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1925164998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146136 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12331827500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1380000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4711722000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17043549500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17043549500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810479000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115452498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925931498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146057 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.692308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.673469 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.389455 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389638 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.176446 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.176395 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.176446 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.176395 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40029.048862 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 41666.666667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40295.143346 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40102.211602 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40029.043535 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41818.181818 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40296.614953 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40102.658130 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -143,13 +143,13 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.260372 # Cycle average of tags in use +system.iocache.tagsinuse 1.268274 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1708338825000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.260372 # Average occupied blocks per context -system.iocache.occ_percent::1 0.078773 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1708338694000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.268274 # Average occupied blocks per context +system.iocache.occ_percent::1 0.079267 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -166,10 +166,10 @@ system.iocache.demand_misses::total 41725 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722330806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742268804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742268804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5722643806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742583804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742583804 # number of overall miss cycles system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) @@ -189,22 +189,22 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137714.930834 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137722.463564 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137621.780803 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137629.330234 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137621.780803 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137629.330234 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64585068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64634068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10462 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10468 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6173.300325 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6174.442874 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -216,10 +216,10 @@ system.iocache.WriteReq_mshr_misses 41552 # nu system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561477996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572419994 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572419994 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561790996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572734994 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572734994 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -233,10 +233,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85711.349538 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85618.214356 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85718.882268 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85625.763787 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -257,22 +257,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10156439 # DTB read hits -system.cpu.dtb.read_misses 47122 # DTB read misses -system.cpu.dtb.read_acv 587 # DTB read access violations -system.cpu.dtb.read_accesses 977122 # DTB read accesses -system.cpu.dtb.write_hits 6633598 # DTB write hits -system.cpu.dtb.write_misses 11598 # DTB write misses -system.cpu.dtb.write_acv 414 # DTB write access violations -system.cpu.dtb.write_accesses 348122 # DTB write accesses -system.cpu.dtb.data_hits 16790037 # DTB hits -system.cpu.dtb.data_misses 58720 # DTB misses -system.cpu.dtb.data_acv 1001 # DTB access violations -system.cpu.dtb.data_accesses 1325244 # DTB accesses -system.cpu.itb.fetch_hits 1333506 # ITB hits -system.cpu.itb.fetch_misses 39875 # ITB misses -system.cpu.itb.fetch_acv 1125 # ITB acv -system.cpu.itb.fetch_accesses 1373381 # ITB accesses +system.cpu.dtb.read_hits 10138302 # DTB read hits +system.cpu.dtb.read_misses 46569 # DTB read misses +system.cpu.dtb.read_acv 588 # DTB read access violations +system.cpu.dtb.read_accesses 971478 # DTB read accesses +system.cpu.dtb.write_hits 6627002 # DTB write hits +system.cpu.dtb.write_misses 12216 # DTB write misses +system.cpu.dtb.write_acv 416 # DTB write access violations +system.cpu.dtb.write_accesses 347261 # DTB write accesses +system.cpu.dtb.data_hits 16765304 # DTB hits +system.cpu.dtb.data_misses 58785 # DTB misses +system.cpu.dtb.data_acv 1004 # DTB access violations +system.cpu.dtb.data_accesses 1318739 # DTB accesses +system.cpu.itb.fetch_hits 1327158 # ITB hits +system.cpu.itb.fetch_misses 39816 # ITB misses +system.cpu.itb.fetch_acv 1096 # ITB acv +system.cpu.itb.fetch_accesses 1366974 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,147 +285,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 116343633 # number of cpu cycles simulated +system.cpu.numCycles 116293341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14429393 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12066685 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 532769 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13006399 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 6718907 # Number of BTB hits +system.cpu.BPredUnit.lookups 14403200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12045652 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 530716 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12993662 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6702662 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 975114 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45137 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29132882 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 73870037 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14429393 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7694021 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 14329837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2400358 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36580859 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259840 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 335514 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 170 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9103703 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330872 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 82240103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.898224 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.215946 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 972407 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45058 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29094387 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 73505774 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14403200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7675069 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14268794 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2359863 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36645005 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31889 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259043 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335706 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051868 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 321893 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 82174946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.894503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211429 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67910266 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1028745 1.25% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2026192 2.46% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 969086 1.18% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2957231 3.60% 91.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 692695 0.84% 91.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 793723 0.97% 92.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070407 1.30% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4791758 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67906152 82.64% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1023009 1.24% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2022244 2.46% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 965640 1.18% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2953506 3.59% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 686113 0.83% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 790817 0.96% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1067854 1.30% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4759611 5.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 82240103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.124024 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.634930 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30393620 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36243117 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 13115942 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 960226 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1527197 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 611480 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42119 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 72202344 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128169 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1527197 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31599738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12790599 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19770106 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12256569 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4295892 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 68223425 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6893 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 500375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1520799 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 45688467 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 82930883 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 82451857 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479026 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38262876 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7425583 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1700626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 251543 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12011289 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10748783 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7011270 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1273745 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 840870 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 59873388 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116185 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 58064745 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115927 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8494287 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4438181 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1448436 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 82240103 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.706039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.353017 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 82174946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123852 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.632072 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30353273 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36299982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13051372 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 972104 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1498214 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 610003 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42096 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 71896046 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 128197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1498214 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31555942 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12820674 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19773044 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12199083 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4327987 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 67967172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7022 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504365 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1538985 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 45476353 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 82567749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 82088652 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479097 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38265070 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7211275 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1700634 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251496 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12093975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10722948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6992313 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1255970 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 835280 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 59689379 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116105 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57965210 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118570 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8314088 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4277616 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1448303 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 82174946 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.352124 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56753994 69.01% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11193552 13.61% 82.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5499635 6.69% 89.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3512602 4.27% 93.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2643529 3.21% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1548822 1.88% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 707324 0.86% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 273213 0.33% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 107432 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56717955 69.02% 69.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11192734 13.62% 82.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5489796 6.68% 89.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3501881 4.26% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2637968 3.21% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1562716 1.90% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 689256 0.84% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 274867 0.33% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 107773 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 82240103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 82174946 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64991 8.48% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 378109 49.32% 57.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323577 42.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 67060 8.71% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 379426 49.28% 57.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 323507 42.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39655118 68.29% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62174 0.11% 68.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39583689 68.29% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62189 0.11% 68.41% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.46% # Type of FU issued @@ -448,112 +448,112 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.46% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10635929 18.32% 86.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722688 11.58% 98.36% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952312 1.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10615864 18.31% 86.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6714571 11.58% 98.36% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952373 1.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 58064745 # Type of FU issued -system.cpu.iq.rate 0.499080 # Inst issue rate -system.cpu.iq.fu_busy_cnt 766677 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013204 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 198560467 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 70176120 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 56485252 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 691729 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 332805 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328298 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58461376 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362765 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 576950 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57965210 # Type of FU issued +system.cpu.iq.rate 0.498440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 769993 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013284 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 198301844 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 69800593 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56410393 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 332994 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328299 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58364794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363128 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 575597 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1635037 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13784 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 26178 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 618376 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1608607 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13533 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14401 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 599018 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18266 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 170591 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18904 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170936 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1527197 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8965647 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616674 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 65615916 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 866303 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10748783 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7011270 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1869859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 484759 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15737 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 26178 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 387398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 383164 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 770562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57355078 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10233934 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 709666 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1498214 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8974617 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617389 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 65429620 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 865390 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10722948 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6992313 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1869565 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 485054 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15735 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14401 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 385242 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 382803 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 768045 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57270091 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10215279 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 695118 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3626343 # number of nop insts executed -system.cpu.iew.exec_refs 16894519 # number of memory reference insts executed -system.cpu.iew.exec_branches 9105401 # Number of branches executed -system.cpu.iew.exec_stores 6660585 # Number of stores executed -system.cpu.iew.exec_rate 0.492980 # Inst execution rate -system.cpu.iew.wb_sent 56953037 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56813550 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28082126 # num instructions producing a value -system.cpu.iew.wb_consumers 37827297 # num instructions consuming a value +system.cpu.iew.exec_nop 3624136 # number of nop insts executed +system.cpu.iew.exec_refs 16869985 # number of memory reference insts executed +system.cpu.iew.exec_branches 9097351 # Number of branches executed +system.cpu.iew.exec_stores 6654706 # Number of stores executed +system.cpu.iew.exec_rate 0.492462 # Inst execution rate +system.cpu.iew.wb_sent 56872608 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56738692 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28028831 # num instructions producing a value +system.cpu.iew.wb_consumers 37767423 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.488325 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742377 # average fanout of values written-back +system.cpu.iew.wb_rate 0.487893 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 56289333 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9199733 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 667749 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 702560 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80712906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.697402 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.610815 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 56292492 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9013620 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667802 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 700532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80676732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.697754 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.611305 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59526212 73.75% 73.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8907000 11.04% 84.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4712189 5.84% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2603041 3.23% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533921 1.90% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 653559 0.81% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475046 0.59% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 520427 0.64% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1781511 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59494729 73.74% 73.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8894659 11.03% 84.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4715834 5.85% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2613071 3.24% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1534221 1.90% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 644957 0.80% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475888 0.59% 97.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 517029 0.64% 97.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1786344 2.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80712906 # Number of insts commited each cycle -system.cpu.commit.count 56289333 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 80676732 # Number of insts commited each cycle +system.cpu.commit.count 56292492 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15506640 # Number of memory references committed -system.cpu.commit.loads 9113746 # Number of loads committed -system.cpu.commit.membars 227885 # Number of memory barriers committed -system.cpu.commit.branches 8462674 # Number of branches committed +system.cpu.commit.refs 15507636 # Number of memory references committed +system.cpu.commit.loads 9114341 # Number of loads committed +system.cpu.commit.membars 227905 # Number of memory barriers committed +system.cpu.commit.branches 8463183 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52127663 # Number of committed integer instructions. -system.cpu.commit.function_calls 744579 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1781511 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52130666 # Number of committed integer instructions. +system.cpu.commit.function_calls 744656 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1786344 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 144169402 # The number of ROB reads -system.cpu.rob.rob_writes 132508314 # The number of ROB writes -system.cpu.timesIdled 1255085 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34103530 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 53094627 # Number of Instructions Simulated -system.cpu.committedInsts_total 53094627 # Number of Instructions Simulated -system.cpu.cpi 2.191251 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.191251 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456360 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456360 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 75184837 # number of integer regfile reads -system.cpu.int_regfile_writes 41033576 # number of integer regfile writes -system.cpu.fp_regfile_reads 166484 # number of floating regfile reads -system.cpu.fp_regfile_writes 167413 # number of floating regfile writes -system.cpu.misc_regfile_reads 1996811 # number of misc regfile reads -system.cpu.misc_regfile_writes 949905 # number of misc regfile writes +system.cpu.rob.rob_reads 143945413 # The number of ROB reads +system.cpu.rob.rob_writes 132113260 # The number of ROB writes +system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53097697 # Number of Instructions Simulated +system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated +system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.190177 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456584 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456584 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75078413 # number of integer regfile reads +system.cpu.int_regfile_writes 40965985 # number of integer regfile writes +system.cpu.fp_regfile_reads 166494 # number of floating regfile reads +system.cpu.fp_regfile_writes 167403 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996876 # number of misc regfile reads +system.cpu.misc_regfile_writes 949968 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -585,231 +585,231 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1004633 # number of replacements -system.cpu.icache.tagsinuse 509.950442 # Cycle average of tags in use -system.cpu.icache.total_refs 8037423 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1005142 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.996306 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 23350341000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.950442 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8037424 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8037424 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8037424 # number of demand (read+write) hits +system.cpu.icache.replacements 1004954 # number of replacements +system.cpu.icache.tagsinuse 509.962774 # Cycle average of tags in use +system.cpu.icache.total_refs 7985922 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005463 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.942532 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23358245000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.962774 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996021 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 7985923 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7985923 # number of ReadReq hits +system.cpu.icache.demand_hits::0 7985923 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8037424 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8037424 # number of overall hits +system.cpu.icache.demand_hits::total 7985923 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 7985923 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8037424 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1066279 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066279 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1066279 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 7985923 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1065945 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065945 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1065945 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066279 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1066279 # number of overall misses +system.cpu.icache.demand_misses::total 1065945 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1065945 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1066279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15932595494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15932595494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15932595494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9103703 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9103703 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9103703 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1065945 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15930410995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15930410995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15930410995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9051868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9051868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9051868 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9103703 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9103703 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9051868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9051868 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9103703 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.117126 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.117126 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9051868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.117760 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.117760 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.117126 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.117760 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14942.238846 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14944.871447 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14942.238846 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14944.871447 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14942.238846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14944.871447 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1325996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1290996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10607.968000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10581.934426 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 235 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 60920 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 60920 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 60920 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1005359 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1005359 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1005359 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 60269 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 60269 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 60269 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005676 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005676 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005676 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12047978496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12047978496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12047978496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12050431496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12050431496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12050431496 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110434 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.110434 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.111101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.110434 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.111101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.757539 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11983.757539 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11982.419284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11982.419284 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402933 # number of replacements -system.cpu.dcache.tagsinuse 511.995988 # Cycle average of tags in use -system.cpu.dcache.total_refs 12110548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1403445 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.629158 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19282000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.995988 # Average occupied blocks per context +system.cpu.dcache.replacements 1403374 # number of replacements +system.cpu.dcache.tagsinuse 511.996006 # Cycle average of tags in use +system.cpu.dcache.total_refs 12090411 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1403886 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.612103 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.996006 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7476386 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7476386 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4221734 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4221734 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 192117 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192117 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 220089 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 220089 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 11698120 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 7456106 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7456106 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4221921 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4221921 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192075 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192075 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220104 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220104 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11678027 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11698120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 11698120 # number of overall hits +system.cpu.dcache.demand_hits::total 11678027 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11678027 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11698120 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1807054 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1807054 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1935931 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1935931 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 22609 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22609 # number of LoadLockedReq misses +system.cpu.dcache.overall_hits::total 11678027 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1809770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1809770 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1936125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1936125 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 22580 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3742985 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3745895 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3742985 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3742985 # number of overall misses +system.cpu.dcache.demand_misses::total 3745895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3745895 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3742985 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 38901669000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 57798606480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 338580500 # number of LoadLockedReq miss cycles +system.cpu.dcache.overall_misses::total 3745895 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38933932500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57800126852 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 338100500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 96700275480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 96700275480 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9283440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9283440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6157665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 214726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 220091 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 220091 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15441105 # number of demand (read+write) accesses +system.cpu.dcache.demand_miss_latency 96734059352 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 96734059352 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9265876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9265876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6158046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6158046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 214655 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214655 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220106 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220106 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15423922 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15441105 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15441105 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 15423922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15423922 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15441105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.194653 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.314394 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105292 # miss rate for LoadLockedReq accesses +system.cpu.dcache.overall_accesses::total 15423922 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.195316 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.314406 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105192 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.242404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.242863 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.242404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.242863 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 21527.673772 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 21513.193665 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.716180 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29853.509898 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14975.474369 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14973.449956 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 25835.068930 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25824.017852 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 25835.068930 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25824.017852 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 919195309 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 917367309 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 193500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 102335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 103073 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8982.218293 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8900.170840 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 24187.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 834763 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 719698 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1637137 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 5136 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2356835 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2356835 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1087356 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 298794 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17473 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks 834855 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 722036 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1637277 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5104 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2359313 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2359313 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1087734 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298848 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17476 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1386150 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1386150 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 1386582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1386582 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24800644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8504282309 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206126500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24802725500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8508331309 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206132500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33304926309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33304926309 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904508000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234433998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2138941998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117129 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency 33311056809 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33311056809 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905005000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234795498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2139800498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117391 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048530 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081373 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081414 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.089770 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089898 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.089770 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089898 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22808.210007 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28462.025037 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11796.858010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22802.197504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28470.430818 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11795.176242 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24026.928045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24023.863579 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -817,27 +817,27 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6435 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211583 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74879 40.96% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1881 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105809 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182812 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73512 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1881 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73515 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211595 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74877 40.96% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 245 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1882 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105819 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182823 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73510 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 245 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1882 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73514 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149151 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819252477000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94027000 0.01% 97.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 384302500 0.02% 97.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38165726500 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1857896533000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981744 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks::0 1820223133000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94250000 0.01% 97.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 384615500 0.02% 97.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38170735500 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1858872734000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981743 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694715 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -876,29 +876,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175475 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6786 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175482 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6787 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5215 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5217 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192432 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5954 # number of protection mode switches +system.cpu.kern.callpal::total 192442 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5953 # number of protection mode switches system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2103 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.320289 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320343 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080837 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401126 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29181178000 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2689752000 0.14% 1.72% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1826025595000 98.28% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.401064 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29154617000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2680769000 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827037340000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 4580778bd..3a986614c 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/chips/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 523f8a126..04178bb32 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -13,7 +13,6 @@ warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index dcb3e878e..eb8b03237 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 16:54:46 -gem5 started Aug 18 2011 17:16:56 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 20 2011 15:41:18 +gem5 started Aug 20 2011 15:46:02 +gem5 executing on zizzer command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582677547500 because m5_exit instruction encountered +Exiting @ tick 2582520130500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a5d979727..b36a36f09 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.582678 # Number of seconds simulated -sim_ticks 2582677547500 # Number of ticks simulated +sim_seconds 2.582520 # Number of seconds simulated +sim_ticks 2582520130500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75295 # Simulator instruction rate (inst/s) -host_tick_rate 2435818565 # Simulator tick rate (ticks/s) -host_mem_usage 423776 # Number of bytes of host memory used -host_seconds 1060.29 # Real time elapsed on the host -sim_insts 79834358 # Number of instructions simulated -system.l2c.replacements 130785 # number of replacements -system.l2c.tagsinuse 27318.484309 # Cycle average of tags in use -system.l2c.total_refs 1826531 # Total number of references to valid blocks. -system.l2c.sampled_refs 161304 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.323532 # Average number of references to valid blocks. +host_inst_rate 84908 # Simulator instruction rate (inst/s) +host_tick_rate 2745493933 # Simulator tick rate (ticks/s) +host_mem_usage 385348 # Number of bytes of host memory used +host_seconds 940.64 # Real time elapsed on the host +sim_insts 79867485 # Number of instructions simulated +system.l2c.replacements 132224 # number of replacements +system.l2c.tagsinuse 27582.981749 # Cycle average of tags in use +system.l2c.total_refs 1821382 # Total number of references to valid blocks. +system.l2c.sampled_refs 162180 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.230620 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 5406.863178 # Average occupied blocks per context -system.l2c.occ_blocks::1 6677.424533 # Average occupied blocks per context -system.l2c.occ_blocks::2 15234.196598 # Average occupied blocks per context -system.l2c.occ_percent::0 0.082502 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.101889 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.232455 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 803697 # number of ReadReq hits -system.l2c.ReadReq_hits::1 562068 # number of ReadReq hits -system.l2c.ReadReq_hits::2 188134 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1553899 # number of ReadReq hits -system.l2c.Writeback_hits::0 603483 # number of Writeback hits -system.l2c.Writeback_hits::total 603483 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1202 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 810 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2012 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 219 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 351 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 570 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 63626 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 37284 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 100910 # number of ReadExReq hits -system.l2c.demand_hits::0 867323 # number of demand (read+write) hits -system.l2c.demand_hits::1 599352 # number of demand (read+write) hits -system.l2c.demand_hits::2 188134 # number of demand (read+write) hits -system.l2c.demand_hits::total 1654809 # number of demand (read+write) hits -system.l2c.overall_hits::0 867323 # number of overall hits -system.l2c.overall_hits::1 599352 # number of overall hits -system.l2c.overall_hits::2 188134 # number of overall hits -system.l2c.overall_hits::total 1654809 # number of overall hits -system.l2c.ReadReq_misses::0 22876 # number of ReadReq misses -system.l2c.ReadReq_misses::1 16980 # number of ReadReq misses -system.l2c.ReadReq_misses::2 159 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40015 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 6837 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3470 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10307 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 768 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 499 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1267 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 99026 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 49105 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148131 # number of ReadExReq misses -system.l2c.demand_misses::0 121902 # number of demand (read+write) misses -system.l2c.demand_misses::1 66085 # number of demand (read+write) misses -system.l2c.demand_misses::2 159 # number of demand (read+write) misses -system.l2c.demand_misses::total 188146 # number of demand (read+write) misses -system.l2c.overall_misses::0 121902 # number of overall misses -system.l2c.overall_misses::1 66085 # number of overall misses -system.l2c.overall_misses::2 159 # number of overall misses -system.l2c.overall_misses::total 188146 # number of overall misses -system.l2c.ReadReq_miss_latency 2090784500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 57155000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 7364000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7771362499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9862146999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9862146999 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 826573 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 579048 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 188293 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1593914 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 603483 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 603483 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8039 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4280 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12319 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 987 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 850 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1837 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 162652 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 86389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249041 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 989225 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 665437 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 188293 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1842955 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 989225 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 665437 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 188293 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1842955 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027676 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.029324 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000844 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.057844 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.850479 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.810748 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.778116 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.587059 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.608821 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.568417 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.123230 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.099311 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000844 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.223385 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.123230 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.099311 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000844 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.223385 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 91396.419829 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 123132.184923 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 13149588.050314 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 13364116.655067 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8359.660670 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 16471.181556 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 5000.765535 # Average occupied blocks per context +system.l2c.occ_blocks::1 7177.119061 # Average occupied blocks per context +system.l2c.occ_blocks::2 15405.097153 # Average occupied blocks per context +system.l2c.occ_percent::0 0.076306 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.109514 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.235063 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 739666 # number of ReadReq hits +system.l2c.ReadReq_hits::1 629011 # number of ReadReq hits +system.l2c.ReadReq_hits::2 183263 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1551940 # number of ReadReq hits +system.l2c.Writeback_hits::0 599118 # number of Writeback hits +system.l2c.Writeback_hits::total 599118 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 1040 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1060 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2100 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 181 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 449 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 630 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 58369 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 39072 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 97441 # number of ReadExReq hits +system.l2c.demand_hits::0 798035 # number of demand (read+write) hits +system.l2c.demand_hits::1 668083 # number of demand (read+write) hits +system.l2c.demand_hits::2 183263 # number of demand (read+write) hits +system.l2c.demand_hits::total 1649381 # number of demand (read+write) hits +system.l2c.overall_hits::0 798035 # number of overall hits +system.l2c.overall_hits::1 668083 # number of overall hits +system.l2c.overall_hits::2 183263 # number of overall hits +system.l2c.overall_hits::total 1649381 # number of overall hits +system.l2c.ReadReq_misses::0 19689 # number of ReadReq misses +system.l2c.ReadReq_misses::1 20600 # number of ReadReq misses +system.l2c.ReadReq_misses::2 170 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40459 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 7392 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3836 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11228 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 461 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1325 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 98007 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 50222 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148229 # number of ReadExReq misses +system.l2c.demand_misses::0 117696 # number of demand (read+write) misses +system.l2c.demand_misses::1 70822 # number of demand (read+write) misses +system.l2c.demand_misses::2 170 # number of demand (read+write) misses +system.l2c.demand_misses::total 188688 # number of demand (read+write) misses +system.l2c.overall_misses::0 117696 # number of overall misses +system.l2c.overall_misses::1 70822 # number of overall misses +system.l2c.overall_misses::2 170 # number of overall misses +system.l2c.overall_misses::total 188688 # number of overall misses +system.l2c.ReadReq_miss_latency 2113875000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 61547500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 8091500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7780940999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9894815999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9894815999 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 759355 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 649611 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 183433 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1592399 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 599118 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 599118 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 8432 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4896 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13328 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1045 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 910 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1955 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 156376 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 89294 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245670 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 915731 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 738905 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 183433 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1838069 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 915731 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 738905 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 183433 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1838069 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.025929 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.031711 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.000927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.058567 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.876660 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.783497 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.826794 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.506593 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.626739 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.562434 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.128527 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.095847 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.000927 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.225301 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.128527 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.095847 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.000927 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.225301 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 107363.248514 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 102615.291262 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 12434558.823529 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12644537.363306 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8326.231061 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 16044.708029 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9588.541667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 14757.515030 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 9365.162037 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17552.060738 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 78478.000717 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 158260.105875 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 79391.686298 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 154930.926666 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 80902.257543 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 149234.274026 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 62026081.754717 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 62256218.286286 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 80902.257543 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 149234.274026 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 62026081.754717 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 62256218.286286 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 84070.962471 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 139713.874206 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 58204799.994118 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 58428584.830795 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 84070.962471 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 139713.874206 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 58204799.994118 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 58428584.830795 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,56 +143,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111655 # number of writebacks -system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 99 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 39916 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 10307 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1267 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 188047 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 188047 # number of overall MSHR misses +system.l2c.writebacks 112853 # number of writebacks +system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 94 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 40365 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 11228 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1325 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 148229 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 188594 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 188594 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1599541500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 412620000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 50764500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5935595999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7535137499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7535137499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131969781000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32516901535 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164486682535 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.048291 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.068934 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.211989 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.329214 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.282125 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.408178 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1617473000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 449580000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 53034500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5939516999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7556989999 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7556989999 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131965465500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32542103084 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164507568584 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.053157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.062137 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.220053 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.335347 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.331594 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.293301 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.283688 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.490588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.267943 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456044 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.910724 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.714697 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.947901 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.660011 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.190095 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.282592 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0.998694 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.471381 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.190095 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.282592 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0.998694 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.471381 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40072.690149 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40032.987290 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40066.692976 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40069.911085 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40070.500986 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.205949 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.255234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.028136 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.489319 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.205949 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.255234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.028136 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.489319 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40071.175523 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40040.969006 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40026.037736 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40069.871611 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40070.150689 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -207,27 +207,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 41192849 # DTB read hits -system.cpu0.dtb.read_misses 63693 # DTB read misses -system.cpu0.dtb.write_hits 7450240 # DTB write hits -system.cpu0.dtb.write_misses 14279 # DTB write misses +system.cpu0.dtb.read_hits 42414340 # DTB read hits +system.cpu0.dtb.read_misses 56223 # DTB read misses +system.cpu0.dtb.write_hits 6898086 # DTB write hits +system.cpu0.dtb.write_misses 11305 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2696 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 5912 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 640 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2713 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 11513 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 590 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1671 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 41256542 # DTB read accesses -system.cpu0.dtb.write_accesses 7464519 # DTB write accesses +system.cpu0.dtb.perms_faults 1641 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 42470563 # DTB read accesses +system.cpu0.dtb.write_accesses 6909391 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 48643089 # DTB hits -system.cpu0.dtb.misses 77972 # DTB misses -system.cpu0.dtb.accesses 48721061 # DTB accesses -system.cpu0.itb.inst_hits 7154156 # ITB inst hits -system.cpu0.itb.inst_misses 18344 # ITB inst misses +system.cpu0.dtb.hits 49312426 # DTB hits +system.cpu0.dtb.misses 67528 # DTB misses +system.cpu0.dtb.accesses 49379954 # DTB accesses +system.cpu0.itb.inst_hits 6438737 # ITB inst hits +system.cpu0.itb.inst_misses 18334 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -236,520 +236,516 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1605 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 6284 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 6092 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 7172500 # ITB inst accesses -system.cpu0.itb.hits 7154156 # DTB hits -system.cpu0.itb.misses 18344 # DTB misses -system.cpu0.itb.accesses 7172500 # DTB accesses -system.cpu0.numCycles 357540967 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6457071 # ITB inst accesses +system.cpu0.itb.hits 6438737 # DTB hits +system.cpu0.itb.misses 18334 # DTB misses +system.cpu0.itb.accesses 6457071 # DTB accesses +system.cpu0.numCycles 352502516 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9593725 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 7120843 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 688397 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8086863 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5605356 # Number of BTB hits +system.cpu0.BPredUnit.lookups 8652992 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 6404778 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 637693 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7363134 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5053345 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 917445 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 151480 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 18599757 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50204356 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9593725 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6522801 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12725278 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3026243 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 114823 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 80197472 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 119675 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 131982 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 222 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7147681 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 329179 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 9806 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 114004183 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.572281 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.836691 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 807352 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 136692 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 16884109 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45966993 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8652992 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5860697 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11522341 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2668103 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 112168 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 79167270 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 2014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 119305 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 115037 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6432455 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 291981 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 9711 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 109779148 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.541337 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.795461 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 101298717 88.86% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1249230 1.10% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1702654 1.49% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1440887 1.26% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1218688 1.07% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 996216 0.87% 94.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 913152 0.80% 95.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 546684 0.48% 95.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4637955 4.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98275003 89.52% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 1141137 1.04% 90.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1489424 1.36% 91.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1304085 1.19% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1112037 1.01% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 879763 0.80% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 783842 0.71% 95.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 505631 0.46% 96.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4288226 3.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 114004183 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.026833 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.140416 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19798941 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 79925582 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 11493306 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 769981 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2016373 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1516743 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 98250 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62465027 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 321354 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2016373 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20942863 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33418227 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41890543 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11135381 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4600796 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59851687 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1820 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 622371 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3206696 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 196 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 60092077 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 271645522 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 271595503 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 50019 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 44620651 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15471425 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 873594 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 797183 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8821523 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 12757061 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 8422181 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1717649 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1992572 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 55833489 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1355727 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 82528607 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 169777 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11480759 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26808481 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257868 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 114004183 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.723909 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.428339 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109779148 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.024547 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.130402 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18050945 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78849390 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10366657 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 743574 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1768582 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1352275 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89418 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56923097 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 298418 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1768582 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19113011 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 33326039 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 41047359 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10060323 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4463834 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54560689 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1472 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 580904 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 3150021 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 227 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54846534 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 247844774 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 247794895 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 49879 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 41443860 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13402673 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 827250 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 762254 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8494444 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 11787351 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7696820 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1444181 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1562010 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51022975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1296408 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80307756 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 139273 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9946263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22977035 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 252908 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109779148 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731539 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.440195 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 83031906 72.83% 72.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10859028 9.53% 82.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4622462 4.05% 86.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3473838 3.05% 89.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9590269 8.41% 97.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1336341 1.17% 99.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 758222 0.67% 99.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 245908 0.22% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 86209 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 80155628 73.02% 73.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10112206 9.21% 82.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4137187 3.77% 86.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3171994 2.89% 88.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9961890 9.07% 97.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1265964 1.15% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 671041 0.61% 99.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 224336 0.20% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 78902 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 114004183 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109779148 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 40984 0.54% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 430 0.01% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7316558 95.62% 96.16% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 293687 3.84% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 37945 0.47% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 630 0.01% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 7705227 95.96% 96.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 285473 3.56% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 88545 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 32461139 39.33% 39.44% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 66584 0.08% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1699 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 39.52% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 41999048 50.89% 90.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7911577 9.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29747563 37.04% 37.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 62367 0.08% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 5 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 4 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1707 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 43146000 53.73% 90.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 7261641 9.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 82528607 # Type of FU issued -system.cpu0.iq.rate 0.230823 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 7651659 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.092715 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 286948190 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 68723133 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50664328 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11541 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7288 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5232 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 90085763 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5958 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 417346 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 80307756 # Type of FU issued +system.cpu0.iq.rate 0.227822 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8029275 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.099981 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 278618763 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62278383 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46688761 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11606 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7153 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5243 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 88242529 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6041 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 399833 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2922980 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 6316 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 61885 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1142353 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2542386 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5153 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20600 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1003035 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 30234184 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13064 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 32220164 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 13264 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2016373 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25967321 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 376582 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57371840 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 294662 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 12757061 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 8422181 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 894783 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 65983 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6042 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 61885 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 548006 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 156688 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 704694 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 81662256 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 41659868 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 866351 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1768582 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 25955516 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 355771 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 52493661 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 246498 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 11787351 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7696820 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 864266 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62537 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20600 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 509776 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 136927 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 646703 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 79579333 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 42855337 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 728423 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 182624 # number of nop insts executed -system.cpu0.iew.exec_refs 49452351 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7085446 # Number of branches executed -system.cpu0.iew.exec_stores 7792483 # Number of stores executed -system.cpu0.iew.exec_rate 0.228400 # Inst execution rate -system.cpu0.iew.wb_sent 81169545 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50669560 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26746507 # num instructions producing a value -system.cpu0.iew.wb_consumers 50218305 # num instructions consuming a value +system.cpu0.iew.exec_nop 174278 # number of nop insts executed +system.cpu0.iew.exec_refs 50025973 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6436853 # Number of branches executed +system.cpu0.iew.exec_stores 7170636 # Number of stores executed +system.cpu0.iew.exec_rate 0.225755 # Inst execution rate +system.cpu0.iew.wb_sent 79157088 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46694004 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24804627 # num instructions producing a value +system.cpu0.iew.wb_consumers 46107956 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.141717 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.532605 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.132464 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.537968 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 45235360 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 11991795 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1097859 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 616755 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112037138 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.403753 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.265449 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 41930270 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 10408005 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1043500 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 570177 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 108054182 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.388049 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.248702 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 93611832 83.55% 83.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 10012247 8.94% 92.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2707975 2.42% 94.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1499111 1.34% 96.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1132088 1.01% 97.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 700448 0.63% 97.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 719513 0.64% 98.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 269232 0.24% 98.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1384692 1.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 91026362 84.24% 84.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 9315133 8.62% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2453841 2.27% 95.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1345650 1.25% 96.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1029771 0.95% 97.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 653477 0.60% 97.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 658529 0.61% 98.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 238490 0.22% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1332929 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112037138 # Number of insts commited each cycle -system.cpu0.commit.count 45235360 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 108054182 # Number of insts commited each cycle +system.cpu0.commit.count 41930270 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 17113909 # Number of memory references committed -system.cpu0.commit.loads 9834081 # Number of loads committed -system.cpu0.commit.membars 304797 # Number of memory barriers committed -system.cpu0.commit.branches 6085015 # Number of branches committed -system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 40053285 # Number of committed integer instructions. -system.cpu0.commit.function_calls 683094 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1384692 # number cycles where commit BW limit reached +system.cpu0.commit.refs 15938750 # Number of memory references committed +system.cpu0.commit.loads 9244965 # Number of loads committed +system.cpu0.commit.membars 288660 # Number of memory barriers committed +system.cpu0.commit.branches 5543054 # Number of branches committed +system.cpu0.commit.fp_insts 4980 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 37176133 # Number of committed integer instructions. +system.cpu0.commit.function_calls 620334 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1332929 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 166715497 # The number of ROB reads -system.cpu0.rob.rob_writes 116483375 # The number of ROB writes -system.cpu0.timesIdled 1500698 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 243536784 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 45109533 # Number of Instructions Simulated -system.cpu0.committedInsts_total 45109533 # Number of Instructions Simulated -system.cpu0.cpi 7.926062 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.926062 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.126166 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.126166 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 365152407 # number of integer regfile reads -system.cpu0.int_regfile_writes 50032906 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4200 # number of floating regfile reads +system.cpu0.rob.rob_reads 157975997 # The number of ROB reads +system.cpu0.rob.rob_writes 106454954 # The number of ROB writes +system.cpu0.timesIdled 1454281 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 242723368 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 41804443 # Number of Instructions Simulated +system.cpu0.committedInsts_total 41804443 # Number of Instructions Simulated +system.cpu0.cpi 8.432178 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.432178 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.118593 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.118593 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 354304839 # number of integer regfile reads +system.cpu0.int_regfile_writes 46156049 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4230 # number of floating regfile reads system.cpu0.fp_regfile_writes 1342 # number of floating regfile writes -system.cpu0.misc_regfile_reads 71323581 # number of misc regfile reads -system.cpu0.misc_regfile_writes 671757 # number of misc regfile writes -system.cpu0.icache.replacements 594199 # number of replacements -system.cpu0.icache.tagsinuse 511.628418 # Cycle average of tags in use -system.cpu0.icache.total_refs 6500767 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 594711 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.930968 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6436890000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.628418 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999274 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 6500767 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6500767 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 6500767 # number of demand (read+write) hits +system.cpu0.misc_regfile_reads 65708495 # number of misc regfile reads +system.cpu0.misc_regfile_writes 636034 # number of misc regfile writes +system.cpu0.icache.replacements 540132 # number of replacements +system.cpu0.icache.tagsinuse 511.623908 # Cycle average of tags in use +system.cpu0.icache.total_refs 5846805 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 540644 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.814519 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 511.623908 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 5846805 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5846805 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5846805 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6500767 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 6500767 # number of overall hits +system.cpu0.icache.demand_hits::total 5846805 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5846805 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6500767 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 646785 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 646785 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 646785 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 5846805 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 585522 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 585522 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 585522 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 646785 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 646785 # number of overall misses +system.cpu0.icache.demand_misses::total 585522 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 585522 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 646785 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 9658555994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 9658555994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 9658555994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 7147552 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7147552 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 7147552 # number of demand (read+write) accesses +system.cpu0.icache.overall_misses::total 585522 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 8762208993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 8762208993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 8762208993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6432327 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6432327 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6432327 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7147552 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 7147552 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::total 6432327 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6432327 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7147552 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.090490 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.090490 # miss rate for demand accesses +system.cpu0.icache.overall_accesses::total 6432327 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.091028 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.091028 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.090490 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.091028 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14933.178713 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14964.781841 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14933.178713 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14964.781841 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14933.178713 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14964.781841 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1667497 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1480495 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 196 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7444.183036 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7553.545918 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 31555 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 52053 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 52053 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 52053 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 594732 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 594732 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 594732 # number of overall MSHR misses +system.cpu0.icache.writebacks 29912 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 44859 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 44859 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 44859 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 540663 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 540663 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 540663 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 7219185997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 7219185997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 7219185997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 6562850995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 6562850995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 6562850995 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083208 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.084054 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.083208 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.084054 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.083208 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.084054 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.553158 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12138.553158 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12138.524358 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12138.524358 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 392671 # number of replacements -system.cpu0.dcache.tagsinuse 483.584669 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13959325 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 393183 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 35.503379 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 372646 # number of replacements +system.cpu0.dcache.tagsinuse 487.071508 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12784845 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 373158 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.261211 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 486.484981 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -2.900311 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.950166 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.005665 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 8695002 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 8695002 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4786521 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4786521 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 223142 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 223142 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 209904 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 209904 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 13481523 # number of demand (read+write) hits +system.cpu0.dcache.occ_blocks::0 487.071508 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.951312 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 7969031 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7969031 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 4348200 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4348200 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 221332 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 221332 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 199760 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199760 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 12317231 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13481523 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 13481523 # number of overall hits +system.cpu0.dcache.demand_hits::total 12317231 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 12317231 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 13481523 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 481329 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 481329 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1933412 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1933412 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 10228 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10228 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7385 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7385 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 2414741 # number of demand (read+write) misses +system.cpu0.dcache.overall_hits::total 12317231 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 463423 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 463423 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1863605 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1863605 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 9962 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9962 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 7780 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 2327028 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2414741 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 2414741 # number of overall misses +system.cpu0.dcache.demand_misses::total 2327028 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 2327028 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2414741 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 6831199500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 71775006335 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 125537000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 81774000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 78606205835 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 78606205835 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 9176331 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9176331 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6719933 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6719933 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 233370 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 233370 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 217289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 217289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 15896264 # number of demand (read+write) accesses +system.cpu0.dcache.overall_misses::total 2327028 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 6461559500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 70508741836 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 120808500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 88519000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 76970301336 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 76970301336 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8432454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8432454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6211805 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6211805 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 231294 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 231294 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 207540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 207540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14644259 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15896264 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 15896264 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14644259 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 14644259 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15896264 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.052453 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.287713 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043827 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.033987 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.151906 # miss rate for demand accesses +system.cpu0.dcache.overall_accesses::total 14644259 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.054957 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.300010 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043071 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037487 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.158904 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.151906 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::0 0.158904 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 14192.370499 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 13943.113527 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37123.492735 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 37834.595763 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12273.856081 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12126.932343 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11072.985782 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11377.763496 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 32552.644708 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 33076.654572 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 32552.644708 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 33076.654572 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7515481 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2368000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 844 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8904.598341 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18076.335878 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 6713488 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1808000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 859 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7815.469150 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 14699.186992 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 345751 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 230083 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1750706 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 435 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1980789 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1980789 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 251246 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 182706 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9793 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7384 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 433952 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 433952 # number of overall MSHR misses +system.cpu0.dcache.writebacks 327128 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 223214 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1685177 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 329 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1908391 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1908391 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 240209 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 178428 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9633 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 7778 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 418637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 418637 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 3167466500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6457872480 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 89563500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 59583000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9625338980 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9625338980 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 139101280000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1100636486 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 140201916486 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.027380 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 2943893000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6377983487 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86869500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65155000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 9321876487 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 9321876487 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959490000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038770484 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 139998260484 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028486 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.027189 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028724 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041963 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.033982 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037477 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.027299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.028587 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.027299 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.028587 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12607.032550 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35345.705560 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9145.665271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8069.203684 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22180.653575 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12255.548293 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35745.418247 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9017.907194 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8376.832091 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 22267.206403 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -758,27 +754,27 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 9398153 # DTB read hits -system.cpu1.dtb.read_misses 34944 # DTB read misses -system.cpu1.dtb.write_hits 4980209 # DTB write hits -system.cpu1.dtb.write_misses 12567 # DTB write misses +system.cpu1.dtb.read_hits 10576986 # DTB read hits +system.cpu1.dtb.read_misses 41991 # DTB read misses +system.cpu1.dtb.write_hits 5532460 # DTB write hits +system.cpu1.dtb.write_misses 15559 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7467 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 5132 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 777 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 9433097 # DTB read accesses -system.cpu1.dtb.write_accesses 4992776 # DTB write accesses +system.cpu1.dtb.perms_faults 787 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10618977 # DTB read accesses +system.cpu1.dtb.write_accesses 5548019 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14378362 # DTB hits -system.cpu1.dtb.misses 47511 # DTB misses -system.cpu1.dtb.accesses 14425873 # DTB accesses -system.cpu1.itb.inst_hits 7673879 # ITB inst hits -system.cpu1.itb.inst_misses 3663 # ITB inst misses +system.cpu1.dtb.hits 16109446 # DTB hits +system.cpu1.dtb.misses 57550 # DTB misses +system.cpu1.dtb.accesses 16166996 # DTB accesses +system.cpu1.itb.inst_hits 8208666 # ITB inst hits +system.cpu1.itb.inst_misses 3757 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -787,520 +783,516 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1371 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2297 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2255 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7677542 # ITB inst accesses -system.cpu1.itb.hits 7673879 # DTB hits -system.cpu1.itb.misses 3663 # DTB misses -system.cpu1.itb.accesses 7677542 # DTB accesses -system.cpu1.numCycles 64448888 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8212423 # ITB inst accesses +system.cpu1.itb.hits 8208666 # DTB hits +system.cpu1.itb.misses 3757 # DTB misses +system.cpu1.itb.accesses 8212423 # DTB accesses +system.cpu1.numCycles 69081256 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 7492397 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6087986 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 429995 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6556371 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5183364 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8330796 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 6738871 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 503522 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7267639 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5704343 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 581252 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 90679 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 16050492 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 59173184 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7492397 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5764616 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 12912375 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4437648 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 50354 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 14454862 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 2217 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 33931 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 110303 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 194 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7671208 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 720838 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2326 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 46632146 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.521202 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.768696 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 683793 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 107847 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 17620797 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 62561411 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8330796 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6388136 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13917594 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4639299 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 49548 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 15790396 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 3022 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 34407 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 125274 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 237 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8206050 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 760093 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2394 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 50674659 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.494403 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.744832 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 33727851 72.33% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 606934 1.30% 73.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1038343 2.23% 75.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2380602 5.11% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1071399 2.30% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 528430 1.13% 84.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1841086 3.95% 88.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 362782 0.78% 89.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5074719 10.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 36764920 72.55% 72.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 704096 1.39% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1222881 2.41% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2516311 4.97% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1142608 2.25% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 651052 1.28% 84.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1887369 3.72% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403735 0.80% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5381687 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 46632146 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.116253 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.918141 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17056644 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 14680691 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11594841 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 352795 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2947175 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 935072 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 71695 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 65351582 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 230259 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2947175 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18144332 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3419554 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 9765064 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 10859095 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1496926 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 59649280 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2711 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 296113 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 846856 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 41886 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 64117293 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 277536206 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 277482920 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 53286 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 35880340 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28236953 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 382644 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 338532 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3807140 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10355028 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6398549 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 758675 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 956516 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 52234406 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 583658 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 46076403 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 106678 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 17743407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 51695034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 121990 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 46632146 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.988082 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.605820 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 50674659 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.120594 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.905621 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18672830 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16053118 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12511393 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 382905 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3054413 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1082178 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 80433 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69756936 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 260341 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3054413 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19817710 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3624621 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 10850261 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11740016 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1587638 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63840108 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3002 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 319994 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 862075 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 38212 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 68266339 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 296265404 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 296212618 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52786 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39108942 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29157397 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 433648 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 381432 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4194062 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11085935 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7020391 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 635108 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 890373 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 56044948 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 651331 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 50360925 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 120514 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18223761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52593424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 131996 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 50674659 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.993809 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.617399 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 29554282 63.38% 63.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5171149 11.09% 74.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3458614 7.42% 81.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3350013 7.18% 89.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2774412 5.95% 95.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1396410 2.99% 98.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 685832 1.47% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 188175 0.40% 99.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 53259 0.11% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 32153473 63.45% 63.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5526378 10.91% 74.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3775422 7.45% 81.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3611274 7.13% 88.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2989508 5.90% 94.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1557590 3.07% 97.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 784960 1.55% 99.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 214293 0.42% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61761 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 46632146 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 50674659 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 13884 1.72% 1.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1004 0.12% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 591453 73.41% 75.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199352 24.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 15522 1.51% 1.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1191 0.12% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 749386 73.14% 74.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 258502 25.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 18555 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 30356671 65.88% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45470 0.10% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 778 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10369047 22.50% 88.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5285878 11.47% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32758484 65.05% 65.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 50347 0.10% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 759 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11614499 23.06% 88.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5918207 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 46076403 # Type of FU issued -system.cpu1.iq.rate 0.714929 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 805693 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017486 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 139732039 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 70588254 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 40690264 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12584 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7193 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5833 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 46856971 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6570 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 234193 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 50360925 # Type of FU issued +system.cpu1.iq.rate 0.729010 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1024601 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020345 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 152586143 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 74924785 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 44270347 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12757 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7087 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5824 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 51360226 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6678 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 266055 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3842003 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 5600 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 34715 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1441399 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3973405 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7375 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 12287 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1481060 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1340152 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1120623 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 1850150 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1139659 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2947175 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2308626 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 70118 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 52866942 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 210917 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10355028 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6398549 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 369018 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28955 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3115 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 34715 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 320337 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 109623 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 429960 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 43402987 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 9638435 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2673416 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3054413 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2505400 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 71046 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56747555 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 255776 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11085935 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7020391 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 408110 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28416 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3434 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 12287 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 384769 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 125659 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 510428 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 47569274 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10848117 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2791651 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 48878 # number of nop insts executed -system.cpu1.iew.exec_refs 14847152 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5186837 # Number of branches executed -system.cpu1.iew.exec_stores 5208717 # Number of stores executed -system.cpu1.iew.exec_rate 0.673448 # Inst execution rate -system.cpu1.iew.wb_sent 42199254 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 40696097 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22507628 # num instructions producing a value -system.cpu1.iew.wb_consumers 40593312 # num instructions consuming a value +system.cpu1.iew.exec_nop 51276 # number of nop insts executed +system.cpu1.iew.exec_refs 16673626 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5809146 # Number of branches executed +system.cpu1.iew.exec_stores 5825509 # Number of stores executed +system.cpu1.iew.exec_rate 0.688599 # Inst execution rate +system.cpu1.iew.wb_sent 46311223 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 44276171 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24275566 # num instructions producing a value +system.cpu1.iew.wb_consumers 44463888 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.631448 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.554466 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.640929 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545961 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 34749379 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18015602 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 461668 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 380980 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 43720356 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.794810 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.823117 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38087596 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18562736 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 519335 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 450588 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 47661477 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.799127 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835707 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 31867002 72.89% 72.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5587415 12.78% 85.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1616564 3.70% 89.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 871952 1.99% 91.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 744460 1.70% 93.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 803606 1.84% 94.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 559765 1.28% 96.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 398216 0.91% 97.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1271376 2.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 34693281 72.79% 72.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6099066 12.80% 85.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1834262 3.85% 89.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 962147 2.02% 91.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 825706 1.73% 93.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 739217 1.55% 94.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 588574 1.23% 95.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 450580 0.95% 96.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1468644 3.08% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 43720356 # Number of insts commited each cycle -system.cpu1.commit.count 34749379 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 47661477 # Number of insts commited each cycle +system.cpu1.commit.count 38087596 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 11470175 # Number of memory references committed -system.cpu1.commit.loads 6513025 # Number of loads committed -system.cpu1.commit.membars 132167 # Number of memory barriers committed -system.cpu1.commit.branches 4257777 # Number of branches committed +system.cpu1.commit.refs 12651861 # Number of memory references committed +system.cpu1.commit.loads 7112530 # Number of loads committed +system.cpu1.commit.membars 148745 # Number of memory barriers committed +system.cpu1.commit.branches 4804762 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 31123411 # Number of committed integer instructions. -system.cpu1.commit.function_calls 369866 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1271376 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 34029989 # Number of committed integer instructions. +system.cpu1.commit.function_calls 433336 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1468644 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 94544262 # The number of ROB reads -system.cpu1.rob.rob_writes 108591524 # The number of ROB writes -system.cpu1.timesIdled 403013 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 17816742 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 34724825 # Number of Instructions Simulated -system.cpu1.committedInsts_total 34724825 # Number of Instructions Simulated -system.cpu1.cpi 1.855989 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.855989 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.538796 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.538796 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 204029035 # number of integer regfile reads -system.cpu1.int_regfile_writes 43806802 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4161 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes -system.cpu1.misc_regfile_reads 72521776 # number of misc regfile reads -system.cpu1.misc_regfile_writes 283678 # number of misc regfile writes -system.cpu1.icache.replacements 430439 # number of replacements -system.cpu1.icache.tagsinuse 498.734431 # Cycle average of tags in use -system.cpu1.icache.total_refs 7202456 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 430951 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 16.712935 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74509623000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.734431 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.974091 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7202456 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7202456 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7202456 # number of demand (read+write) hits +system.cpu1.rob.rob_reads 102084600 # The number of ROB reads +system.cpu1.rob.rob_writes 116474424 # The number of ROB writes +system.cpu1.timesIdled 450576 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18406597 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 38063042 # Number of Instructions Simulated +system.cpu1.committedInsts_total 38063042 # Number of Instructions Simulated +system.cpu1.cpi 1.814917 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.814917 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550989 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550989 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 222881114 # number of integer regfile reads +system.cpu1.int_regfile_writes 47167594 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4241 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1808 # number of floating regfile writes +system.cpu1.misc_regfile_reads 77248425 # number of misc regfile reads +system.cpu1.misc_regfile_writes 323332 # number of misc regfile writes +system.cpu1.icache.replacements 486491 # number of replacements +system.cpu1.icache.tagsinuse 498.789046 # Cycle average of tags in use +system.cpu1.icache.total_refs 7677673 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 487003 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 15.765145 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 498.789046 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 7677673 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7677673 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 7677673 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7202456 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7202456 # number of overall hits +system.cpu1.icache.demand_hits::total 7677673 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 7677673 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 7202456 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 468704 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 468704 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 468704 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 7677673 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 528325 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 528325 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 528325 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 468704 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 468704 # number of overall misses +system.cpu1.icache.demand_misses::total 528325 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 528325 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 468704 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 6861113492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 6861113492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 6861113492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 7671160 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7671160 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 7671160 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 528325 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7771273996 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7771273996 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7771273996 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 8205998 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8205998 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 8205998 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7671160 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 7671160 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 8205998 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 8205998 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7671160 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.061099 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.061099 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 8205998 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.064383 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.064383 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.061099 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.064383 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14638.478639 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14709.267962 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14638.478639 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14709.267962 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14638.478639 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14709.267962 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1040994 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 1184497 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 141 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 157 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7382.936170 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7544.566879 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18963 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 37728 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 37728 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 37728 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 430976 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 430976 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 430976 # number of overall MSHR misses +system.cpu1.icache.writebacks 18578 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 41295 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 41295 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 41295 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 487030 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 487030 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 487030 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5122297994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5122297994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5122297994 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5811540497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5811540497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5811540497 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.056181 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059350 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.056181 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.059350 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.056181 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.059350 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11885.343950 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11885.343950 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11932.612975 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11932.612975 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # 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number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 46249656862 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 148116500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 88362500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 51314959362 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 51314959362 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 7406139 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7406139 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 4413843 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4413843 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 88002 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 88002 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 83694 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83694 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 11819982 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10694850 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 10694850 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11819982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 11819982 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10694850 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.044179 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.316500 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.153755 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.140812 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.143612 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 11819982 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.043780 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.288715 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144315 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.135244 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.143612 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.135244 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15485.619989 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15622.029601 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36568.819277 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 36292.942216 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11518.339768 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11662.716535 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8286.411992 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7963.455299 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32451.229978 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 32100.258330 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32451.229978 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 32100.258330 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 10791088 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5629500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 2675 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4034.051589 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33912.650602 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 13378551 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5449500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3082 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4340.866645 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34710.191083 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 207215 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 126705 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1124640 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 1020 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1251345 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1251345 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 173260 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 111299 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10894 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 10338 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 284559 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 284559 # number of overall MSHR misses +system.cpu1.dcache.writebacks 223500 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 134561 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 1158019 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 988 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 1292580 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 1292580 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 189680 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 116324 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 11712 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 11095 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 306004 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 306004 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2232969500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3340467088 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 89924500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54610500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5573436588 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5573436588 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8313873500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41408758936 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49722632436 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025518 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2497244500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 3447430551 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 55002000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 5944675051 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 5944675051 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455396000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503639517 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 49959035517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025611 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.028502 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026354 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140591 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133088 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.140785 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132566 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.026607 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.025889 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.026607 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.025889 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12887.968948 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 30013.451046 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8254.497889 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5282.501451 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19586.224959 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13165.565690 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29636.451214 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8468.280396 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4957.368184 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19426.788705 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1361,8 +1353,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308159015940 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308159015940 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1308164389827 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1308164389827 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -1377,8 +1369,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 61327 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 55750 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 36142 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 41971 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 8cd80ba37..79ce98ed4 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_loader=/chips/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 44872c771..b45c8117b 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -3,11 +3,12 @@ Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 18 2011 19:13:50 -gem5 started Aug 18 2011 19:17:05 -gem5 executing on nadc-0330 +gem5 compiled Aug 20 2011 15:41:18 +gem5 started Aug 20 2011 15:46:02 +gem5 executing on zizzer command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503824454500 because m5_exit instruction encountered +Exiting @ tick 2503587516500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index f5e789429..ae3ccdd2b 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,108 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503824 # Number of seconds simulated -sim_ticks 2503824454500 # Number of ticks simulated +sim_seconds 2.503588 # Number of seconds simulated +sim_ticks 2503587516500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79718 # Simulator instruction rate (inst/s) -host_tick_rate 2598962996 # Simulator tick rate (ticks/s) -host_mem_usage 429452 # Number of bytes of host memory used -host_seconds 963.39 # Real time elapsed on the host -sim_insts 76800038 # Number of instructions simulated -system.l2c.replacements 119528 # number of replacements -system.l2c.tagsinuse 25937.630096 # Cycle average of tags in use -system.l2c.total_refs 1800987 # Total number of references to valid blocks. -system.l2c.sampled_refs 150361 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.977754 # Average number of references to valid blocks. +host_inst_rate 84198 # Simulator instruction rate (inst/s) +host_tick_rate 2745069755 # Simulator tick rate (ticks/s) +host_mem_usage 385208 # Number of bytes of host memory used +host_seconds 912.03 # Real time elapsed on the host +sim_insts 76790714 # Number of instructions simulated +system.l2c.replacements 119531 # number of replacements +system.l2c.tagsinuse 25929.939584 # Cycle average of tags in use +system.l2c.total_refs 1799445 # Total number of references to valid blocks. +system.l2c.sampled_refs 150368 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.966941 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11548.723381 # Average occupied blocks per context -system.l2c.occ_blocks::1 14388.906715 # Average occupied blocks per context -system.l2c.occ_percent::0 0.176220 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219557 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1352767 # number of ReadReq hits -system.l2c.ReadReq_hits::1 155574 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1508341 # number of ReadReq hits -system.l2c.Writeback_hits::0 630909 # number of Writeback hits -system.l2c.Writeback_hits::total 630909 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 19 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105993 # number of ReadExReq hits -system.l2c.demand_hits::0 1458760 # number of demand (read+write) hits -system.l2c.demand_hits::1 155574 # number of demand (read+write) hits -system.l2c.demand_hits::total 1614334 # number of demand (read+write) hits -system.l2c.overall_hits::0 1458760 # number of overall hits -system.l2c.overall_hits::1 155574 # number of overall hits -system.l2c.overall_hits::total 1614334 # number of overall hits -system.l2c.ReadReq_misses::0 36107 # number of ReadReq misses -system.l2c.ReadReq_misses::1 150 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36257 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3257 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3257 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 9 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140403 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140403 # number of ReadExReq misses -system.l2c.demand_misses::0 176510 # number of demand (read+write) misses -system.l2c.demand_misses::1 150 # number of demand (read+write) misses -system.l2c.demand_misses::total 176660 # number of demand (read+write) misses -system.l2c.overall_misses::0 176510 # number of overall misses -system.l2c.overall_misses::1 150 # number of overall misses -system.l2c.overall_misses::total 176660 # number of overall misses -system.l2c.ReadReq_miss_latency 1897665500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1154500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 52000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7382579000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9280244500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9280244500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1388874 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 155724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1544598 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 630909 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 630909 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3306 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3306 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 28 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246396 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1635270 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 155724 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1790994 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1635270 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 155724 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1790994 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025997 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000963 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026961 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.985178 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.321429 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569827 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.107939 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000963 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108903 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.107939 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000963 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108903 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52556.720304 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12651103.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12703660.053637 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 354.467301 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11550.967581 # Average occupied blocks per context +system.l2c.occ_blocks::1 14378.972003 # Average occupied blocks per context +system.l2c.occ_percent::0 0.176254 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.219406 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1351962 # number of ReadReq hits +system.l2c.ReadReq_hits::1 155464 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1507426 # number of ReadReq hits +system.l2c.Writeback_hits::0 630774 # number of Writeback hits +system.l2c.Writeback_hits::total 630774 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 105933 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105933 # number of ReadExReq hits +system.l2c.demand_hits::0 1457895 # number of demand (read+write) hits +system.l2c.demand_hits::1 155464 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613359 # number of demand (read+write) hits +system.l2c.overall_hits::0 1457895 # number of overall hits +system.l2c.overall_hits::1 155464 # number of overall hits +system.l2c.overall_hits::total 1613359 # number of overall hits +system.l2c.ReadReq_misses::0 36117 # number of ReadReq misses +system.l2c.ReadReq_misses::1 148 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36265 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3244 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3244 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 140419 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140419 # number of ReadExReq misses +system.l2c.demand_misses::0 176536 # number of demand (read+write) misses +system.l2c.demand_misses::1 148 # number of demand (read+write) misses +system.l2c.demand_misses::total 176684 # number of demand (read+write) misses +system.l2c.overall_misses::0 176536 # number of overall misses +system.l2c.overall_misses::1 148 # number of overall misses +system.l2c.overall_misses::total 176684 # number of overall misses +system.l2c.ReadReq_miss_latency 1896887000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 953000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7384203500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9281090500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9281090500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1388079 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 155612 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1543691 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 630774 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 630774 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 246352 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246352 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1634431 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 155612 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1790043 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1634431 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 155612 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1790043 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026019 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000951 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026970 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.987219 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.105263 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.569993 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.108011 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000951 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108962 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.108011 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000951 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108962 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52520.613561 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12816804.054054 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12869324.667616 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 293.773120 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 5777.777778 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52581.347977 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52586.925559 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52576.310124 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 61868296.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61920872.976791 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52576.310124 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 61868296.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61920872.976791 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52573.358975 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 62710070.945946 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 62762644.304921 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52573.358975 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 62710070.945946 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 62762644.304921 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -111,50 +107,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102659 # number of writebacks -system.l2c.ReadReq_mshr_hits 99 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 99 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 99 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36158 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3257 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 9 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140403 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176561 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176561 # number of overall MSHR misses +system.l2c.writebacks 102665 # number of writebacks +system.l2c.ReadReq_mshr_hits 95 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 95 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 36170 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3244 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 140419 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 176589 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 176589 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1452283500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 131732500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 360000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5638732500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7091016000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7091016000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131768110500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32345431294 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164113541794 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026034 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.232193 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.258227 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.985178 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1451509500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 130965000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5640198500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7091708000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7091708000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131769561500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32342663570 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164112225070 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026058 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.232437 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.258495 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.987219 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.321429 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.105263 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.569993 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.107971 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.133807 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.241778 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.107971 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.133807 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.241778 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40164.928923 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40445.962542 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.108043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.134803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.242846 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.108043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.134803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.242846 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40130.204589 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40371.454994 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40161.054251 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40161.847747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40161.847747 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40166.918295 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40159.398377 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -169,27 +165,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51109554 # DTB read hits -system.cpu.dtb.read_misses 89772 # DTB read misses -system.cpu.dtb.write_hits 11994703 # DTB write hits -system.cpu.dtb.write_misses 25525 # DTB write misses +system.cpu.dtb.read_hits 52225825 # DTB read hits +system.cpu.dtb.read_misses 89986 # DTB read misses +system.cpu.dtb.write_hits 11975736 # DTB write hits +system.cpu.dtb.write_misses 26350 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 8382 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 661 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4338 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 8018 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 617 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2390 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51199326 # DTB read accesses -system.cpu.dtb.write_accesses 12020228 # DTB write accesses +system.cpu.dtb.perms_faults 2450 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52315811 # DTB read accesses +system.cpu.dtb.write_accesses 12002086 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63104257 # DTB hits -system.cpu.dtb.misses 115297 # DTB misses -system.cpu.dtb.accesses 63219554 # DTB accesses -system.cpu.itb.inst_hits 14358238 # ITB inst hits -system.cpu.itb.inst_misses 11476 # ITB inst misses +system.cpu.dtb.hits 64201561 # DTB hits +system.cpu.dtb.misses 116336 # DTB misses +system.cpu.dtb.accesses 64317897 # DTB accesses +system.cpu.itb.inst_hits 14135631 # ITB inst hits +system.cpu.itb.inst_misses 11185 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -198,516 +194,516 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2618 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2607 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8489 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8440 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14369714 # ITB inst accesses -system.cpu.itb.hits 14358238 # DTB hits -system.cpu.itb.misses 11476 # DTB misses -system.cpu.itb.accesses 14369714 # DTB accesses -system.cpu.numCycles 416612538 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 14146816 # ITB inst accesses +system.cpu.itb.hits 14135631 # DTB hits +system.cpu.itb.misses 11185 # DTB misses +system.cpu.itb.accesses 14146816 # DTB accesses +system.cpu.numCycles 415920995 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16387222 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12668617 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1109677 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14122008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10400042 # Number of BTB hits +system.cpu.BPredUnit.lookups 16219215 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12559944 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1110172 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13927920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10224432 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1438387 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 228434 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33205064 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105935094 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16387222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11838429 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24790129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7281806 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 140399 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92648607 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 149325 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 219222 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 315 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14348946 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1053874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6421 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 156122024 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.843787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.188312 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1424516 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 228409 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32955891 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104818490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16219215 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11648948 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24471055 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7079806 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 137198 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92799321 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 151217 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217200 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 351 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14126420 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1047323 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6165 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155547085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.838560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.184344 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131359328 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1797067 1.15% 85.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2650142 1.70% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3706376 2.37% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2183779 1.40% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1469088 0.94% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2676851 1.71% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 859477 0.55% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9419916 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131101786 84.28% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1736791 1.12% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2601051 1.67% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3653656 2.35% 89.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2169863 1.39% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1434892 0.92% 91.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2627328 1.69% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 855909 0.55% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9365809 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 156122024 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.039334 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.254277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35461706 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92496954 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22296946 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1073972 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4792446 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2336165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 178310 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123347211 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 575607 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4792446 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37647350 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36719045 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49837786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21186830 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5938567 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115130197 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4438 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 893530 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3968160 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 43280 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 119684467 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529404061 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529305097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 98964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77501999 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42182467 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1209283 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1098761 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12191274 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 22237858 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14288032 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2207613 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2740072 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 103897694 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1876028 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126150518 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 258491 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28028723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 75807996 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 377489 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 156122024 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.494664 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155547085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038996 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.252015 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35186802 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92649693 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21977926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094000 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4638664 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2316854 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 177884 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122073457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 575981 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4638664 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37340555 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36816085 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49864787 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20912628 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5974366 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 113922984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4414 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 914987 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3980816 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 42327 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118460665 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 523781573 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 523685374 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96199 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77493785 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 40966879 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1201529 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1095575 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12285551 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 22000628 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14180796 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1905529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2295702 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102943309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1872075 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126931651 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252428 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27053062 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73124308 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 373806 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155547085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.816034 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505599 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109310496 70.02% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15452280 9.90% 79.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7704093 4.93% 84.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6547773 4.19% 89.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12500649 8.01% 97.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2674638 1.71% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1385356 0.89% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 415101 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 131638 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108904431 70.01% 70.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15118772 9.72% 79.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7542016 4.85% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6525767 4.20% 88.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12768009 8.21% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2736654 1.76% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1396269 0.90% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 422710 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132457 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 156122024 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155547085 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45842 0.53% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 8 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8169590 94.68% 95.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412814 4.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45562 0.51% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8415938 94.58% 95.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436851 4.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60408589 47.89% 47.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96901 0.08% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2257 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52851212 41.90% 89.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12685017 10.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60109955 47.36% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96551 0.08% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 3 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 3 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2253 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53954328 42.51% 90.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12662017 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126150518 # Type of FU issued -system.cpu.iq.rate 0.302801 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8628254 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.068397 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 417401182 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 133881929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87720713 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23251 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13846 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134660044 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12198 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 599778 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126931651 # Type of FU issued +system.cpu.iq.rate 0.305182 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8898356 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070104 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 418652883 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131886553 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87334534 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23945 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13416 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10473 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 135710724 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12753 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 616189 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6553966 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11010 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 95494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2507321 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6319666 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11234 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32604 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2401616 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32840687 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1141901 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34061863 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1153574 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4792446 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28191284 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 424606 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 105991714 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 477393 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 22237858 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14288032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1227462 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 89856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7011 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 95494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 852380 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256698 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109078 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122676478 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51808342 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3474040 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4638664 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28343669 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 418971 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 105030898 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 476967 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 22000628 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14180796 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1225085 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 85041 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7449 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32604 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 851635 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 257956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1109591 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123477395 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52923959 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3454256 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 217992 # number of nop insts executed -system.cpu.iew.exec_refs 64319690 # number of memory reference insts executed -system.cpu.iew.exec_branches 11745709 # Number of branches executed -system.cpu.iew.exec_stores 12511348 # Number of stores executed -system.cpu.iew.exec_rate 0.294462 # Inst execution rate -system.cpu.iew.wb_sent 120986716 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87731231 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47245202 # num instructions producing a value -system.cpu.iew.wb_consumers 86878076 # num instructions consuming a value +system.cpu.iew.exec_nop 215514 # number of nop insts executed +system.cpu.iew.exec_refs 65415175 # number of memory reference insts executed +system.cpu.iew.exec_branches 11714146 # Number of branches executed +system.cpu.iew.exec_stores 12491216 # Number of stores executed +system.cpu.iew.exec_rate 0.296877 # Inst execution rate +system.cpu.iew.wb_sent 121817988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87345007 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47064551 # num instructions producing a value +system.cpu.iew.wb_consumers 86684992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210582 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.543810 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210004 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.542938 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76950419 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 28805793 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1498539 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 978025 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151411950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.508219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.450093 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 76941095 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27854412 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1498269 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 978817 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150990773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.509575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459429 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122345277 80.80% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15024261 9.92% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4072409 2.69% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238793 1.48% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1805162 1.19% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1472326 0.97% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1253236 0.83% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 640621 0.42% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2559865 1.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122133629 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14849154 9.83% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4108732 2.72% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2181203 1.44% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1788420 1.18% 96.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1359682 0.90% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1260703 0.83% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 659440 0.44% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2649810 1.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151411950 # Number of insts commited each cycle -system.cpu.commit.count 76950419 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 150990773 # Number of insts commited each cycle +system.cpu.commit.count 76941095 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27464603 # Number of memory references committed -system.cpu.commit.loads 15683892 # Number of loads committed -system.cpu.commit.membars 413156 # Number of memory barriers committed -system.cpu.commit.branches 9892324 # Number of branches committed +system.cpu.commit.refs 27460142 # Number of memory references committed +system.cpu.commit.loads 15680962 # Number of loads committed +system.cpu.commit.membars 413062 # Number of memory barriers committed +system.cpu.commit.branches 9891108 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68502645 # Number of committed integer instructions. -system.cpu.commit.function_calls 995827 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2559865 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68494112 # Number of committed integer instructions. +system.cpu.commit.function_calls 995603 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2649810 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 252851506 # The number of ROB reads -system.cpu.rob.rob_writes 216434899 # The number of ROB writes -system.cpu.timesIdled 1874952 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260490514 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 76800038 # Number of Instructions Simulated -system.cpu.committedInsts_total 76800038 # Number of Instructions Simulated -system.cpu.cpi 5.424640 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.424640 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184344 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184344 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 556945889 # number of integer regfile reads -system.cpu.int_regfile_writes 90207171 # number of integer regfile writes -system.cpu.fp_regfile_reads 8143 # number of floating regfile reads -system.cpu.fp_regfile_writes 2804 # number of floating regfile writes -system.cpu.misc_regfile_reads 138641891 # number of misc regfile reads -system.cpu.misc_regfile_writes 912464 # number of misc regfile writes -system.cpu.icache.replacements 993778 # number of replacements -system.cpu.icache.tagsinuse 511.609153 # Cycle average of tags in use -system.cpu.icache.total_refs 13263624 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 994290 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.339794 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6449865000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.609153 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999237 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13263624 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13263624 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13263624 # number of demand (read+write) hits +system.cpu.rob.rob_reads 251379971 # The number of ROB reads +system.cpu.rob.rob_writes 214361160 # The number of ROB writes +system.cpu.timesIdled 1877573 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260373910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 76790714 # Number of Instructions Simulated +system.cpu.committedInsts_total 76790714 # Number of Instructions Simulated +system.cpu.cpi 5.416293 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.416293 # CPI: Total CPI of All Threads +system.cpu.ipc 0.184628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184628 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 559837261 # number of integer regfile reads +system.cpu.int_regfile_writes 89743570 # number of integer regfile writes +system.cpu.fp_regfile_reads 8283 # number of floating regfile reads +system.cpu.fp_regfile_writes 2809 # number of floating regfile writes +system.cpu.misc_regfile_reads 137364406 # number of misc regfile reads +system.cpu.misc_regfile_writes 912286 # number of misc regfile writes +system.cpu.icache.replacements 993006 # number of replacements +system.cpu.icache.tagsinuse 511.614815 # Cycle average of tags in use +system.cpu.icache.total_refs 13045370 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 993518 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.130482 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 511.614815 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.999248 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 13045370 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13045370 # number of ReadReq hits +system.cpu.icache.demand_hits::0 13045370 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13263624 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13263624 # number of overall hits +system.cpu.icache.demand_hits::total 13045370 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 13045370 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 13263624 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1085201 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1085201 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1085201 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 13045370 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1080929 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1080929 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1080929 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1085201 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1085201 # number of overall misses +system.cpu.icache.demand_misses::total 1080929 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1080929 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1085201 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15970611491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15970611491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15970611491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14348825 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14348825 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14348825 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1080929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15935046488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15935046488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15935046488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 14126299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14126299 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 14126299 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14348825 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14348825 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 14126299 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 14126299 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14348825 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.075630 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.075630 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 14126299 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.076519 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.076519 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.075630 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.076519 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14716.731270 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14741.991831 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14716.731270 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14741.991831 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14716.731270 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14741.991831 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2367996 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2385493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 355 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 357 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6670.411268 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6682.053221 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57801 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 90865 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 90865 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 90865 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 994336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 994336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 994336 # number of overall MSHR misses +system.cpu.icache.writebacks 57770 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 87373 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 87373 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 87373 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 993556 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 993556 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 993556 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11881405996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11881405996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11881405996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11874405493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11874405493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11874405493 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.069297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.070334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.069297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.070334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.085617 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11949.085617 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11949.085617 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11951.420446 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11951.420446 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644301 # number of replacements -system.cpu.dcache.tagsinuse 511.991682 # Cycle average of tags in use -system.cpu.dcache.total_refs 22398030 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644813 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.735699 # Average number of references to valid blocks. +system.cpu.dcache.replacements 644346 # number of replacements +system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use +system.cpu.dcache.total_refs 22273031 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644858 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.539435 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.991682 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14543242 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14543242 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7265728 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7265728 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 300074 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 300074 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285526 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285526 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21808970 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 14419247 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14419247 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 7264920 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264920 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 299971 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 299971 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 285485 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285485 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 21684167 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21808970 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21808970 # number of overall hits +system.cpu.dcache.demand_hits::total 21684167 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 21684167 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 21808970 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 725476 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 725476 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2967115 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2967115 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13509 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13509 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110353624242 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 218944000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 357000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 121242808742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121242808742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 15143510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 15143510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10231358 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231358 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 313459 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 313459 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 285504 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285504 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 25374868 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25501561 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25501561 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 25374868 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 25374868 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25501561 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047514 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289960 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043080 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000102 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.144799 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 25374868 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.047827 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.289936 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043030 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.145447 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.144799 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.145447 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15009.100232 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15034.848529 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37173.142514 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 37200.718249 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16228.403287 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16232.502966 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 26862.068966 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 18789.473684 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32818.617266 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 32850.888962 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32818.617266 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 32850.888962 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16440438 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7572500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2965 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5544.835750 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26757.950530 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 16719933 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7529000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2957 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5654.356781 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27180.505415 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 573108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 338981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2717547 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3056528 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3056528 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 386495 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249568 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12056 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 29 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 636063 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 636063 # number of overall MSHR misses +system.cpu.dcache.writebacks 573004 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 337704 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2716896 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1445 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3054600 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3054600 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 386559 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249542 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 12043 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 636101 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 636101 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5252112000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8923093438 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161656000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 684500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14175205438 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14175205438 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147157433500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42270831280 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189428264780 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025313 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 5253783500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8925189433 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161542500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 293500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14178972933 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14178972933 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158793000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258212210 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 189417005210 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025526 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024389 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024390 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038420 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000102 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000067 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.024942 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025068 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.024942 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025068 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13589.081359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35754.156935 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13408.759124 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 23603.448276 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22285.851304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22285.851304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13591.155555 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.281560 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13413.808852 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15447.368421 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22290.442765 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -768,8 +764,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308136733935 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308136733935 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1307895610037 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1307895610037 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -784,6 +780,6 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88013 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 23340838e..336a6fed4 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -1301,7 +1301,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1321,7 +1321,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index c0ff48d52..96389038f 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 17 2011 19:14:00 -gem5 started Aug 17 2011 19:16:38 -gem5 executing on nadc-0388 +gem5 compiled Aug 20 2011 15:40:58 +gem5 started Aug 20 2011 15:42:13 +gem5 executing on zizzer command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5139621012500 because m5_exit instruction encountered +Exiting @ tick 5147601271500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 74858b319..e13689c4a 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.139621 # Number of seconds simulated -sim_ticks 5139621012500 # Number of ticks simulated +sim_seconds 5.147601 # Number of seconds simulated +sim_ticks 5147601271500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264330 # Simulator instruction rate (inst/s) -host_tick_rate 1617420466 # Simulator tick rate (ticks/s) -host_mem_usage 409996 # Number of bytes of host memory used -host_seconds 3177.67 # Real time elapsed on the host -sim_insts 839951837 # Number of instructions simulated -system.l2c.replacements 170440 # number of replacements -system.l2c.tagsinuse 38394.915319 # Cycle average of tags in use -system.l2c.total_refs 3798996 # Total number of references to valid blocks. -system.l2c.sampled_refs 206462 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.400461 # Average number of references to valid blocks. +host_inst_rate 290249 # Simulator instruction rate (inst/s) +host_tick_rate 1780077210 # Simulator tick rate (ticks/s) +host_mem_usage 361700 # Number of bytes of host memory used +host_seconds 2891.79 # Real time elapsed on the host +sim_insts 839336586 # Number of instructions simulated +system.l2c.replacements 169225 # number of replacements +system.l2c.tagsinuse 38391.632338 # Cycle average of tags in use +system.l2c.total_refs 3787611 # Total number of references to valid blocks. +system.l2c.sampled_refs 204461 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.524858 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11966.871938 # Average occupied blocks per context -system.l2c.occ_blocks::1 26428.043381 # Average occupied blocks per context -system.l2c.occ_percent::0 0.182600 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403260 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2331798 # number of ReadReq hits -system.l2c.ReadReq_hits::1 145238 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2477036 # number of ReadReq hits -system.l2c.Writeback_hits::0 1588821 # number of Writeback hits -system.l2c.Writeback_hits::total 1588821 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 321 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 321 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 149873 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 149873 # number of ReadExReq hits -system.l2c.demand_hits::0 2481671 # number of demand (read+write) hits -system.l2c.demand_hits::1 145238 # number of demand (read+write) hits -system.l2c.demand_hits::total 2626909 # number of demand (read+write) hits -system.l2c.overall_hits::0 2481671 # number of overall hits -system.l2c.overall_hits::1 145238 # number of overall hits -system.l2c.overall_hits::total 2626909 # number of overall hits -system.l2c.ReadReq_misses::0 68032 # number of ReadReq misses -system.l2c.ReadReq_misses::1 90 # number of ReadReq misses -system.l2c.ReadReq_misses::total 68122 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3926 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3926 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142738 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142738 # number of ReadExReq misses -system.l2c.demand_misses::0 210770 # number of demand (read+write) misses -system.l2c.demand_misses::1 90 # number of demand (read+write) misses -system.l2c.demand_misses::total 210860 # number of demand (read+write) misses -system.l2c.overall_misses::0 210770 # number of overall misses -system.l2c.overall_misses::1 90 # number of overall misses -system.l2c.overall_misses::total 210860 # number of overall misses -system.l2c.ReadReq_miss_latency 3572833000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 39364500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7469371500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 11042204500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 11042204500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2399830 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 145328 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2545158 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1588821 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1588821 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4247 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4247 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292611 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292611 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2692441 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 145328 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2837769 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2692441 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 145328 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2837769 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.028349 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028968 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.924417 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.487808 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078282 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000619 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.078901 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078282 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000619 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.078901 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52516.947907 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 39698144.444444 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 39750661.392351 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 10026.617422 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 12004.760540 # Average occupied blocks per context +system.l2c.occ_blocks::1 26386.871797 # Average occupied blocks per context +system.l2c.occ_percent::0 0.183178 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.402632 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2307522 # number of ReadReq hits +system.l2c.ReadReq_hits::1 137003 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2444525 # number of ReadReq hits +system.l2c.Writeback_hits::0 1590016 # number of Writeback hits +system.l2c.Writeback_hits::total 1590016 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 326 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 326 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 147596 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 147596 # number of ReadExReq hits +system.l2c.demand_hits::0 2455118 # number of demand (read+write) hits +system.l2c.demand_hits::1 137003 # number of demand (read+write) hits +system.l2c.demand_hits::total 2592121 # number of demand (read+write) hits +system.l2c.overall_hits::0 2455118 # number of overall hits +system.l2c.overall_hits::1 137003 # number of overall hits +system.l2c.overall_hits::total 2592121 # number of overall hits +system.l2c.ReadReq_misses::0 66466 # number of ReadReq misses +system.l2c.ReadReq_misses::1 86 # number of ReadReq misses +system.l2c.ReadReq_misses::total 66552 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3784 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3784 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142440 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142440 # number of ReadExReq misses +system.l2c.demand_misses::0 208906 # number of demand (read+write) misses +system.l2c.demand_misses::1 86 # number of demand (read+write) misses +system.l2c.demand_misses::total 208992 # number of demand (read+write) misses +system.l2c.overall_misses::0 208906 # number of overall misses +system.l2c.overall_misses::1 86 # number of overall misses +system.l2c.overall_misses::total 208992 # number of overall misses +system.l2c.ReadReq_miss_latency 3490673000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 33240000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7454154500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10944827500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10944827500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2373988 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 137089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2511077 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1590016 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1590016 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4110 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4110 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 290036 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 290036 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2664024 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 137089 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2801113 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2664024 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 137089 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2801113 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027998 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000627 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028625 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.920681 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.491111 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.078417 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000627 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.079045 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.078417 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000627 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.079045 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52518.174706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 40589220.930233 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 40641739.104938 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8784.355180 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52329.243089 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52331.890621 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52389.830147 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 122691161.111111 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 122743550.941258 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52389.830147 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 122691161.111111 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 122743550.941258 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52391.159182 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 127265436.046512 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 127317827.205693 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52391.159182 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 127265436.046512 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 127317827.205693 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142383 # number of writebacks +system.l2c.writebacks 142484 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 68120 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3926 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142738 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 210858 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 210858 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 66550 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3784 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142440 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 208990 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 208990 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2742078500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 157403500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5729564000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8471642500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8471642500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61532429500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222286000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62754715500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028385 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.468733 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.497118 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.924417 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2679045000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 151709500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5718096500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8397141500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8397141500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61568859000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1235122000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62803981000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028033 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.485451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.513484 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.920681 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.487808 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.491111 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078315 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.450911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.529226 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078315 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.450911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.529226 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40253.647974 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.587876 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40140.425115 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40177.003007 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.078449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.524484 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.602933 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.078449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.524484 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.602933 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40256.123216 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.362579 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40143.895675 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.129176 # Cycle average of tags in use +system.iocache.replacements 47520 # number of replacements +system.iocache.tagsinuse 0.153992 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47536 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994509673000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.129176 # Average occupied blocks per context -system.iocache.occ_percent::1 0.008073 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994510016000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.153992 # Average occupied blocks per context +system.iocache.occ_percent::1 0.009624 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses +system.iocache.ReadReq_misses::1 870 # number of ReadReq misses +system.iocache.ReadReq_misses::total 870 # number of ReadReq misses +system.iocache.WriteReq_misses::1 46704 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46704 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses +system.iocache.demand_misses::1 47574 # number of demand (read+write) misses +system.iocache.demand_misses::total 47574 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_miss_latency 113496932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6374731160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6488228092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6488228092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) +system.iocache.overall_misses::1 47574 # number of overall misses +system.iocache.overall_misses::total 47574 # number of overall misses +system.iocache.ReadReq_miss_latency 108834936 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6370051162 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6478886098 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6478886098 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 870 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 870 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 46704 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46704 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47574 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47574 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47574 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47574 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125410.974586 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125097.627586 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136445.444349 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136391.982742 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136235.760462 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136185.439484 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136235.760462 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136185.439484 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68743556 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68653524 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6100.777068 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6092.787007 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks +system.iocache.writebacks 46652 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47625 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47625 # number of overall MSHR misses +system.iocache.ReadReq_mshr_misses 870 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 46704 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 47574 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47574 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66413982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3944974906 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4011388888 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4011388888 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 63576976 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3941129874 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4004706850 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4004706850 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,435 +235,434 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73385.615470 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84438.675214 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84228.638068 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73076.983908 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84385.274794 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2984960 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 811 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449087853 # number of cpu cycles simulated +system.cpu.numCycles 447857914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91217869 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91217869 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248400 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89951778 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83914735 # Number of BTB hits +system.cpu.BPredUnit.lookups 90944358 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90944358 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1226473 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89599267 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83628993 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28382208 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 451447456 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91217869 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83914735 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171329150 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6161718 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 187674 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82029365 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58090 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9909586 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 559902 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3975 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 286820350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.091965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27835932 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 449937499 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90944358 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83628993 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170885862 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5925894 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 181270 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82341776 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 58576 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9686350 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 533599 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3672 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 285953148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.092624 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403694 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116059602 40.46% 40.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1498115 0.52% 40.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72812872 25.39% 66.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1272717 0.44% 66.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2053780 0.72% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3977163 1.39% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1588647 0.55% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2196057 0.77% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85361397 29.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 115559786 40.41% 40.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1486948 0.52% 40.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72839284 25.47% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1399836 0.49% 66.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1849088 0.65% 67.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3956894 1.38% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1519974 0.53% 69.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2050817 0.72% 70.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85290521 29.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 286820350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203118 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.005254 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33356268 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78574400 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165851521 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4241450 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4796711 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 882885518 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 285953148 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.203065 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.004643 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32848686 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 78733964 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165420335 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4337474 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4612689 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 880519790 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4796711 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37592669 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52283630 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10046208 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165609505 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16491627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 878188662 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14524 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11489749 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2124384 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 880584292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1724975571 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1724975011 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843343914 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37240371 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 491374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 493473 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42595982 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19743931 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10730204 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1270430 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1078815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 870972067 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 898477 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866458351 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 218010 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 31071842 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 45598434 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144784 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 286820350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.020910 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373009 # Number of insts issued each cycle +system.cpu.rename.SquashCycles 4612689 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37008244 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52433742 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9987311 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165318823 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16592339 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 876077378 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14259 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11608934 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2117422 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 878323292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1719903468 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1719903124 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 842717831 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35605454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 480050 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 481410 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42986896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19404127 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10589665 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1106439 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 977378 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 869234759 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 887302 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 865293083 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 172874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 29947401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 43606928 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 139213 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 285953148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.025996 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.373161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82323990 28.70% 28.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22353891 7.79% 36.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14123864 4.92% 41.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9769344 3.41% 44.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79473928 27.71% 72.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4992964 1.74% 74.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72968378 25.44% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 634028 0.22% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 179963 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 81963860 28.66% 28.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22232412 7.77% 36.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 13907684 4.86% 41.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9593533 3.35% 44.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79512028 27.81% 72.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4973941 1.74% 74.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72992433 25.53% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 625767 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 151490 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 286820350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 285953148 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 195550 8.86% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1820080 82.44% 91.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 192012 8.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 192405 8.66% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1837790 82.69% 91.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 192432 8.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 302678 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830926438 95.90% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25678898 2.96% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9550337 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 296605 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 830140846 95.94% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25417132 2.94% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9438500 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866458351 # Type of FU issued -system.cpu.iq.rate 1.929374 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2207642 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002548 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022315315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 902983728 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855563326 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 258 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 55 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868363218 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1360799 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 865293083 # Type of FU issued +system.cpu.iq.rate 1.932071 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2222627 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002569 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2019084567 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 900079448 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 854502226 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 147 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 154 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 42 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 867219037 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1353310 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4398376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17098 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 43182 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2298641 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4224491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17341 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10951 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2251290 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 161145 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817207 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4796711 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33445550 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6029017 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871870544 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 303715 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19743931 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10730246 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 897675 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5516781 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26023 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 43182 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 896575 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 530355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1426930 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864313806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25191099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2144544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4612689 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33472492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6015693 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 870122061 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301987 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19404127 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10589719 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 886500 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5552993 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26264 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10951 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 883301 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 519788 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1403089 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 863190269 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24933733 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2102813 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34501157 # number of memory reference insts executed -system.cpu.iew.exec_branches 86709322 # Number of branches executed -system.cpu.iew.exec_stores 9310058 # Number of stores executed -system.cpu.iew.exec_rate 1.924598 # Inst execution rate -system.cpu.iew.wb_sent 863645103 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855563381 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671472669 # num instructions producing a value -system.cpu.iew.wb_consumers 1171866734 # num instructions consuming a value +system.cpu.iew.exec_refs 34134363 # number of memory reference insts executed +system.cpu.iew.exec_branches 86606805 # Number of branches executed +system.cpu.iew.exec_stores 9200630 # Number of stores executed +system.cpu.iew.exec_rate 1.927375 # Inst execution rate +system.cpu.iew.wb_sent 862563162 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 854502268 # cumulative count of insts written-back +system.cpu.iew.wb_producers 670839861 # num instructions producing a value +system.cpu.iew.wb_consumers 1171063083 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905114 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572994 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907976 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572847 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839951837 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 31810372 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 753691 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1255440 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282039656 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.978134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864065 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839336586 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 30675414 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 748087 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1233611 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 281355498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.983189 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.864496 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102542445 36.36% 36.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12533027 4.44% 40.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4681692 1.66% 42.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76967359 27.29% 69.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4010237 1.42% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1852910 0.66% 71.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1082027 0.38% 72.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71603983 25.39% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6765976 2.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102129547 36.30% 36.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12394321 4.41% 40.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4610399 1.64% 42.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76952670 27.35% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4007315 1.42% 71.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1836126 0.65% 71.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1044804 0.37% 72.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71657785 25.47% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6722531 2.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282039656 # Number of insts commited each cycle -system.cpu.commit.count 839951837 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 281355498 # Number of insts commited each cycle +system.cpu.commit.count 839336586 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23777157 # Number of memory references committed -system.cpu.commit.loads 15345552 # Number of loads committed +system.cpu.commit.refs 23518062 # Number of memory references committed +system.cpu.commit.loads 15179633 # Number of loads committed system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85535847 # Number of branches committed +system.cpu.commit.branches 85448275 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768568499 # Number of committed integer instructions. +system.cpu.commit.int_insts 767896653 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6765976 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6722531 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1146952939 # The number of ROB reads -system.cpu.rob.rob_writes 1748336346 # The number of ROB writes -system.cpu.timesIdled 3079654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162267503 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839951837 # Number of Instructions Simulated -system.cpu.committedInsts_total 839951837 # Number of Instructions Simulated -system.cpu.cpi 0.534659 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534659 # CPI: Total CPI of All Threads -system.cpu.ipc 1.870351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.870351 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1407338355 # number of integer regfile reads -system.cpu.int_regfile_writes 857621513 # number of integer regfile writes -system.cpu.fp_regfile_reads 55 # number of floating regfile reads -system.cpu.misc_regfile_reads 282388563 # number of misc regfile reads -system.cpu.misc_regfile_writes 410581 # number of misc regfile writes -system.cpu.icache.replacements 1030220 # number of replacements -system.cpu.icache.tagsinuse 510.462524 # Cycle average of tags in use -system.cpu.icache.total_refs 8809167 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1030732 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.546515 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553868000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.462524 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996997 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8809167 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8809167 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8809167 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1144564074 # The number of ROB reads +system.cpu.rob.rob_writes 1744648535 # The number of ROB writes +system.cpu.timesIdled 3067742 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 161904766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839336586 # Number of Instructions Simulated +system.cpu.committedInsts_total 839336586 # Number of Instructions Simulated +system.cpu.cpi 0.533586 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.533586 # CPI: Total CPI of All Threads +system.cpu.ipc 1.874114 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.874114 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1405583914 # number of integer regfile reads +system.cpu.int_regfile_writes 856547410 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.misc_regfile_reads 281786405 # number of misc regfile reads +system.cpu.misc_regfile_writes 403681 # number of misc regfile writes +system.cpu.icache.replacements 1011974 # number of replacements +system.cpu.icache.tagsinuse 510.480374 # Cycle average of tags in use +system.cpu.icache.total_refs 8606970 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1012486 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.500829 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54553287000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.480374 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997032 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8606970 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8606970 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8606970 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8809167 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8809167 # number of overall hits +system.cpu.icache.demand_hits::total 8606970 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8606970 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8809167 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1100416 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1100416 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1100416 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8606970 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1079377 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079377 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1079377 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1100416 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1100416 # number of overall misses +system.cpu.icache.demand_misses::total 1079377 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1079377 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1100416 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16477170489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16477170489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16477170489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9909583 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9909583 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9909583 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1079377 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16165039489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16165039489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16165039489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9686347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9686347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9686347 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9909583 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9909583 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9686347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9686347 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9909583 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.111046 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.111046 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9686347 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111433 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111433 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111046 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111433 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14973.583162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14976.268245 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14973.583162 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14976.268245 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14973.583162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14976.268245 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2487991 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2584490 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 243 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 245 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10238.646091 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10548.938776 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1561 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 67148 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 67148 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 67148 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1033268 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1033268 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1033268 # number of overall MSHR misses +system.cpu.icache.writebacks 1557 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 64335 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 64335 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 64335 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1015042 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1015042 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1015042 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12490519491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12490519491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12490519491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12263411490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12263411490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12263411490 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104270 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104791 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.104270 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104791 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.104270 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104791 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12088.363804 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12088.363804 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12081.678876 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # 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number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 13090 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 13090 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 14318 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14318 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 13090 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 13090 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 14318 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14318 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 183495000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 183495000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 183495000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 42893 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 42893 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 13090 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 13090 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 170458000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 170458000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 170458000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 40652 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 40652 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 42896 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 42896 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 40655 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 40655 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 42896 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 42896 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.333807 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 40655 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 40655 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.322001 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.333784 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.321978 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.333784 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.321978 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.686548 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 13022.001528 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.686548 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 13022.001528 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.686548 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 13022.001528 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +672,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2322 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2568 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 14318 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 14318 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 14318 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 13090 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 13090 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 13090 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 140154000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 140154000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 140154000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 130828500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 130828500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 130828500 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.333807 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.322001 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.333784 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.321978 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.333784 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.321978 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9788.657634 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9788.657634 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9994.537815 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 143345 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.852844 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 148404 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 143358 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.035199 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934943000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.852844 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.865803 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 148429 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 148429 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 134574 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.858456 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 145276 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 134589 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.079405 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5098934716000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.858456 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866154 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 145328 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 145328 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 148429 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 148429 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 145328 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 145328 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 148429 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 148429 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 144294 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 144294 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 145328 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 145328 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 135405 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 135405 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 144294 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 144294 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 135405 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 135405 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 144294 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 144294 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1999592000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1999592000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1999592000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 292723 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 292723 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 135405 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 135405 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 1884318500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 1884318500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 1884318500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 280733 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 280733 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 292723 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 292723 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 280733 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 280733 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 292723 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 292723 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492937 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 280733 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 280733 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.482327 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492937 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.482327 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492937 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.482327 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13857.762624 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13916.166316 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13857.762624 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13916.166316 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13857.762624 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13916.166316 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +758,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 36787 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 43317 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 144294 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 144294 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 144294 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 135405 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 135405 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 135405 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1562734500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1562734500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1562734500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1474266000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1474266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1474266000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492937 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.482327 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492937 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.482327 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492937 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.482327 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10830.211235 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10830.211235 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10887.825413 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1661784 # number of replacements -system.cpu.dcache.tagsinuse 511.998465 # Cycle average of tags in use -system.cpu.dcache.total_refs 18023326 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1662296 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.842429 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1651577 # number of replacements +system.cpu.dcache.tagsinuse 511.998478 # Cycle average of tags in use +system.cpu.dcache.total_refs 17702284 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1652089 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.715091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998465 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.998478 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11452816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11452816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6548488 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6548488 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 18001304 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 11207304 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11207304 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6473053 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6473053 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17680357 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18001304 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 18001304 # number of overall hits +system.cpu.dcache.demand_hits::total 17680357 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17680357 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 18001304 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2480783 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2480783 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1873809 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1873809 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4354592 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17680357 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2476228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2476228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1855910 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1855910 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4332138 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4354592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4354592 # number of overall misses +system.cpu.dcache.demand_misses::total 4332138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4332138 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4354592 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 37442770000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63502469838 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 100945239838 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 100945239838 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13933599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13933599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8422297 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8422297 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22355896 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4332138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37330141500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63200421145 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100530562645 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100530562645 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13683532 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13683532 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8328963 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8328963 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22012495 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22355896 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22355896 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22012495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22012495 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22355896 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.178043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222482 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.194785 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22012495 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.180964 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222826 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.196804 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.194785 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.196804 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15093.125840 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15075.405617 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33889.510531 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 34053.602354 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23181.331302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23205.761831 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23181.331302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23205.761831 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1084772653 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6673000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73247 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 392 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14809.789520 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17022.959184 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1081837152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5932000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72874 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 266 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14845.310426 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22300.751880 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1548151 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1110544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1577040 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2687584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2687584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1370239 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296769 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1667008 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1667008 # number of overall MSHR misses +system.cpu.dcache.writebacks 1542574 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1113618 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1561886 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2675504 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2675504 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1362610 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 294024 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1656634 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1656634 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18185435000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9767723153 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27953158153 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27953158153 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86946921000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1385819000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88332740000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098341 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18053047500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9720000152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27773047652 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27773047652 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86987590000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1400743000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88388333000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.099580 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035236 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035301 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074567 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.075259 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.075259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13271.724860 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32913.556177 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16768.460711 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13248.873485 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33058.526352 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency |