diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:32 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:32 -0500 |
| commit | afa897403d72725a6965366647232937e90df5b6 (patch) | |
| tree | 2e1d8af8652e449e0c0117b13014faaa87e0a9a5 /tests/long/10.linux-boot | |
| parent | d6289507d875dede9201bb2c48a889eca1e19900 (diff) | |
| download | gem5-afa897403d72725a6965366647232937e90df5b6.tar.xz | |
ARM: Update stats for default inclusion of CF adapter.
Diffstat (limited to 'tests/long/10.linux-boot')
| -rw-r--r-- | tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 104 | ||||
| -rwxr-xr-x | tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 6 | ||||
| -rw-r--r-- | tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 984 | ||||
| -rw-r--r-- | tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal | bin | 3940 -> 3941 bytes |
4 files changed, 567 insertions, 527 deletions
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 5e6e6c0a7..083bb5627 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -9,7 +9,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 -boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 +boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0 init_param=0 kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 @@ -515,7 +515,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma [system.iocache] type=BaseCache @@ -621,7 +621,7 @@ port=system.membus.port[2] [system.realview] type=RealView -children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -633,23 +633,63 @@ pio_addr=268451840 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[20] +pio=system.iobus.port[21] -[system.realview.cf0_fake] -type=IsaFake -pio_addr=402653184 +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +config_latency=20000 +ctrl_offset=2 +disks= +io_shift=1 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 pio_latency=1000 -pio_size=4095 platform=system.realview -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 system=system -update_data=false -warn_access= -pio=system.iobus.port[24] +config=system.iobus.port[26] +dma=system.iobus.port[27] +pio=system.iobus.port[8] [system.realview.clcd] type=Pl111 @@ -664,7 +704,7 @@ pio_latency=10000 platform=system.realview system=system vnc=system.vncserver -dma=system.iobus.port[26] +dma=system.iobus.port[28] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -675,7 +715,7 @@ pio_addr=268632064 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[8] +pio=system.iobus.port[9] [system.realview.flash_fake] type=IsaFake @@ -691,7 +731,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.port[23] +pio=system.iobus.port[24] [system.realview.gic] type=Gic @@ -712,7 +752,7 @@ pio_addr=268513280 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[15] +pio=system.iobus.port[16] [system.realview.gpio1_fake] type=AmbaFake @@ -722,7 +762,7 @@ pio_addr=268517376 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[16] +pio=system.iobus.port[17] [system.realview.gpio2_fake] type=AmbaFake @@ -732,7 +772,7 @@ pio_addr=268521472 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[17] +pio=system.iobus.port[18] [system.realview.kmi0] type=Pl050 @@ -786,7 +826,7 @@ pio_addr=268455936 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[21] +pio=system.iobus.port[22] [system.realview.realview_io] type=RealViewCtrl @@ -805,7 +845,7 @@ pio_addr=268529664 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[22] +pio=system.iobus.port[23] [system.realview.sci_fake] type=AmbaFake @@ -815,7 +855,7 @@ pio_addr=268492800 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[19] +pio=system.iobus.port[20] [system.realview.smc_fake] type=AmbaFake @@ -825,7 +865,7 @@ pio_addr=269357056 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[12] +pio=system.iobus.port[13] [system.realview.sp810_fake] type=AmbaFake @@ -835,7 +875,7 @@ pio_addr=268439552 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[13] +pio=system.iobus.port[14] [system.realview.ssp_fake] type=AmbaFake @@ -845,7 +885,7 @@ pio_addr=268488704 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[18] +pio=system.iobus.port[19] [system.realview.timer0] type=Sp804 @@ -896,7 +936,7 @@ pio_addr=268476416 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[9] +pio=system.iobus.port[10] [system.realview.uart2_fake] type=AmbaFake @@ -906,7 +946,7 @@ pio_addr=268480512 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[10] +pio=system.iobus.port[11] [system.realview.uart3_fake] type=AmbaFake @@ -916,7 +956,7 @@ pio_addr=268484608 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[11] +pio=system.iobus.port[12] [system.realview.watchdog_fake] type=AmbaFake @@ -926,7 +966,7 @@ pio_addr=268500992 pio_latency=1000 platform=system.realview system=system -pio=system.iobus.port[14] +pio=system.iobus.port[15] [system.terminal] type=Terminal diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index b0b26bf8a..83f702085 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 31 2011 10:39:48 -M5 started Mar 31 2011 10:41:48 +M5 compiled Apr 4 2011 11:17:23 +M5 started Apr 4 2011 11:17:27 M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 82667402500 because m5_exit instruction encountered +Exiting @ tick 82662490500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 22329b251..edd79728c 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,389 +1,389 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 90803 # Simulator instruction rate (inst/s) -host_mem_usage 385116 # Number of bytes of host memory used -host_seconds 572.31 # Real time elapsed on the host -host_tick_rate 144444192 # Simulator tick rate (ticks/s) +host_inst_rate 92348 # Simulator instruction rate (inst/s) +host_mem_usage 389996 # Number of bytes of host memory used +host_seconds 562.86 # Real time elapsed on the host +host_tick_rate 146862568 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51967991 # Number of instructions simulated -sim_seconds 0.082667 # Number of seconds simulated -sim_ticks 82667402500 # Number of ticks simulated +sim_insts 51978682 # Number of instructions simulated +sim_seconds 0.082662 # Number of seconds simulated +sim_ticks 82662490500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 9197470 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 11720402 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 155471 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 664024 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11242806 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 13225964 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 787685 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8444335 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 800394 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 9175263 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 11695749 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 155381 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 665245 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11246732 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 13229511 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 787550 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8445621 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 801383 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 93520933 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.557000 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.350737 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 93507712 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.557193 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.351787 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 71862945 76.84% 76.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10613514 11.35% 88.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 3470472 3.71% 91.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 1669950 1.79% 93.69% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 3525302 3.77% 97.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 743125 0.79% 98.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 539739 0.58% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 295492 0.32% 99.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 800394 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 71892468 76.88% 76.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10568988 11.30% 88.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 3427833 3.67% 91.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 1711600 1.83% 93.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 3527395 3.77% 97.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 741726 0.79% 98.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 541099 0.58% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 295220 0.32% 99.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 801383 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 93520933 # Number of insts commited each cycle -system.cpu.commit.COM:count 52091171 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 93507712 # Number of insts commited each cycle +system.cpu.commit.COM:count 52101862 # Number of instructions committed system.cpu.commit.COM:fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.COM:function_calls 529543 # Number of function calls committed. -system.cpu.commit.COM:int_insts 42499828 # Number of committed integer instructions. -system.cpu.commit.COM:loads 9204456 # Number of loads committed +system.cpu.commit.COM:function_calls 529734 # Number of function calls committed. +system.cpu.commit.COM:int_insts 42509491 # Number of committed integer instructions. +system.cpu.commit.COM:loads 9207015 # Number of loads committed system.cpu.commit.COM:membars 3 # Number of memory barriers committed -system.cpu.commit.COM:refs 16289486 # Number of memory references committed +system.cpu.commit.COM:refs 16293738 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 640570 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 52091171 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 2963049 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 16156603 # The number of squashed insts skipped by commit -system.cpu.committedInsts 51967991 # Number of Instructions Simulated -system.cpu.committedInsts_total 51967991 # Number of Instructions Simulated -system.cpu.cpi 3.181474 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.181474 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 111599 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 111599 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14959.817352 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 641726 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 52101862 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 2963383 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 16147201 # The number of squashed insts skipped by commit +system.cpu.committedInsts 51978682 # Number of Instructions Simulated +system.cpu.committedInsts_total 51978682 # Number of Instructions Simulated +system.cpu.cpi 3.180631 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.180631 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 111504 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 111504 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14941.207869 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11849.393291 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 105029 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 105029 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 98286000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058871 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 6570 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6570 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 966 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66404000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050216 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11805.277281 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 104947 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 104947 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 97969500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058805 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 6557 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6557 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 967 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65991500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050133 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5604 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9424637 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9424637 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 14817.536812 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5590 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9423338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9423338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 14823.280125 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13267.620751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13267.626376 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 8938243 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8938243 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 7207161000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_hits::0 8937009 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8937009 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7208991000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate::0 0.051609 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 486394 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 486394 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 237639 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3300387000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 486329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 486329 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 237469 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3301781500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026409 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248755 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38192917500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 105021 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 105021 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 105021 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 105021 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6670926 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6670926 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 39939.840777 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 248860 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38194393000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 105004 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 105004 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 105004 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 105004 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6672578 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6672578 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 39930.375248 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38522.323685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38504.296551 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4625068 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4625068 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 81711242773 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.306683 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2045858 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2045858 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1875300 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6570290483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_hits::0 4626571 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4626571 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 81697827271 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.306629 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2046007 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2046007 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1875409 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 6568755983 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025567 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 170558 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 939960187 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7470.310989 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21040 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.551220 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 910 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 6797983 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 526000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 170598 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 940173192 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7672.355023 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21291.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 32.542596 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 876 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 6720983 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 511000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 16095563 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 16095916 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16095563 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 35114.358197 # average overall miss latency +system.cpu.dcache.demand_accesses::total 16095916 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 35108.618395 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23540.117962 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13563311 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23531.646751 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 13563580 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563311 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 88918403773 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.157326 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 13563580 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 88906818271 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.157328 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 2532252 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 2532336 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2532252 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2112939 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9870677483 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.026051 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 2532336 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2112878 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9870537483 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 419313 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 419458 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999513 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.750780 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 16095563 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.750765 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 16095916 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16095563 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 35114.358197 # average overall miss latency +system.cpu.dcache.overall_accesses::total 16095916 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 35108.618395 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23540.117962 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23531.646751 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13563311 # number of overall hits +system.cpu.dcache.overall_hits::0 13563580 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13563311 # number of overall hits -system.cpu.dcache.overall_miss_latency 88918403773 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.157326 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 13563580 # number of overall hits +system.cpu.dcache.overall_miss_latency 88906818271 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.157328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 2532252 # number of overall misses +system.cpu.dcache.overall_misses::0 2532336 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2532252 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2112939 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9870677483 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.026051 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 2532336 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2112878 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9870537483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 419313 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39132877687 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 419458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39134566192 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 422673 # number of replacements -system.cpu.dcache.sampled_refs 423185 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 422792 # number of replacements +system.cpu.dcache.sampled_refs 423304 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.750780 # Cycle average of tags in use -system.cpu.dcache.total_refs 13775188 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.750765 # Cycle average of tags in use +system.cpu.dcache.total_refs 13775411 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 48224000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 391306 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 53936427 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 70459 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 1223835 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 76423626 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 23928576 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14469727 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2568818 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 235907 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1186175 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 35245643 # DTB accesses -system.cpu.dtb.align_faults 1502 # Number of TLB faults due to alignment restrictions +system.cpu.dcache.writebacks 391506 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 53936622 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 70601 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 1224137 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 76419738 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 23948605 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14435253 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2568567 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 235986 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1187204 # Number of cycles decode is unblocking +system.cpu.dtb.accesses 35246983 # DTB accesses +system.cpu.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2802 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2766 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 35173393 # DTB hits +system.cpu.dtb.hits 35174002 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 72250 # DTB misses -system.cpu.dtb.perms_faults 1115 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 1019 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 27745512 # DTB read accesses -system.cpu.dtb.read_hits 27683911 # DTB read hits -system.cpu.dtb.read_misses 61601 # DTB read misses -system.cpu.dtb.write_accesses 7500131 # DTB write accesses -system.cpu.dtb.write_hits 7489482 # DTB write hits -system.cpu.dtb.write_misses 10649 # DTB write misses -system.cpu.fetch.Branches 13225964 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 6550605 # Number of cache lines fetched -system.cpu.fetch.Cycles 16044931 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 257300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 64080161 # Number of instructions fetch has processed -system.cpu.fetch.ItlbSquashes 3986 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.MiscStallCycles 17407 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1041050 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 7083 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.branchRate 0.079995 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 6549214 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9985155 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.387578 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 96089723 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.820891 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.076577 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.misses 72981 # DTB misses +system.cpu.dtb.perms_faults 1114 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 1061 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 27744902 # DTB read accesses +system.cpu.dtb.read_hits 27682402 # DTB read hits +system.cpu.dtb.read_misses 62500 # DTB read misses +system.cpu.dtb.write_accesses 7502081 # DTB write accesses +system.cpu.dtb.write_hits 7491600 # DTB write hits +system.cpu.dtb.write_misses 10481 # DTB write misses +system.cpu.fetch.Branches 13229511 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6553650 # Number of cache lines fetched +system.cpu.fetch.Cycles 16012029 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 257276 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 64080399 # Number of instructions fetch has processed +system.cpu.fetch.ItlbSquashes 4041 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.MiscStallCycles 17184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 1041966 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 7137 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.branchRate 0.080021 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 6552269 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9962813 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.387603 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 96076251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.821047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.076929 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 80061400 83.32% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1246898 1.30% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1750624 1.82% 86.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1251283 1.30% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4759856 4.95% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 798226 0.83% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 841539 0.88% 94.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 741758 0.77% 95.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4638139 4.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 80080684 83.35% 83.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1206606 1.26% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1754286 1.83% 86.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1219002 1.27% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4793265 4.99% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 802218 0.83% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 845287 0.88% 94.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744134 0.77% 95.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4630769 4.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 96089723 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 5467 # number of floating regfile reads -system.cpu.fp_regfile_writes 1929 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 6550512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6550512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14752.246405 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 96076251 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 5420 # number of floating regfile reads +system.cpu.fp_regfile_writes 1898 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses::0 6553557 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6553557 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14743.844575 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12017.726532 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12014.286786 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 6004197 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6004197 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8059373495 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.083400 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 546315 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 546315 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 44384 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6032069496 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076625 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 6005950 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6005950 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8073832496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.083559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 547607 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 547607 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 44625 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6042969996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.076749 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 501931 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 502982 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 4957500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.avg_blocked_cycles::no_mshrs 6823.818182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7957.783133 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11.962625 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 88 # number of cycles access was blocked +system.cpu.icache.avg_refs 11.941659 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 600496 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 660496 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 6550512 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 6553557 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6550512 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14752.246405 # average overall miss latency +system.cpu.icache.demand_accesses::total 6553557 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14743.844575 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12017.726532 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 6004197 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 12014.286786 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 6005950 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6004197 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8059373495 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.083400 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 6005950 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8073832496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.083559 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 546315 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 547607 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 546315 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 44384 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6032069496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.076625 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 547607 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 44625 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6042969996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.076749 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 501931 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 502982 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.970187 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 496.735661 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 6550512 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.970025 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 496.652768 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 6553557 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6550512 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14752.246405 # average overall miss latency +system.cpu.icache.overall_accesses::total 6553557 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14743.844575 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12017.726532 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12014.286786 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 6004197 # number of overall hits +system.cpu.icache.overall_hits::0 6005950 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 6004197 # number of overall hits -system.cpu.icache.overall_miss_latency 8059373495 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.083400 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 6005950 # number of overall hits +system.cpu.icache.overall_miss_latency 8073832496 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.083559 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 546315 # number of overall misses +system.cpu.icache.overall_misses::0 547607 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 546315 # number of overall misses -system.cpu.icache.overall_mshr_hits 44384 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6032069496 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.076625 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 547607 # number of overall misses +system.cpu.icache.overall_mshr_hits 44625 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6042969996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.076749 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 501931 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 502982 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 4957500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 501401 # number of replacements -system.cpu.icache.sampled_refs 501913 # Sample count of references to valid blocks. +system.cpu.icache.replacements 502429 # number of replacements +system.cpu.icache.sampled_refs 502941 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 496.735661 # Cycle average of tags in use -system.cpu.icache.total_refs 6004197 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 6211908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 41188 # number of writebacks -system.cpu.idleCycles 69245083 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 10229161 # Number of branches executed -system.cpu.iew.EXEC:nop 166597 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.475852 # Inst execution rate -system.cpu.iew.EXEC:refs 35984402 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7799191 # Number of stores executed +system.cpu.icache.tagsinuse 496.652768 # Cycle average of tags in use +system.cpu.icache.total_refs 6005950 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 6210686000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 41369 # number of writebacks +system.cpu.idleCycles 69248731 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 10230019 # Number of branches executed +system.cpu.iew.EXEC:nop 166886 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.475904 # Inst execution rate +system.cpu.iew.EXEC:refs 35985354 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7801149 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 62355336 # num instructions consuming a value -system.cpu.iew.WB:count 60877824 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.509736 # average fanout of values written-back +system.cpu.iew.WB:consumers 62345618 # num instructions consuming a value +system.cpu.iew.WB:count 60884415 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.509768 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 31784768 # num instructions producing a value -system.cpu.iew.WB:rate 0.368209 # insts written-back per cycle -system.cpu.iew.WB:sent 78147343 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 710642 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 21410172 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 12850597 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4002212 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 353192 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 8736302 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 70500878 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 28185211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1060546 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 78674830 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 31781773 # num instructions producing a value +system.cpu.iew.WB:rate 0.368271 # insts written-back per cycle +system.cpu.iew.WB:sent 78152559 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 711242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 21406073 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 12848037 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4002488 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 354669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8736360 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 70502341 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 28184205 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1059977 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 78678877 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28556 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 45532 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2568818 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 264100 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 45641 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2568567 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 263948 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8285 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 330904 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 7460 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 8235 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 331109 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7560 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 280975 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17000760 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 3646141 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1651272 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 280975 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 187196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 523446 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 182828391 # number of integer regfile reads -system.cpu.int_regfile_writes 43909645 # number of integer regfile writes -system.cpu.ipc 0.314320 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.314320 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2392951 3.00% 3.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 40765047 51.13% 54.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 71833 0.09% 54.22% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 280540 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17000484 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 3641022 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1649637 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 280540 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 186102 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 525140 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 182840055 # number of integer regfile reads +system.cpu.int_regfile_writes 43911822 # number of integer regfile writes +system.cpu.ipc 0.314403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.314403 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2393207 3.00% 3.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 40767716 51.13% 54.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 71906 0.09% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 54.22% # Type of FU issued @@ -394,111 +394,111 @@ system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.22% # Ty system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 1 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 11 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 10 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 2 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 9 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 6 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 880 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 895 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 10 0.00% 54.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 6 0.00% 54.22% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 54.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 28539771 35.79% 90.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7964861 9.99% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 28538408 35.79% 90.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7966700 9.99% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 79735376 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4820944 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.060462 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 79738854 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4821847 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.060470 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 4959 0.10% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 4503516 93.42% 93.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 312469 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5252 0.11% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4503965 93.41% 93.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 312629 6.48% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 96089723 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.829801 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.378962 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 96076251 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.829954 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.379344 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 59895094 62.33% 62.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 16672825 17.35% 79.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 7219542 7.51% 87.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4124127 4.29% 91.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5945369 6.19% 97.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1307408 1.36% 99.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 617440 0.64% 99.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 235414 0.24% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 72504 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 59918658 62.37% 62.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 16598524 17.28% 79.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 7253913 7.55% 87.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 4126106 4.29% 91.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5947858 6.19% 97.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1304063 1.36% 99.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 619735 0.65% 99.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 235123 0.24% 99.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 72271 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 96089723 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.482266 # Inst issue rate -system.cpu.iq.fp_alu_accesses 8546 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 16333 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6331 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 9298 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 82154823 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 260564966 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 60871493 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 88267100 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 66302141 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 79735376 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4032140 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 17675893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 127840 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1069091 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 22304285 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 6563470 # DTB accesses +system.cpu.iq.ISSUE:issued_per_cycle::total 96076251 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.482316 # Inst issue rate +system.cpu.iq.fp_alu_accesses 8555 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 16356 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 6330 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 9324 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 82158939 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 260560114 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 60878085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 88252468 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 66303042 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 79738854 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4032413 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 17660461 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 127886 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1069030 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 22275203 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 6566505 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 1619 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1618 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 6556387 # DTB hits -system.cpu.itb.inst_accesses 6563470 # ITB inst accesses -system.cpu.itb.inst_hits 6556387 # ITB inst hits -system.cpu.itb.inst_misses 7083 # ITB inst misses -system.cpu.itb.misses 7083 # DTB misses -system.cpu.itb.perms_faults 5304 # Number of TLB faults due to permissions restrictions +system.cpu.itb.hits 6559368 # DTB hits +system.cpu.itb.inst_accesses 6566505 # ITB inst accesses +system.cpu.itb.inst_hits 6559368 # ITB inst hits +system.cpu.itb.inst_misses 7137 # ITB inst misses +system.cpu.itb.misses 7137 # DTB misses +system.cpu.itb.perms_faults 5235 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits @@ -508,37 +508,37 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.memDep0.conflictingLoads 3483 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10121 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 12850597 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8736302 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 84311208 # number of misc regfile reads -system.cpu.misc_regfile_writes 505887 # number of misc regfile writes -system.cpu.numCycles 165334806 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 3427 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9862 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 12848037 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8736360 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 84327441 # number of misc regfile reads +system.cpu.misc_regfile_writes 505947 # number of misc regfile writes +system.cpu.numCycles 165324982 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 33117946 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 36733346 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 775449 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 25568402 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2466412 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 439285 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 190546876 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 73646302 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 53333432 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13047340 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2568818 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5448397 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 16600085 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 49406 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 190497470 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 16338820 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 812667 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 14273675 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 662897 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 160028013 # The number of ROB reads -system.cpu.rob.rob_writes 139108925 # The number of ROB writes -system.cpu.timesIdled 1092643 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 33112132 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 36741742 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 775024 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 25585942 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2464411 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 439406 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 190546426 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 73652077 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 53332963 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13017560 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2568567 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5444932 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 16591220 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 49319 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 190497107 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 16347118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 812559 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 14268469 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 662925 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 160015001 # The number of ROB reads +system.cpu.rob.rob_writes 139111158 # The number of ROB writes +system.cpu.timesIdled 1092841 # Number of times that the entire CPU went into an idle state and unscheduled itself system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -606,141 +606,141 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 168856 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168856 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52453.278430 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 168878 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168878 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52453.870744 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40012.348538 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 60908 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60908 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5662226500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.639290 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107948 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107948 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4319253000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.639290 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40012.272411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 60953 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60953 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5661084000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.639071 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107925 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107925 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4318324500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.639071 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107948 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 753810 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 101430 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 855240 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52702.508435 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 6230167.630058 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 6282870.138493 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40041.091563 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 107925 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 754907 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 102462 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 857369 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52723.366686 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5971800 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 6024523.366686 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40042.738791 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 733359 # number of ReadReq hits -system.l2c.ReadReq_hits::1 101257 # number of ReadReq hits -system.l2c.ReadReq_hits::total 834616 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 1077819000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.027130 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.001706 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028836 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 20451 # number of ReadReq misses -system.l2c.ReadReq_misses::1 173 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20624 # number of ReadReq misses +system.l2c.ReadReq_hits::0 734519 # number of ReadReq hits +system.l2c.ReadReq_hits::1 102282 # number of ReadReq hits +system.l2c.ReadReq_hits::total 836801 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 1074924000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.027007 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.001757 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028764 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 20388 # number of ReadReq misses +system.l2c.ReadReq_misses::1 180 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20568 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 823885500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.202859 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.230155 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 20576 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 28941115500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1732 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1732 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 396.713615 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_miss_latency 821677000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027182 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.200269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.227452 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 20520 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 28942557500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1743 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1743 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 399.055490 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::0 49 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.983834 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1704 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1704 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 68160000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.983834 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.971888 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1694 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1694 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 67760000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.971888 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1704 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1694 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 745824450 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 432494 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 432494 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 432494 # number of Writeback hits -system.l2c.Writeback_hits::total 432494 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 745944450 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 432875 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 432875 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 432875 # number of Writeback hits +system.l2c.Writeback_hits::total 432875 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 8.116644 # Average number of references to valid blocks. +system.l2c.avg_refs 8.172694 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 922666 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 101430 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1024096 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52492.975023 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 38959800.578035 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 39012293.553058 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40016.950142 # average overall mshr miss latency -system.l2c.demand_hits::0 794267 # number of demand (read+write) hits -system.l2c.demand_hits::1 101257 # number of demand (read+write) hits -system.l2c.demand_hits::total 895524 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6740045500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.139161 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.001706 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.140866 # miss rate for demand accesses -system.l2c.demand_misses::0 128399 # number of demand (read+write) misses -system.l2c.demand_misses::1 173 # number of demand (read+write) misses -system.l2c.demand_misses::total 128572 # number of demand (read+write) misses +system.l2c.demand_accesses::0 923785 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 102462 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1026247 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52496.691684 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 37422266.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 37474763.358350 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40017.139632 # average overall mshr miss latency +system.l2c.demand_hits::0 795472 # number of demand (read+write) hits +system.l2c.demand_hits::1 102282 # number of demand (read+write) hits +system.l2c.demand_hits::total 897754 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6736008000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.138899 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.001757 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.140656 # miss rate for demand accesses +system.l2c.demand_misses::0 128313 # number of demand (read+write) misses +system.l2c.demand_misses::1 180 # number of demand (read+write) misses +system.l2c.demand_misses::total 128493 # number of demand (read+write) misses system.l2c.demand_mshr_hits 48 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5143138500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.139296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.267120 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.406417 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 128524 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5140001500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.139042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.253587 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.392629 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 128445 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.099484 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.481769 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 6519.756785 # Average occupied blocks per context -system.l2c.occ_blocks::1 31573.183682 # Average occupied blocks per context -system.l2c.overall_accesses::0 922666 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 101430 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1024096 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52492.975023 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 38959800.578035 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 39012293.553058 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40016.950142 # average overall mshr miss latency +system.l2c.occ_%::0 0.099470 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.481649 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 6518.840874 # Average occupied blocks per context +system.l2c.occ_blocks::1 31565.358061 # Average occupied blocks per context +system.l2c.overall_accesses::0 923785 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 102462 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1026247 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52496.691684 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 37422266.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 37474763.358350 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40017.139632 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 794267 # number of overall hits -system.l2c.overall_hits::1 101257 # number of overall hits -system.l2c.overall_hits::total 895524 # number of overall hits -system.l2c.overall_miss_latency 6740045500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.139161 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.001706 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.140866 # miss rate for overall accesses -system.l2c.overall_misses::0 128399 # number of overall misses -system.l2c.overall_misses::1 173 # number of overall misses -system.l2c.overall_misses::total 128572 # number of overall misses +system.l2c.overall_hits::0 795472 # number of overall hits +system.l2c.overall_hits::1 102282 # number of overall hits +system.l2c.overall_hits::total 897754 # number of overall hits +system.l2c.overall_miss_latency 6736008000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.138899 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.001757 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.140656 # miss rate for overall accesses +system.l2c.overall_misses::0 128313 # number of overall misses +system.l2c.overall_misses::1 180 # number of overall misses +system.l2c.overall_misses::total 128493 # number of overall misses system.l2c.overall_mshr_hits 48 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5143138500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.139296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.267120 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.406417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 128524 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29686939950 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5140001500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.139042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.253587 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.392629 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 128445 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29688501950 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94736 # number of replacements -system.l2c.sampled_refs 127028 # Sample count of references to valid blocks. +system.l2c.replacements 94647 # number of replacements +system.l2c.sampled_refs 126947 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 38092.940467 # Cycle average of tags in use -system.l2c.total_refs 1031041 # Total number of references to valid blocks. +system.l2c.tagsinuse 38084.198936 # Cycle average of tags in use +system.l2c.total_refs 1037499 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87630 # number of writebacks +system.l2c.writebacks 87563 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 855723281..3d9759fde 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal |