diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-12-07 16:19:57 -0800 |
| commit | 1cfe2c88204aed6310fa8be9a310350cb06f6026 (patch) | |
| tree | dec3bca4f85b5cfcb13eefc118a5ae7cdcaf17ab /tests/long/10.linux-boot | |
| parent | e681c0f7b30f521805ebec04271435306f4c56ed (diff) | |
| download | gem5-1cfe2c88204aed6310fa8be9a310350cb06f6026.tar.xz | |
Stats: Fix stats for cumulative flags change.
Diffstat (limited to 'tests/long/10.linux-boot')
4 files changed, 1402 insertions, 1402 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 0e093f087..1cdc4de6d 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 14 2010 23:49:18 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 14 2010 23:51:27 +M5 compiled Dec 1 2010 12:54:21 +M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase +M5 started Dec 3 2010 12:06:07 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 118370500 -Exiting @ tick 1900844230500 because m5_exit instruction encountered +Exiting @ tick 1900831708500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 498607f9c..39fd478e5 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,393 +1,393 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136464 # Simulator instruction rate (inst/s) -host_mem_usage 294032 # Number of bytes of host memory used -host_seconds 417.62 # Real time elapsed on the host -host_tick_rate 4551611662 # Simulator tick rate (ticks/s) +host_inst_rate 160492 # Simulator instruction rate (inst/s) +host_mem_usage 293848 # Number of bytes of host memory used +host_seconds 355.10 # Real time elapsed on the host +host_tick_rate 5352987788 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56990237 # Number of instructions simulated -sim_seconds 1.900844 # Number of seconds simulated -sim_ticks 1900844230500 # Number of ticks simulated +sim_insts 56990213 # Number of instructions simulated +sim_seconds 1.900832 # Number of seconds simulated +sim_ticks 1900831708500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5873671 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11166529 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27790 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 685267 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10432996 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12491450 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 879904 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7524834 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 923111 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5880494 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11174244 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27800 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 685606 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10433425 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12492393 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 880061 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7524876 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 920219 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 78256773 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.636207 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.403151 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 78262011 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.636166 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.402915 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 56995845 72.83% 72.83% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9310416 11.90% 84.73% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5430205 6.94% 91.67% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2440245 3.12% 94.79% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1860572 2.38% 97.16% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 630930 0.81% 97.97% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 344016 0.44% 98.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 321433 0.41% 98.82% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 923111 1.18% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 56998112 72.83% 72.83% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9312532 11.90% 84.73% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5431102 6.94% 91.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2441098 3.12% 94.79% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1859715 2.38% 97.16% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 630504 0.81% 97.97% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 344653 0.44% 98.41% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 324076 0.41% 98.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 920219 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 78256773 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49787514 # Number of instructions committed -system.cpu0.commit.COM:loads 7895784 # Number of loads committed +system.cpu0.commit.COM:committed_per_cycle::total 78262011 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49787612 # Number of instructions committed +system.cpu0.commit.COM:loads 7895841 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13320151 # Number of memory references committed +system.cpu0.commit.COM:refs 13320204 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 652659 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49787514 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 564772 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7271893 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46926700 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46926700 # Number of Instructions Simulated -system.cpu0.cpi 2.403270 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403270 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 178277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 178277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14385.010585 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 652972 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49787612 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 564765 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7275284 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46926792 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46926792 # Number of Instructions Simulated +system.cpu0.cpi 2.403365 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403365 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 178266 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 178266 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.082008 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10557.129525 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 158910 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158910 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 278594500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108634 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 19367 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19367 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10555.240699 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 158902 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158902 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 278514000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108624 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 19364 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19364 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_mshr_hits 4366 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158367500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084144 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158307500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084133 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15001 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8018710 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8018710 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.163525 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 14998 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8019167 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8019167 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.581419 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.972926 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.536326 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6640866 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6640866 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32726776000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.171829 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1377844 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1377844 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 392731 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23413154000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122852 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6641537 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6641537 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 32725024000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.171792 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1377630 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1377630 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 392532 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23413352500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122843 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 985113 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920830500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13300.547196 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 985098 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920862000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 185115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13269.357045 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10297.264022 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 181459 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 181459 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 48613500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019745 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10269.978106 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 181460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 181460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 48499500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019744 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_misses::0 3655 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 3655 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37636500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019745 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37526500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019739 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 3655 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5224193 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5224193 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32390.296487 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 3654 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5224194 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5224194 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32391.467747 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30580.318877 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30578.461362 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3607335 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3607335 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 52370509997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.309494 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1616858 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1616858 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1353465 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641930 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050418 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3607293 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3607293 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 52373796592 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.309502 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1616901 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1616901 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1353492 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641929 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050421 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 263393 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320665498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8775.921635 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 263409 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320645998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8778.099961 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.499931 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 83634 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 8.500462 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 83583 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 733965430 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 733699929 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13242903 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13243361 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13242903 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28415.944557 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13243361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28418.079690 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.360996 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10248201 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10248830 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10248201 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 85097285997 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.226136 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10248830 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 85098820592 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.226116 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2994702 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2994531 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2994702 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1746196 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 31467795930 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.094277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2994531 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1746024 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 31467994429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.094274 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1248506 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1248507 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.occ_%::0 0.973616 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 498.491480 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 498.491430 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13242903 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::0 13243361 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13242903 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28415.944557 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13243361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28418.079690 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.360996 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10248201 # number of overall hits +system.cpu0.dcache.overall_hits::0 10248830 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10248201 # number of overall hits -system.cpu0.dcache.overall_miss_latency 85097285997 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.226136 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10248830 # number of overall hits +system.cpu0.dcache.overall_miss_latency 85098820592 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.226116 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2994702 # number of overall misses +system.cpu0.dcache.overall_misses::0 2994531 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2994702 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1746196 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 31467795930 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.094277 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2994531 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1746024 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 31467994429 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.094274 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1248506 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2241495998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1248507 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2241507998 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1246705 # number of replacements -system.cpu0.dcache.sampled_refs 1247217 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1246700 # number of replacements +system.cpu0.dcache.sampled_refs 1247212 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.491481 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10601259 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.491430 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10601878 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 721554 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33796856 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33338 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 520908 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 62600964 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32174872 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11303760 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1270160 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100637 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 981284 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 794683 # DTB accesses -system.cpu0.dtb.data_acv 699 # DTB access violations -system.cpu0.dtb.data_hits 14241389 # DTB hits -system.cpu0.dtb.data_misses 32519 # DTB misses +system.cpu0.decode.DECODE:BlockedCycles 33792520 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33358 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 521061 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 62605463 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32178672 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11309201 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1270716 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100684 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 981617 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 795304 # DTB accesses +system.cpu0.dtb.data_acv 690 # DTB access violations +system.cpu0.dtb.data_hits 14242761 # DTB hits +system.cpu0.dtb.data_misses 32467 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 599310 # DTB read accesses -system.cpu0.dtb.read_acv 523 # DTB read access violations -system.cpu0.dtb.read_hits 8657125 # DTB read hits -system.cpu0.dtb.read_misses 26727 # DTB read misses -system.cpu0.dtb.write_accesses 195373 # DTB write accesses -system.cpu0.dtb.write_acv 176 # DTB write access violations -system.cpu0.dtb.write_hits 5584264 # DTB write hits -system.cpu0.dtb.write_misses 5792 # DTB write misses -system.cpu0.fetch.Branches 12491450 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7791215 # Number of cache lines fetched -system.cpu0.fetch.Cycles 20268333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 374565 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 63688508 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 1103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 745343 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.110762 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7791215 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6753575 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.564727 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 79526933 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.800842 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.104211 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 599691 # DTB read accesses +system.cpu0.dtb.read_acv 517 # DTB read access violations +system.cpu0.dtb.read_hits 8658240 # DTB read hits +system.cpu0.dtb.read_misses 26670 # DTB read misses +system.cpu0.dtb.write_accesses 195613 # DTB write accesses +system.cpu0.dtb.write_acv 173 # DTB write access violations +system.cpu0.dtb.write_hits 5584521 # DTB write hits +system.cpu0.dtb.write_misses 5797 # DTB write misses +system.cpu0.fetch.Branches 12492393 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7792591 # Number of cache lines fetched +system.cpu0.fetch.Cycles 20275777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 374501 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 63694095 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 745780 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.110766 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7792591 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6760555 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.564753 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 79532727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.800854 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.104099 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67079407 84.35% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 896436 1.13% 85.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1772079 2.23% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 811632 1.02% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2745328 3.45% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585266 0.74% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 679619 0.85% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 829666 1.04% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4127500 5.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67079150 84.34% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 900735 1.13% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1776168 2.23% 87.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 808150 1.02% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2746406 3.45% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 585611 0.74% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 679507 0.85% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 830147 1.04% 94.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4126853 5.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79526933 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 7791215 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7791215 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.927393 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 79532727 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 7792591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7792591 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.531748 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.913224 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6933667 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6933667 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12921471000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.110066 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 857548 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 857548 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 36674 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9865192500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105359 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.722051 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6935061 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6935061 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12920860500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.110044 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 857530 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 857530 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 36660 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9864987500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105340 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 820874 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12107.843137 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 820870 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11583.333333 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.447903 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 51 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.449643 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 54 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 617500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 625500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7791215 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7792591 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7791215 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15067.927393 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7792591 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15067.531748 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12017.913224 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6933667 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12017.722051 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6935061 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6933667 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12921471000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.110066 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6935061 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12920860500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.110044 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 857548 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 857530 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 857548 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 36674 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9865192500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.105359 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 857530 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 36660 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9864987500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.105340 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 820874 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 820870 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.861243 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7791215 # number of overall (read+write) accesses +system.cpu0.icache.occ_blocks::0 509.861229 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7792591 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7791215 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15067.927393 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7792591 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15067.531748 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12017.913224 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12017.722051 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6933667 # number of overall hits +system.cpu0.icache.overall_hits::0 6935061 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6933667 # number of overall hits -system.cpu0.icache.overall_miss_latency 12921471000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.110066 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6935061 # number of overall hits +system.cpu0.icache.overall_miss_latency 12920860500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.110044 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 857548 # number of overall misses +system.cpu0.icache.overall_misses::0 857530 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 857548 # number of overall misses -system.cpu0.icache.overall_mshr_hits 36674 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9865192500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.105359 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 857530 # number of overall misses +system.cpu0.icache.overall_mshr_hits 36660 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9864987500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.105340 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 820874 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 820870 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 820245 # number of replacements -system.cpu0.icache.sampled_refs 820756 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 820241 # number of replacements +system.cpu0.icache.sampled_refs 820752 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.861243 # Cycle average of tags in use -system.cpu0.icache.total_refs 6933667 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 509.861229 # Cycle average of tags in use +system.cpu0.icache.total_refs 6935061 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 109 # number of writebacks -system.cpu0.idleCycles 33250612 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8091553 # Number of branches executed -system.cpu0.iew.EXEC:nop 3189610 # number of nop insts executed +system.cpu0.idleCycles 33249487 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8091689 # Number of branches executed +system.cpu0.iew.EXEC:nop 3189515 # number of nop insts executed system.cpu0.iew.EXEC:rate 0.446670 # Inst execution rate -system.cpu0.iew.EXEC:refs 14308443 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5602810 # Number of stores executed +system.cpu0.iew.EXEC:refs 14309755 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5603066 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31619553 # num instructions consuming a value -system.cpu0.iew.WB:count 49998381 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.757763 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31608779 # num instructions consuming a value +system.cpu0.iew.WB:count 49999865 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.758055 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23960113 # num instructions producing a value -system.cpu0.iew.WB:rate 0.443336 # insts written-back per cycle -system.cpu0.iew.WB:sent 50080785 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 711622 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9015836 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9134167 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1511990 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 755493 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5841972 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57170075 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8705633 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 463276 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50374391 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 59438 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23961182 # num instructions producing a value +system.cpu0.iew.WB:rate 0.443331 # insts written-back per cycle +system.cpu0.iew.WB:sent 50082132 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 711844 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9016513 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9135520 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1511943 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 755935 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5842466 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57173513 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8706689 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 463253 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50376392 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 59411 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 6976 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1270160 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 547257 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 6975 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1270716 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 547260 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 121631 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 411302 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 10774 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 122212 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 411295 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 10786 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 38966 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18610 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1238383 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 417605 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 38966 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 331944 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 379678 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.416100 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416100 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.memOrderViolation 39006 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18611 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1239679 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 418103 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 39006 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 331745 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 380099 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.416083 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416083 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35331602 69.50% 69.51% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 55961 0.11% 69.62% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.62% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35332190 69.50% 69.50% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 55947 0.11% 69.61% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.64% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.65% # Type of FU issued @@ -410,80 +410,80 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9004352 17.71% 87.36% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645593 11.11% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779196 1.53% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9005421 17.71% 87.36% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645944 11.11% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779180 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 50837669 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 379948 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 50839647 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 380083 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 41291 10.87% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.87% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 225058 59.23% 70.10% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 113599 29.90% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 41221 10.85% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.85% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 225189 59.25% 70.09% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 113673 29.91% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 79526933 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639251 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210486 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 79532727 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639229 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210023 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 54768546 68.87% 68.87% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12090793 15.20% 84.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5440746 6.84% 90.91% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3421929 4.30% 95.22% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2219727 2.79% 98.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 991235 1.25% 99.25% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 436578 0.55% 99.80% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 113986 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 43393 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 54768244 68.86% 68.86% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12092577 15.20% 84.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5445890 6.85% 90.91% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3420529 4.30% 95.22% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2219923 2.79% 98.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 995680 1.25% 99.26% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 437086 0.55% 99.81% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 109289 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 43509 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 79526933 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.450778 # Inst issue rate -system.cpu0.iq.iqInstsAdded 52258300 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 50837669 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1722165 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6733244 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24149 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1157393 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3421850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 79532727 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.450777 # Inst issue rate +system.cpu0.iq.iqInstsAdded 52261894 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 50839647 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1722104 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6736109 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24176 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1157339 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3425002 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 951504 # ITB accesses -system.cpu0.itb.fetch_acv 721 # ITB acv -system.cpu0.itb.fetch_hits 922631 # ITB hits -system.cpu0.itb.fetch_misses 28873 # ITB misses +system.cpu0.itb.fetch_accesses 951977 # ITB accesses +system.cpu0.itb.fetch_acv 722 # ITB acv +system.cpu0.itb.fetch_hits 923088 # ITB hits +system.cpu0.itb.fetch_misses 28889 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -500,7 +500,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # nu system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed +system.cpu0.kern.callpal::swpipl 147043 90.75% 93.03% # number of callpals executed system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed @@ -509,45 +509,45 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.96% # nu system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 162037 # number of callpals executed +system.cpu0.kern.callpal::total 162035 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 176107 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 176106 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6625 # number of quiesce instructions executed system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 89357 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 153911 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862714429000 97.99% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96239500 0.01% 98.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398463500 0.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 103371000 0.01% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37530876000 1.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900843379000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862701571500 97.99% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96288500 0.01% 98.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398425500 0.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 103369500 0.01% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37531203000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900830858000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 +system.cpu0.kern.ipl_used::31 0.682800 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1170 +system.cpu0.kern.mode_good::user 1171 system.cpu0.kern.mode_good::idle 0 system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1171 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.170052 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169762 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898870092500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1973278500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1898856944500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1973905500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3288 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed @@ -580,503 +580,503 @@ system.cpu0.kern.syscall::132 1 0.50% 98.51% # nu system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 201 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2303690 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1915346 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9134167 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5841972 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 112777545 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 12780906 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 33989447 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1008250 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33579404 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1370622 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 43227 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 72557706 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 59333926 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 39987201 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11036329 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1270160 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3988199 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5997752 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 16871933 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1393572 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10085816 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 207581 # count of temporary serializing insts renamed -system.cpu0.timesIdled 1187611 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.memDep0.conflictingLoads 2309039 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1917455 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9135520 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5842466 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 112782214 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 12781389 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 33989509 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1007909 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33583011 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1370380 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 43256 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 72564759 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 59338809 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 39990302 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11042113 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1270716 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3987723 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 6000791 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 16867773 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1393581 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10085074 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 207606 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1187595 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1157962 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2699963 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8335 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 172116 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2481640 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 2995076 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 209806 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1517916 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 197525 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1159628 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2701076 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8300 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 172219 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2481214 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 2994712 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 209821 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1517871 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 197774 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 17848598 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.593368 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.404700 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 17831958 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.593915 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.406567 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 13459755 75.41% 75.41% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2076221 11.63% 87.04% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 798391 4.47% 91.52% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 569134 3.19% 94.70% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 394612 2.21% 96.92% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 153567 0.86% 97.78% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 111850 0.63% 98.40% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 87543 0.49% 98.89% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 197525 1.11% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 13448737 75.42% 75.42% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2070572 11.61% 87.03% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 799926 4.49% 91.52% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 567078 3.18% 94.70% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 394341 2.21% 96.91% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 151842 0.85% 97.76% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 111575 0.63% 98.39% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 90113 0.51% 98.89% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 197774 1.11% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 17848598 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10590789 # Number of instructions committed -system.cpu1.commit.COM:loads 1991065 # Number of loads committed +system.cpu1.commit.COM:committed_per_cycle::total 17831958 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10590665 # Number of instructions committed +system.cpu1.commit.COM:loads 1991024 # Number of loads committed system.cpu1.commit.COM:membars 52740 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3374997 # Number of memory references committed +system.cpu1.commit.COM:refs 3374947 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 164251 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10590789 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 163017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1716683 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10063537 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10063537 # Number of Instructions Simulated -system.cpu1.cpi 1.953144 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.953144 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 46385 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46385 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11093.156176 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 164356 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10590665 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 163015 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1719784 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10063421 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10063421 # Number of Instructions Simulated +system.cpu1.cpi 1.950737 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.950737 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 46382 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46382 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11099.301842 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8017.085427 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 39649 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39649 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 74723500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145219 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6736 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6736 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 766 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47862000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128705 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8021.283727 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 39650 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39650 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 74720500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145143 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6732 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6732 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 765 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47863000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128649 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5970 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2063183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2063183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15106.279717 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2063263 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2063263 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15045.752696 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.123629 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.073615 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1870531 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1870531 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2910255000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.093376 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 192652 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 192652 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 97561 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1111055000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046089 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1869340 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1869340 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 2917717500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.093989 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 193923 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 193923 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 98779 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1111669500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046113 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95091 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 43197 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 43197 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13112.263417 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 95144 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 43195 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43195 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13108.977686 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10114.107884 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 39340 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 39340 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 50574000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089289 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3857 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3857 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39000000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089265 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10107.291126 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 39341 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 39341 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 50522000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089223 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3854 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3854 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 38953500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089223 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3856 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1334344 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1334344 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 21202.003457 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 3854 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1334339 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1334339 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 21230.266809 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18758.167110 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18781.127505 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1085015 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1085015 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 5286274320 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.186855 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 249329 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 249329 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 200876 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 908889471 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_hits::0 1084932 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1084932 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 5294977154 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.186914 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 249407 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 249407 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 200954 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 910001971 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036312 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 48453 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377675000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10123.559438 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377711000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9964.987699 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.895667 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 5123 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 22.877704 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 5284 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 51862995 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 52654995 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3397527 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3397602 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3397527 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 18544.981164 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3397602 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 18525.014445 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14071.953345 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2955546 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2954272 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2955546 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 8196529320 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.130089 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2954272 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 8212694654 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.130483 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 441981 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 443330 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 441981 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 298437 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 2019944471 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.042250 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 443330 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 299733 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 2021671471 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.042264 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 143544 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 143597 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.933247 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 477.822541 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3397527 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.933246 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 477.822051 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3397602 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3397527 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 18544.981164 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3397602 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 18525.014445 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14071.953345 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2955546 # number of overall hits +system.cpu1.dcache.overall_hits::0 2954272 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2955546 # number of overall hits -system.cpu1.dcache.overall_miss_latency 8196529320 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.130089 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2954272 # number of overall hits +system.cpu1.dcache.overall_miss_latency 8212694654 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.130483 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 441981 # number of overall misses +system.cpu1.dcache.overall_misses::0 443330 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 441981 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 298437 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 2019944471 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.042250 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 443330 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 299733 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 2021671471 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.042264 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 143544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 395352000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 143597 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 395388500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 132498 # number of replacements -system.cpu1.dcache.sampled_refs 132892 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 132546 # number of replacements +system.cpu1.dcache.sampled_refs 132940 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 477.822541 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3042651 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1877659701000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tagsinuse 477.822051 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3041362 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1877659740000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 88702 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 6987029 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BlockedCycles 6966662 # Number of cycles decode is blocked system.cpu1.decode.DECODE:BranchMispred 7945 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 127739 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 13932578 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8260937 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2501859 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 305063 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 23694 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 98772 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 453342 # DTB accesses +system.cpu1.decode.DECODE:BranchResolved 127784 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 13937245 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8263002 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2503476 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 305841 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 23696 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 98817 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 453673 # DTB accesses system.cpu1.dtb.data_acv 183 # DTB access violations -system.cpu1.dtb.data_hits 3613400 # DTB hits -system.cpu1.dtb.data_misses 12964 # DTB misses +system.cpu1.dtb.data_hits 3613751 # DTB hits +system.cpu1.dtb.data_misses 13007 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 321975 # DTB read accesses -system.cpu1.dtb.read_acv 83 # DTB read access violations -system.cpu1.dtb.read_hits 2187186 # DTB read hits -system.cpu1.dtb.read_misses 10487 # DTB read misses -system.cpu1.dtb.write_accesses 131367 # DTB write accesses -system.cpu1.dtb.write_acv 100 # DTB write access violations -system.cpu1.dtb.write_hits 1426214 # DTB write hits -system.cpu1.dtb.write_misses 2477 # DTB write misses -system.cpu1.fetch.Branches 2995076 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1674453 # Number of cache lines fetched -system.cpu1.fetch.Cycles 4316686 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 103652 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14184875 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 191233 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.152378 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1674453 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1367768 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.721673 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 18153661 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.781378 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.130034 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 322326 # DTB read accesses +system.cpu1.dtb.read_acv 82 # DTB read access violations +system.cpu1.dtb.read_hits 2187602 # DTB read hits +system.cpu1.dtb.read_misses 10512 # DTB read misses +system.cpu1.dtb.write_accesses 131347 # DTB write accesses +system.cpu1.dtb.write_acv 101 # DTB write access violations +system.cpu1.dtb.write_hits 1426149 # DTB write hits +system.cpu1.dtb.write_misses 2495 # DTB write misses +system.cpu1.fetch.Branches 2994712 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1675694 # Number of cache lines fetched +system.cpu1.fetch.Cycles 4319661 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 103833 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14189706 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 191595 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.152550 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1675694 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1369449 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.722818 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 18137799 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782328 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.130924 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15520231 85.49% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 211004 1.16% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 323759 1.78% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 198428 1.09% 89.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 375870 2.07% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 125712 0.69% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169249 0.93% 93.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 251729 1.39% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 977679 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15502694 85.47% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 211332 1.17% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 324186 1.79% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 198526 1.09% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 376340 2.07% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 125878 0.69% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169328 0.93% 93.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 252414 1.39% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 977101 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18153661 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 1674453 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1674453 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14671.340426 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 18137799 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 1675694 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1675694 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14669.843213 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.734234 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1410604 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1410604 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3871018500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.157573 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 263849 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 263849 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 8241 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2972397500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152652 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.039136 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1411833 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1411833 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3870799500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.157464 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 263861 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 263861 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 8268 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2972301000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152530 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 255608 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses 255593 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs 4444.444444 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.519875 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 5.524987 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1674453 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1675694 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1674453 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14671.340426 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1675694 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14669.843213 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11628.734234 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1410604 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1411833 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1410604 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3871018500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.157573 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1411833 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3870799500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.157464 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 263849 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 263861 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 263849 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 8241 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2972397500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.152652 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 263861 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 8268 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2972301000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.152530 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 255608 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 255593 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.occ_%::0 0.900435 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 461.022947 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1674453 # number of overall (read+write) accesses +system.cpu1.icache.occ_blocks::0 461.022612 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1675694 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1674453 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14671.340426 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1675694 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14669.843213 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11628.734234 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1410604 # number of overall hits +system.cpu1.icache.overall_hits::0 1411833 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1410604 # number of overall hits -system.cpu1.icache.overall_miss_latency 3871018500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.157573 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1411833 # number of overall hits +system.cpu1.icache.overall_miss_latency 3870799500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.157464 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 263849 # number of overall misses +system.cpu1.icache.overall_misses::0 263861 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 263849 # number of overall misses -system.cpu1.icache.overall_mshr_hits 8241 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2972397500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.152652 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 263861 # number of overall misses +system.cpu1.icache.overall_mshr_hits 8268 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2972301000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.152530 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 255608 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 255593 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 255038 # number of replacements -system.cpu1.icache.sampled_refs 255550 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 255024 # number of replacements +system.cpu1.icache.sampled_refs 255536 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 461.022947 # Cycle average of tags in use -system.cpu1.icache.total_refs 1410604 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897916451000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 461.022612 # Cycle average of tags in use +system.cpu1.icache.total_refs 1411833 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897916222000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 13 # number of writebacks -system.cpu1.idleCycles 1501880 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1627207 # Number of branches executed -system.cpu1.iew.EXEC:nop 601288 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.550852 # Inst execution rate -system.cpu1.iew.EXEC:refs 3642900 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1435734 # Number of stores executed +system.cpu1.idleCycles 1493284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1627599 # Number of branches executed +system.cpu1.iew.EXEC:nop 601660 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.551671 # Inst execution rate +system.cpu1.iew.EXEC:refs 3643304 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1435691 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6254497 # num instructions consuming a value -system.cpu1.iew.WB:count 10719851 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.736543 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6256127 # num instructions consuming a value +system.cpu1.iew.WB:count 10722196 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.736602 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4606706 # num instructions producing a value -system.cpu1.iew.WB:rate 0.545386 # insts written-back per cycle -system.cpu1.iew.WB:sent 10743061 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 178420 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 265381 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2308328 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 500549 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 208852 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1509637 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12390699 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2207166 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106974 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10827293 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 2483 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4608274 # num instructions producing a value +system.cpu1.iew.WB:rate 0.546185 # insts written-back per cycle +system.cpu1.iew.WB:sent 10745464 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 178521 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 256730 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2308752 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 500484 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 209358 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1509923 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12393438 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2207613 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 106928 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10829897 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 2615 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 4852 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 305063 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 10314 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 4833 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 305841 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 10301 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 22342 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 67469 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2212 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 22559 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 67759 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 10592 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 10819 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 317263 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 125705 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 10592 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104736 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 73684 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.511995 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.511995 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 317728 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 126000 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 10819 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104538 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 73983 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.512627 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.512627 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3525 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6856403 62.71% 62.74% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 17935 0.16% 62.90% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.90% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6858697 62.71% 62.74% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 17938 0.16% 62.91% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.01% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.01% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.01% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282654 20.88% 83.90% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452686 13.29% 97.18% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307870 2.82% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282943 20.87% 83.90% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452642 13.28% 97.18% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307886 2.82% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 10934267 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 157620 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014415 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 10936825 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 157834 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 4070 2.58% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.58% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 93965 59.61% 62.20% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 59585 37.80% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 3969 2.51% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 94191 59.68% 62.19% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 59674 37.81% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 18153661 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602317 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.206394 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 18137799 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602985 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.207807 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 12924725 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2574747 14.18% 85.38% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1068107 5.88% 91.26% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 685428 3.78% 95.04% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 525394 2.89% 97.93% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 238254 1.31% 99.25% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 93756 0.52% 99.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 34360 0.19% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 8890 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 12914156 71.20% 71.20% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2567061 14.15% 85.35% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1068417 5.89% 91.24% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 686600 3.79% 95.03% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 525581 2.90% 97.93% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 238380 1.31% 99.24% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 93711 0.52% 99.76% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 34504 0.19% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 9389 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 18153661 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.556294 # Inst issue rate -system.cpu1.iq.iqInstsAdded 11233407 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 10934267 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 556004 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1651489 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10261 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 847945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 18137799 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.557118 # Inst issue rate +system.cpu1.iq.iqInstsAdded 11235835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 10936825 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 555943 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1653815 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10214 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 392928 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 848491 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 448239 # ITB accesses -system.cpu1.itb.fetch_acv 291 # ITB acv -system.cpu1.itb.fetch_hits 439727 # ITB hits -system.cpu1.itb.fetch_misses 8512 # ITB misses +system.cpu1.itb.fetch_accesses 449298 # ITB accesses +system.cpu1.itb.fetch_acv 268 # ITB acv +system.cpu1.itb.fetch_hits 440704 # ITB hits +system.cpu1.itb.fetch_misses 8594 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1092,7 +1092,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # nu system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 49367 86.50% 89.53% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49369 86.50% 89.53% # number of callpals executed system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed @@ -1102,42 +1102,42 @@ system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # nu system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 57069 # number of callpals executed +system.cpu1.kern.callpal::total 57071 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 64908 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 64910 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed system.cpu1.kern.ipl_count::0 20666 37.58% 37.58% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1922 3.49% 41.07% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 32054 58.29% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 54993 # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 32056 58.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 54995 # number of times we switched to this ipl system.cpu1.kern.ipl_good::0 20159 47.72% 47.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 19808 46.89% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 42240 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870788653000 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 347996000 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 137644000 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29218866000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900493159000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1870775538500 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 348024500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 137644500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29219363500 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900480571000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.975467 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.617957 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 848 -system.cpu1.kern.mode_good::user 572 +system.cpu1.kern.ipl_used::31 0.617919 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 850 +system.cpu1.kern.mode_good::user 574 system.cpu1.kern.mode_good::idle 276 system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches -system.cpu1.kern.mode_switch::user 572 # number of protection mode switches +system.cpu1.kern.mode_switch::user 574 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2543 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.480181 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.481314 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.108533 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.588714 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6310117500 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1035001500 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893135458000 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 1.589847 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6310376000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1022366000 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893135370000 99.61% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1451 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed @@ -1162,29 +1162,29 @@ system.cpu1.kern.syscall::92 2 1.60% 96.80% # nu system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 125 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 486173 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 418032 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2308328 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1509637 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 19655541 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 539966 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7148793 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 37026 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8494445 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 255442 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 15493 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15440476 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 12911511 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8475661 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2354555 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 305063 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 804143 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1326868 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 5655487 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 515592 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2314825 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 52743 # count of temporary serializing insts renamed -system.cpu1.timesIdled 195289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.memDep0.conflictingLoads 490785 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 414407 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2308752 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1509923 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 19631083 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 523690 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7148714 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 34540 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8495610 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 254592 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 15458 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15445784 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 12915573 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8478574 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2357052 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 305841 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 801048 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1329860 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 5654556 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 515569 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2305021 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 52779 # count of temporary serializing insts renamed +system.cpu1.timesIdled 194610 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1200,14 +1200,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 172 # number of ReadReq misses system.iocache.ReadReq_misses::total 172 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -1215,37 +1215,37 @@ system.iocache.ReadReq_mshr_misses 172 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137698.469532 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137691.995716 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85694.888285 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5721646806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85688.414469 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5721377806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3560793998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560524998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6175.166651 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6177.748159 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64586068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64613068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137606.001438 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137599.578276 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85602.434954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741472804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741204804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -1253,7 +1253,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3571675996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571407996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -1261,20 +1261,20 @@ system.iocache.demand_mshr_misses 41724 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029213 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.467409 # Average occupied blocks per context +system.iocache.occ_%::1 0.029207 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.467307 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137606.001438 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137599.578276 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85602.434954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741472804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741204804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -1282,7 +1282,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3571675996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571407996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -1292,196 +1292,196 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41692 # number of replacements system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.467409 # Cycle average of tags in use +system.iocache.tagsinuse 0.467307 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1711286220000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 42275 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 299574 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55985.285399 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 837699.087169 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257314 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 42271 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 299585 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55984.756831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 837468.637532 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40323.891140 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 140918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 34497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 175415 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6515623500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.452318 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.183986 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116381 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 7778 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124159 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5006574000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.482548 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.936937 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40322.708602 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 140934 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 34491 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175425 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6515506000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.452288 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.184051 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116380 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7780 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124160 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5006467500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.482523 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.937238 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 124159 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1807451 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 343425 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2150876 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52799.873154 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3686022.252810 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 124160 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1807452 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 343469 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2150921 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52799.023345 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3689312.055109 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.119229 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.019200 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1503144 # number of ReadReq hits -system.l2c.ReadReq_hits::1 339066 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1842210 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16067371000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.168363 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.012693 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304307 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4359 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308666 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1503148 # number of ReadReq hits +system.l2c.ReadReq_hits::1 339114 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1842262 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16066954000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.168361 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.012679 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304304 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4355 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308659 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12351592500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.170765 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.898741 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12351281500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.170761 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.898605 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308650 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840468500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 4894.075404 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 4740.869565 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 308643 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840474000 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 607 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 600 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1207 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 4817.117117 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4657.665505 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.692580 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.728964 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_hits::0 52 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::1 26 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 2726000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.914614 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.956739 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 557 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 575 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1132 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 45295500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.858785 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.883527 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_latency 2673500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.914333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.956667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 555 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 574 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1129 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 45175500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.859967 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.881667 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1132 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 2884 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 1624 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4508 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 5854.945055 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12526.645768 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 1129 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 2880 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 1625 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5822.515585 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12443.573668 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.724913 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 154 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 348 # number of UpgradeReq hits +system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 349 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 502 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 15984000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.946602 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.785714 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_latency 15878000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.946875 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.785231 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 2727 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 1276 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4006 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 160307000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.389043 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.466749 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::total 4003 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 160188000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.389931 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.463385 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 4006 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4003 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1533340998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1533346998 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses::0 810378 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 810378 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 810378 # number of Writeback hits system.l2c.Writeback_hits::total 810378 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.650924 # Average number of references to valid blocks. +system.l2c.avg_refs 5.651210 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2064750 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 385700 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2064766 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 385740 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450450 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 53681.099770 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1860673.518992 # average overall miss latency +system.l2c.demand_accesses::total 2450506 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 53680.339637 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1860936.135146 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40105.835368 # average overall mshr miss latency -system.l2c.demand_hits::0 1644062 # number of demand (read+write) hits -system.l2c.demand_hits::1 373563 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency +system.l2c.demand_hits::0 1644082 # number of demand (read+write) hits +system.l2c.demand_hits::1 373605 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2017625 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22582994500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.203748 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.031467 # miss rate for demand accesses +system.l2c.demand_hits::total 2017687 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22582460000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.203744 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.031459 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 420688 # number of demand (read+write) misses -system.l2c.demand_misses::1 12137 # number of demand (read+write) misses +system.l2c.demand_misses::0 420684 # number of demand (read+write) misses +system.l2c.demand_misses::1 12135 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 432825 # number of demand (read+write) misses +system.l2c.demand_misses::total 432819 # number of demand (read+write) misses system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17358166500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.209618 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.122139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17357749000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.209614 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.122007 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 432809 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 432803 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.occ_%::0 0.187928 # Average percentage of cache occupancy system.l2c.occ_%::1 0.005741 # Average percentage of cache occupancy system.l2c.occ_%::2 0.351843 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12316.075760 # Average occupied blocks per context -system.l2c.occ_blocks::1 376.251227 # Average occupied blocks per context -system.l2c.occ_blocks::2 23058.372205 # Average occupied blocks per context -system.l2c.overall_accesses::0 2064750 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 385700 # number of overall (read+write) accesses +system.l2c.occ_blocks::0 12316.028373 # Average occupied blocks per context +system.l2c.occ_blocks::1 376.255092 # Average occupied blocks per context +system.l2c.occ_blocks::2 23058.373739 # Average occupied blocks per context +system.l2c.overall_accesses::0 2064766 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 385740 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2450450 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 53681.099770 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1860673.518992 # average overall miss latency +system.l2c.overall_accesses::total 2450506 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 53680.339637 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1860936.135146 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40105.835368 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1644062 # number of overall hits -system.l2c.overall_hits::1 373563 # number of overall hits +system.l2c.overall_hits::0 1644082 # number of overall hits +system.l2c.overall_hits::1 373605 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2017625 # number of overall hits -system.l2c.overall_miss_latency 22582994500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.203748 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.031467 # miss rate for overall accesses +system.l2c.overall_hits::total 2017687 # number of overall hits +system.l2c.overall_miss_latency 22582460000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.203744 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.031459 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 420688 # number of overall misses -system.l2c.overall_misses::1 12137 # number of overall misses +system.l2c.overall_misses::0 420684 # number of overall misses +system.l2c.overall_misses::1 12135 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 432825 # number of overall misses +system.l2c.overall_misses::total 432819 # number of overall misses system.l2c.overall_mshr_hits 16 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17358166500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.209618 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.122139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17357749000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.209614 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.122007 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 432809 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2373809498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 432803 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2373820998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 395557 # number of replacements -system.l2c.sampled_refs 431639 # Sample count of references to valid blocks. +system.l2c.replacements 395553 # number of replacements +system.l2c.sampled_refs 431632 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35750.699192 # Cycle average of tags in use -system.l2c.total_refs 2439159 # Total number of references to valid blocks. +system.l2c.tagsinuse 35750.657204 # Cycle average of tags in use +system.l2c.total_refs 2439243 # Total number of references to valid blocks. system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 121360 # number of writebacks +system.l2c.writebacks 121365 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index ca3dfd6a4..5bcb96563 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 14 2010 23:49:18 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 14 2010 23:49:28 +M5 compiled Dec 1 2010 12:54:21 +M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase +M5 started Dec 3 2010 12:04:42 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1866702027500 because m5_exit instruction encountered +Exiting @ tick 1865725201500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 7a6e724ef..8a396ee2c 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 136365 # Simulator instruction rate (inst/s) -host_mem_usage 291304 # Number of bytes of host memory used -host_seconds 389.05 # Real time elapsed on the host -host_tick_rate 4798136047 # Simulator tick rate (ticks/s) +host_inst_rate 175308 # Simulator instruction rate (inst/s) +host_mem_usage 291488 # Number of bytes of host memory used +host_seconds 302.62 # Real time elapsed on the host +host_tick_rate 6165281708 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53052455 # Number of instructions simulated -sim_seconds 1.866702 # Number of seconds simulated -sim_ticks 1866702027500 # Number of ticks simulated +sim_insts 53051410 # Number of instructions simulated +sim_seconds 1.865725 # Number of seconds simulated +sim_ticks 1865725201500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6621213 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12790882 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 40565 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 813829 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11937472 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14341052 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1015322 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8457404 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1008788 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6623532 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12798498 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 40602 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 812765 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11935951 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14337786 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1014820 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8457292 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1010049 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 89226144 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.630371 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.393749 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 89220035 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.630402 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.393670 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 65115177 72.98% 72.98% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10635450 11.92% 84.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6055707 6.79% 91.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2838740 3.18% 94.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2097041 2.35% 97.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 703016 0.79% 98.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 396600 0.44% 98.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 375625 0.42% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1008788 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 65107302 72.97% 72.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10633646 11.92% 84.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6059339 6.79% 91.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2842196 3.19% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2097639 2.35% 97.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 698987 0.78% 98.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 396440 0.44% 98.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 374437 0.42% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1010049 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 89226144 # Number of insts commited each cycle -system.cpu.commit.COM:count 56245607 # Number of instructions committed -system.cpu.commit.COM:loads 9107515 # Number of loads committed -system.cpu.commit.COM:membars 227978 # Number of memory barriers committed -system.cpu.commit.COM:refs 15496786 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 89220035 # Number of insts commited each cycle +system.cpu.commit.COM:count 56244494 # Number of instructions committed +system.cpu.commit.COM:loads 9107208 # Number of loads committed +system.cpu.commit.COM:membars 227971 # Number of memory barriers committed +system.cpu.commit.COM:refs 15496285 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 772588 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56245607 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667624 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8707015 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53052455 # Number of Instructions Simulated -system.cpu.committedInsts_total 53052455 # Number of Instructions Simulated -system.cpu.cpi 2.357033 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.357033 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 215727 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215727 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14718.915641 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 771538 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56244494 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667580 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8696245 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53051410 # Number of Instructions Simulated +system.cpu.committedInsts_total 53051410 # Number of Instructions Simulated +system.cpu.cpi 2.356931 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.356931 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 215724 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215724 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14717.635433 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11880.303464 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 193465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 327672500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103195 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.423892 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 193462 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 193462 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 327644000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103197 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses::0 22262 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4797 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207489500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080959 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_hits 4800 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207438500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080946 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17465 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9301609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9301609 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 22726.604176 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17462 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9298342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9298342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 22727.861188 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22780.008433 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.930840 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7726221 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7726221 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 35803219500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.169367 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1575388 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1575388 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 491526 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24690385500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7723201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7723201 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 35799586000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.169400 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1575141 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1575141 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 491284 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24690187500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116565 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1083862 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906011000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219693 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219693 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1083857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906002000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219691 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219691 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219690 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219690 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::0 219688 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219688 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses @@ -104,384 +104,384 @@ system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6154417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6154417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29746.241624 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6154235 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6154235 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29744.201377 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.562806 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.748800 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4299174 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4299174 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 55186506550 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.301449 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1855243 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1855243 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1555600 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8416840868 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4298938 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4298938 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 55184327582 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.301467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 1855297 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1855297 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1555651 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8416980869 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048689 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299643 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235850498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8970.438750 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 299646 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235741498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8981.209245 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.879414 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 83323 # number of cycles access was blocked +system.cpu.dcache.avg_refs 8.877118 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 83266 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 747443868 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 747829369 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15456026 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15452577 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15456026 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26522.737668 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15452577 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26522.535484 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23929.965102 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 12025395 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 12022139 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12025395 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 90989726050 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.221961 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 12022139 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 90983913582 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.221998 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3430631 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3430438 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430631 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2047126 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33107226368 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089512 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3430438 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2046935 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33107168369 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.089532 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1383505 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1383503 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995490 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15456026 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.995488 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15452577 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15456026 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26522.737668 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15452577 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26522.535484 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23929.965102 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 12025395 # number of overall hits +system.cpu.dcache.overall_hits::0 12022139 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12025395 # number of overall hits -system.cpu.dcache.overall_miss_latency 90989726050 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.221961 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 12022139 # number of overall hits +system.cpu.dcache.overall_miss_latency 90983913582 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.221998 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3430631 # number of overall misses +system.cpu.dcache.overall_misses::0 3430438 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3430631 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2047126 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33107226368 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089512 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3430438 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2046935 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33107168369 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.089532 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1383505 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2141861498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1383503 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2141743498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400326 # number of replacements -system.cpu.dcache.sampled_refs 1400838 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400321 # number of replacements +system.cpu.dcache.sampled_refs 1400833 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995490 # Cycle average of tags in use -system.cpu.dcache.total_refs 12438621 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.995488 # Cycle average of tags in use +system.cpu.dcache.total_refs 12435360 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 832750 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 37798869 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42152 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 613702 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 71408267 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37495225 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12847618 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1517170 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134367 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1084431 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236579 # DTB accesses -system.cpu.dtb.data_acv 821 # DTB access violations -system.cpu.dtb.data_hits 16598484 # DTB hits -system.cpu.dtb.data_misses 46851 # DTB misses +system.cpu.dcache.writebacks 832778 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 37796755 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42128 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 613699 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 71391245 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37490796 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12847951 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1515207 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134411 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1084532 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1236239 # DTB accesses +system.cpu.dtb.data_acv 812 # DTB access violations +system.cpu.dtb.data_hits 16594781 # DTB hits +system.cpu.dtb.data_misses 46795 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 911643 # DTB read accesses -system.cpu.dtb.read_acv 587 # DTB read access violations -system.cpu.dtb.read_hits 10010922 # DTB read hits -system.cpu.dtb.read_misses 38585 # DTB read misses -system.cpu.dtb.write_accesses 324936 # DTB write accesses -system.cpu.dtb.write_acv 234 # DTB write access violations -system.cpu.dtb.write_hits 6587562 # DTB write hits -system.cpu.dtb.write_misses 8266 # DTB write misses -system.cpu.fetch.Branches 14341052 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8858763 # Number of cache lines fetched -system.cpu.fetch.Cycles 23012166 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 454758 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72677531 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2805 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 885401 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114686 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8858763 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7636535 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.581205 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 90743314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.800913 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110485 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 911340 # DTB read accesses +system.cpu.dtb.read_acv 579 # DTB read access violations +system.cpu.dtb.read_hits 10007690 # DTB read hits +system.cpu.dtb.read_misses 38589 # DTB read misses +system.cpu.dtb.write_accesses 324899 # DTB write accesses +system.cpu.dtb.write_acv 233 # DTB write access violations +system.cpu.dtb.write_hits 6587091 # DTB write hits +system.cpu.dtb.write_misses 8206 # DTB write misses +system.cpu.fetch.Branches 14337786 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8855787 # Number of cache lines fetched +system.cpu.fetch.Cycles 23008954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 454021 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 72656034 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 884311 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114667 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8855787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7638352 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.581069 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 90735242 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.800748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.110037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76629913 84.45% 84.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1043583 1.15% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1968273 2.17% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 922995 1.02% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2983072 3.29% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 649341 0.72% 92.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 774162 0.85% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1071348 1.18% 94.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4700627 5.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76622057 84.45% 84.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1044700 1.15% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1968700 2.17% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 923179 1.02% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2984209 3.29% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 647959 0.71% 92.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 776741 0.86% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1074256 1.18% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4693441 5.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90743314 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8858763 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8858763 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14954.289774 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 90735242 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8855787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8855787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14954.156504 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.526205 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7818580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7818580 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15555198000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.117419 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1040183 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1040183 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 47630 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11849620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112042 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.651524 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7815574 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7815574 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15555508000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.117461 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1040213 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1040213 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 47670 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11849625000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112078 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 992553 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12638.888889 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 992543 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 12375 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.878725 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.875775 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 682500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 693000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8858763 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8855787 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8858763 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14954.289774 # average overall miss latency +system.cpu.icache.demand_accesses::total 8855787 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14954.156504 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11938.526205 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7818580 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7815574 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7818580 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15555198000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.117419 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7815574 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15555508000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.117461 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1040183 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1040213 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1040183 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 47630 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11849620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.112042 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1040213 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 47670 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11849625000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.112078 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 992553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 992543 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995726 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.811580 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8858763 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.810496 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8855787 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8858763 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14954.289774 # average overall miss latency +system.cpu.icache.overall_accesses::total 8855787 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14954.156504 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11938.526205 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7818580 # number of overall hits +system.cpu.icache.overall_hits::0 7815574 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7818580 # number of overall hits -system.cpu.icache.overall_miss_latency 15555198000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.117419 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7815574 # number of overall hits +system.cpu.icache.overall_miss_latency 15555508000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.117461 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1040183 # number of overall misses +system.cpu.icache.overall_misses::0 1040213 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1040183 # number of overall misses -system.cpu.icache.overall_mshr_hits 47630 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11849620000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.112042 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1040213 # number of overall misses +system.cpu.icache.overall_mshr_hits 47670 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11849625000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.112078 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 992553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 992543 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 991855 # number of replacements -system.cpu.icache.sampled_refs 992366 # Sample count of references to valid blocks. +system.cpu.icache.replacements 991845 # number of replacements +system.cpu.icache.sampled_refs 992356 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.811580 # Cycle average of tags in use -system.cpu.icache.total_refs 7818579 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 509.810496 # Cycle average of tags in use +system.cpu.icache.total_refs 7815573 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 92 # number of writebacks -system.cpu.idleCycles 34303057 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9120771 # Number of branches executed -system.cpu.iew.EXEC:nop 3587259 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.457031 # Inst execution rate -system.cpu.iew.EXEC:refs 16688341 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6610740 # Number of stores executed +system.cpu.idleCycles 34303252 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9120523 # Number of branches executed +system.cpu.iew.EXEC:nop 3586903 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.457009 # Inst execution rate +system.cpu.iew.EXEC:refs 16684584 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6610209 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 35263770 # num instructions consuming a value -system.cpu.iew.WB:count 56701745 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757231 # average fanout of values written-back +system.cpu.iew.WB:consumers 35266489 # num instructions consuming a value +system.cpu.iew.WB:count 56698013 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757126 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26702819 # num instructions producing a value -system.cpu.iew.WB:rate 0.453446 # insts written-back per cycle -system.cpu.iew.WB:sent 56803907 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 838873 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9248148 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10633496 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1790322 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 888125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6942976 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65083615 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10077601 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 523401 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57150006 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 61281 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26701175 # num instructions producing a value +system.cpu.iew.WB:rate 0.453444 # insts written-back per cycle +system.cpu.iew.WB:sent 56800066 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 837864 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9247048 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10627556 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1790217 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 887680 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6942367 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65072200 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10074375 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 520995 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57143757 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61290 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11748 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1517170 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 557912 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 11719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1515207 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 557918 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 131935 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 439695 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9709 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 132136 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 439501 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9711 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42652 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17619 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1525981 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 553705 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42652 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 406121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 432752 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.424262 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424262 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 42523 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17618 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1520348 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 553290 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42523 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 405909 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431955 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.424281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424281 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39530216 68.54% 68.55% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62377 0.11% 68.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.66% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39528092 68.55% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62364 0.11% 68.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10431492 18.09% 86.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659819 11.55% 98.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 952981 1.65% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10425722 18.08% 86.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659174 11.55% 98.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 952878 1.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 57673409 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 436908 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007576 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 57664754 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 434083 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007528 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 51858 11.87% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 268470 61.45% 73.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 116580 26.68% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 49311 11.36% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 268240 61.79% 73.15% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 116532 26.85% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 90743314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635566 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200958 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 90735242 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200743 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 62371115 68.73% 68.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14052012 15.49% 84.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6227116 6.86% 91.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3817489 4.21% 95.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2534919 2.79% 98.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1095821 1.21% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 467371 0.52% 99.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 128077 0.14% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 49394 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 62361011 68.73% 68.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14057815 15.49% 84.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6222317 6.86% 91.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3820698 4.21% 95.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2539136 2.80% 98.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1090667 1.20% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 464211 0.51% 99.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 130030 0.14% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 49357 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 90743314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.461216 # Inst issue rate -system.cpu.iq.iqInstsAdded 59456475 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57673409 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2039881 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8066144 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 29810 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1372257 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4171431 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 90735242 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.461176 # Inst issue rate +system.cpu.iq.iqInstsAdded 59445556 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 57664754 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2039741 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8057348 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 28990 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1372161 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4163419 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1294967 # ITB accesses -system.cpu.itb.fetch_acv 915 # ITB acv -system.cpu.itb.fetch_hits 1255877 # ITB hits -system.cpu.itb.fetch_misses 39090 # ITB misses +system.cpu.itb.fetch_accesses 1294712 # ITB accesses +system.cpu.itb.fetch_acv 931 # ITB acv +system.cpu.itb.fetch_hits 1255658 # ITB hits +system.cpu.itb.fetch_misses 39054 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -497,51 +497,51 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175602 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175584 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5222 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192574 # number of callpals executed +system.cpu.kern.callpal::total 192554 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211736 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6428 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74918 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 241 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105906 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182955 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73551 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73553 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149235 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1827169522000 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98068500 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392034000 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39041528500 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1866701153000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981753 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211714 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74913 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 242 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105891 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182935 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73546 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 242 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73549 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149226 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1826194246000 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98158000 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 391805000 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39040113000 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865724322000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694512 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.ipl_used::31 0.694573 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 system.cpu.kern.mode_switch::kernel 5963 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320141 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.319805 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400786 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30087907500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2984190000 0.16% 1.77% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1833629047500 98.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400566 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 30090318500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2984804000 0.16% 1.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832649191500 98.23% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -574,29 +574,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3017684 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2588344 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10633496 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6942976 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 125046371 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 13291099 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38228333 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1062884 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39061405 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1660710 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58609 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 82224860 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 67584077 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45304633 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12511976 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1517170 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4651674 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7076298 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 19709988 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1694270 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 11738773 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 247232 # count of temporary serializing insts renamed -system.cpu.timesIdled 1310674 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3016554 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2589214 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 10627556 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6942367 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 125038494 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 13289726 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38227615 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1062967 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39056171 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1660859 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 58584 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 82207964 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 67568741 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45291881 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12513158 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1515207 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4651851 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7064264 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 19709127 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1694237 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 11738316 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 247282 # count of temporary serializing insts renamed +system.cpu.timesIdled 1310688 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -612,14 +612,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -627,37 +627,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137728.913313 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137727.806267 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85725.355699 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722911806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85724.248652 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5722865806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3562059980 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3562013980 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6166.098893 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.439863 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64596052 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64631052 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137635.729275 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137634.602852 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85632.186411 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5742850804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5742803804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -665,7 +665,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3573002978 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572955978 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -673,20 +673,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.081527 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.304436 # Average occupied blocks per context +system.iocache.occ_%::1 0.081046 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.296742 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137635.729275 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137634.602852 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85632.186411 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5742850804 # number of overall miss cycles +system.iocache.overall_miss_latency 5742803804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -694,7 +694,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3573002978 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572955978 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -704,47 +704,47 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.304436 # Cycle average of tags in use +system.iocache.tagsinuse 1.296742 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1711281439000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300869 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300869 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52487.240298 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300867 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300867 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52486.783520 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40337.781709 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183860 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6141479500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388903 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 117009 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117009 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4719883500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388903 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40337.693248 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 183854 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183854 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6141636000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.388919 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 117013 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117013 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4720034500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.388919 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 117009 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2092408 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2092408 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.041420 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 117013 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2092394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2092394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52046.378325 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40014.986194 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.178174 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1784924 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1784924 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16003325000 # number of ReadReq miss cycles +system.l2c.ReadReq_hits::0 1784912 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1784912 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16003324500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_rate::0 0.146952 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307484 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307484 # number of ReadReq misses +system.l2c.ReadReq_misses::0 307482 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307482 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12303928000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 12303907000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::0 0.146952 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307483 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 811377500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_misses 307481 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 811370500 # number of ReadReq MSHR uncacheable cycles system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits @@ -767,80 +767,80 @@ system.l2c.UpgradeReq_mshr_miss_rate::1 inf # ms system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116250998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 832842 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832842 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 832842 # number of Writeback hits -system.l2c.Writeback_hits::total 832842 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116153998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 832870 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 832870 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 832870 # number of Writeback hits +system.l2c.Writeback_hits::total 832870 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.630753 # Average number of references to valid blocks. +system.l2c.avg_refs 5.629899 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2393277 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2393261 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2393277 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52167.655297 # average overall miss latency +system.l2c.demand_accesses::total 2393261 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52167.777006 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40103.963090 # average overall mshr miss latency -system.l2c.demand_hits::0 1968784 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency +system.l2c.demand_hits::0 1968766 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1968784 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22144804500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177369 # miss rate for demand accesses +system.l2c.demand_hits::total 1968766 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22144960500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.177371 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424493 # number of demand (read+write) misses +system.l2c.demand_misses::0 424495 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424493 # number of demand (read+write) misses +system.l2c.demand_misses::total 424495 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17023811500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177369 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17023941500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.177371 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424492 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 424494 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.186929 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.344699 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12250.608437 # Average occupied blocks per context -system.l2c.occ_blocks::1 22590.202953 # Average occupied blocks per context -system.l2c.overall_accesses::0 2393277 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.186894 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.344697 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12248.264673 # Average occupied blocks per context +system.l2c.occ_blocks::1 22590.041641 # Average occupied blocks per context +system.l2c.overall_accesses::0 2393261 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2393277 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52167.655297 # average overall miss latency +system.l2c.overall_accesses::total 2393261 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52167.777006 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40103.963090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1968784 # number of overall hits +system.l2c.overall_hits::0 1968766 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1968784 # number of overall hits -system.l2c.overall_miss_latency 22144804500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177369 # miss rate for overall accesses +system.l2c.overall_hits::total 1968766 # number of overall hits +system.l2c.overall_miss_latency 22144960500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.177371 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424493 # number of overall misses +system.l2c.overall_misses::0 424495 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424493 # number of overall misses +system.l2c.overall_misses::total 424495 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17023811500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177369 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17023941500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.177371 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424492 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1927628498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 424494 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1927524498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 390990 # number of replacements -system.l2c.sampled_refs 423735 # Sample count of references to valid blocks. +system.l2c.replacements 390994 # number of replacements +system.l2c.sampled_refs 423736 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34840.811390 # Cycle average of tags in use -system.l2c.total_refs 2385947 # Total number of references to valid blocks. +system.l2c.tagsinuse 34838.306314 # Cycle average of tags in use +system.l2c.total_refs 2385591 # Total number of references to valid blocks. system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 117624 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post |