diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-10 09:59:01 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-10 09:59:01 -0600 |
| commit | a5a2b9ecbdeeefcfa8d5a5d116c385cdf59e0256 (patch) | |
| tree | 0d018e4f474bb9dd45bffad990de8e753114e6c2 /tests/long/10.linux-boot | |
| parent | acbc03ae464b027fe93dca3a0bc796ef63f53113 (diff) | |
| download | gem5-a5a2b9ecbdeeefcfa8d5a5d116c385cdf59e0256.tar.xz | |
X86 Regressions: Update stats due to fence instruction
Diffstat (limited to 'tests/long/10.linux-boot')
4 files changed, 583 insertions, 582 deletions
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 5371c92be..9ef75afe6 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,10 +15,11 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem +num_work_ids=16 physmem=system.physmem readfile=tests/halt.sh smbios_table=system.smbios_table @@ -1301,7 +1302,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1321,7 +1322,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 795bcf9d9..18f42b689 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 21 2011 16:24:08 -gem5 started Nov 21 2011 23:30:30 -gem5 executing on u200540-lin -command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Jan 9 2012 20:47:38 +gem5 started Jan 9 2012 21:13:16 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5145286546500 because m5_exit instruction encountered +Exiting @ tick 5161177988500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f0652d752..e687ea7eb 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.145287 # Number of seconds simulated -sim_ticks 5145286546500 # Number of ticks simulated +sim_seconds 5.161178 # Number of seconds simulated +sim_ticks 5161177988500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 333179 # Simulator instruction rate (inst/s) -host_tick_rate 2041066369 # Simulator tick rate (ticks/s) -host_mem_usage 358476 # Number of bytes of host memory used -host_seconds 2520.88 # Real time elapsed on the host -sim_insts 839904894 # Number of instructions simulated -system.l2c.replacements 171120 # number of replacements -system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use -system.l2c.total_refs 3818646 # Total number of references to valid blocks. -system.l2c.sampled_refs 206013 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.535947 # Average number of references to valid blocks. +host_inst_rate 384526 # Simulator instruction rate (inst/s) +host_tick_rate 2360358751 # Simulator tick rate (ticks/s) +host_mem_usage 386468 # Number of bytes of host memory used +host_seconds 2186.61 # Real time elapsed on the host +sim_insts 840808469 # Number of instructions simulated +system.l2c.replacements 169467 # number of replacements +system.l2c.tagsinuse 38339.786444 # Cycle average of tags in use +system.l2c.total_refs 3812924 # Total number of references to valid blocks. +system.l2c.sampled_refs 204660 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.630529 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11983.527500 # Average occupied blocks per context -system.l2c.occ_blocks::1 26428.399366 # Average occupied blocks per context -system.l2c.occ_percent::0 0.182854 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.403265 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2330328 # number of ReadReq hits -system.l2c.ReadReq_hits::1 145914 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2476242 # number of ReadReq hits -system.l2c.Writeback_hits::0 1599020 # number of Writeback hits -system.l2c.Writeback_hits::total 1599020 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 343 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 150210 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 150210 # number of ReadExReq hits -system.l2c.demand_hits::0 2480538 # number of demand (read+write) hits -system.l2c.demand_hits::1 145914 # number of demand (read+write) hits -system.l2c.demand_hits::total 2626452 # number of demand (read+write) hits -system.l2c.overall_hits::0 2480538 # number of overall hits -system.l2c.overall_hits::1 145914 # number of overall hits -system.l2c.overall_hits::total 2626452 # number of overall hits -system.l2c.ReadReq_misses::0 68080 # number of ReadReq misses -system.l2c.ReadReq_misses::1 84 # number of ReadReq misses -system.l2c.ReadReq_misses::total 68164 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3905 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3905 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142426 # number of ReadExReq misses -system.l2c.demand_misses::0 210506 # number of demand (read+write) misses -system.l2c.demand_misses::1 84 # number of demand (read+write) misses -system.l2c.demand_misses::total 210590 # number of demand (read+write) misses -system.l2c.overall_misses::0 210506 # number of overall misses -system.l2c.overall_misses::1 84 # number of overall misses -system.l2c.overall_misses::total 210590 # number of overall misses -system.l2c.ReadReq_miss_latency 3574844000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 37228000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7453066500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 11027910500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 11027910500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2398408 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 145998 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2544406 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1599020 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1599020 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4248 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4248 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 292636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292636 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2691044 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 145998 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2837042 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2691044 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 145998 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2837042 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.028385 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000575 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028961 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.919256 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.486700 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078225 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000575 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.078800 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078225 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000575 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.078800 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52509.459459 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 42557666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42610176.126126 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 9533.418694 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11950.408174 # Average occupied blocks per context +system.l2c.occ_blocks::1 26389.378270 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182349 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.402670 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2335607 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145488 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2481095 # number of ReadReq hits +system.l2c.Writeback_hits::0 1594493 # number of Writeback hits +system.l2c.Writeback_hits::total 1594493 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 327 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 327 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150672 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150672 # number of ReadExReq hits +system.l2c.demand_hits::0 2486279 # number of demand (read+write) hits +system.l2c.demand_hits::1 145488 # number of demand (read+write) hits +system.l2c.demand_hits::total 2631767 # number of demand (read+write) hits +system.l2c.overall_hits::0 2486279 # number of overall hits +system.l2c.overall_hits::1 145488 # number of overall hits +system.l2c.overall_hits::total 2631767 # number of overall hits +system.l2c.ReadReq_misses::0 66850 # number of ReadReq misses +system.l2c.ReadReq_misses::1 109 # number of ReadReq misses +system.l2c.ReadReq_misses::total 66959 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3932 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3932 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142221 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142221 # number of ReadExReq misses +system.l2c.demand_misses::0 209071 # number of demand (read+write) misses +system.l2c.demand_misses::1 109 # number of demand (read+write) misses +system.l2c.demand_misses::total 209180 # number of demand (read+write) misses +system.l2c.overall_misses::0 209071 # number of overall misses +system.l2c.overall_misses::1 109 # number of overall misses +system.l2c.overall_misses::total 209180 # number of overall misses +system.l2c.ReadReq_miss_latency 3511861000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 38996000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7442399000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 10954260000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 10954260000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2402457 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145597 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2548054 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1594493 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1594493 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4259 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4259 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292893 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292893 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2695350 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145597 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2840947 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2695350 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145597 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2840947 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027826 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000749 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028574 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.923221 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.485573 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.077567 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000749 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078316 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.077567 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000749 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078316 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52533.448018 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 32218908.256881 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 32271441.704899 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 9917.599186 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52329.395616 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.817678 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52387.630281 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 131284648.809524 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 131337036.439805 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52387.630281 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 131284648.809524 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 131337036.439805 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52394.928039 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 100497798.165138 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 100550193.093176 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52394.928039 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 100497798.165138 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 100550193.093176 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,58 +100,58 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142550 # number of writebacks +system.l2c.writebacks 142631 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 68162 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3905 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142426 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 210588 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 210588 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 66957 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3932 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142221 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 209178 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 209178 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2743592500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 156565000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5717024500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8460617000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8460617000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61532546500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1222452000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62754998500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028420 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.466869 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.495289 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.919256 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2695362500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 157637000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5708607000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8403969500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8403969500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 59978490000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1230737500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 61209227500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027870 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.459879 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.487749 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.923221 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.486700 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.485573 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078255 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.442403 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.520658 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078255 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.442403 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.520658 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.077607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.436692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.514299 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.077607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.436692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.514299 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40255.126424 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40090.793489 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40138.987913 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40176.163363 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47572 # number of replacements -system.iocache.tagsinuse 0.146650 # Cycle average of tags in use +system.iocache.replacements 47573 # number of replacements +system.iocache.tagsinuse 0.195398 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994510051000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.146650 # Average occupied blocks per context -system.iocache.occ_percent::1 0.009166 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994542788000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.195398 # Average occupied blocks per context +system.iocache.occ_percent::1 0.012212 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits @@ -168,10 +168,10 @@ system.iocache.demand_misses::total 47627 # nu system.iocache.overall_misses::0 0 # number of overall misses system.iocache.overall_misses::1 47627 # number of overall misses system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency 113785932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6369912160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6483698092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6483698092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency 113669932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6372391160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6486061092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6486061092 # number of overall miss cycles system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) @@ -191,26 +191,26 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125453.067255 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125325.173098 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136342.297945 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136395.358733 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136134.925399 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136184.540114 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136134.925399 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136184.540114 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68669502 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68679532 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11251 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6098.534813 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6104.304684 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks +system.iocache.writebacks 46668 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses @@ -218,10 +218,10 @@ system.iocache.WriteReq_mshr_misses 46720 # nu system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 66598982 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3940155856 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4006754838 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4006754838 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66482982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3942637876 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4009120858 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4009120858 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,10 +235,10 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73299.869901 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84388.653168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84177.480379 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions @@ -255,140 +255,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 449021643 # number of cpu cycles simulated +system.cpu.numCycles 449878562 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 91138491 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 91138491 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1248082 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89857544 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83686998 # Number of BTB hits +system.cpu.BPredUnit.lookups 91189820 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91189820 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1250253 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 90006318 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83822675 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28288670 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 450771327 # Number of instructions fetch has processed -system.cpu.fetch.Branches 91138491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83686998 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 171087914 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6045536 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 191873 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82674920 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 54951 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9822160 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 542562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4016 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 287044907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.085924 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403637 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28390554 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 451032028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91189820 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83822675 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171638033 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6092005 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 127923 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 86885537 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36685 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 38090 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9866979 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 541048 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3553 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 291873782 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.039474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.398963 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 116472661 40.58% 40.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1490084 0.52% 41.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72800190 25.36% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1427390 0.50% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1806479 0.63% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3992507 1.39% 68.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1571582 0.55% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2063795 0.72% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85420219 29.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 120818032 41.39% 41.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1855546 0.64% 42.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72826244 24.95% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1422491 0.49% 67.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1829890 0.63% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4020066 1.38% 69.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1590838 0.55% 70.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1683069 0.58% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85827606 29.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 287044907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.202971 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.003897 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 33370892 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79040686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165533455 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4389968 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4709906 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 881886507 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 578 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4709906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37547254 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52554502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10077381 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165462513 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16693351 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 877383155 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14371 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11668719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2142745 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 879650717 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1723132927 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1723132383 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 544 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 843287047 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36363663 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 486686 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 487762 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43318784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19666821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10717044 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1121000 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1013044 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 870450598 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 900193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 866206507 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178001 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 30597956 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 44655599 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 144106 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 287044907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.017669 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373774 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 291873782 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.202699 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.002564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33589176 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83124342 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 166020087 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4383500 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4756677 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 883216023 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4756677 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37852860 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55892656 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9911063 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165583689 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 17876837 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 878703692 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12652 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12602978 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2126989 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 880098416 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1724229495 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1724229039 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843418783 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36679626 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 488930 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 489908 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 44000804 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19727758 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10753359 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1338256 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1089668 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870922009 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1727938 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 867227375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177419 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30993538 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45221667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 207753 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 291873782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.971241 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.381572 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 82633676 28.79% 28.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22379993 7.80% 36.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 14042555 4.89% 41.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9676323 3.37% 44.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79535811 27.71% 72.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5032653 1.75% 74.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72954170 25.42% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 636902 0.22% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152824 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 86148709 29.52% 29.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 24105973 8.26% 37.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 13574297 4.65% 42.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9676822 3.32% 45.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79595279 27.27% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5022101 1.72% 74.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72958833 25.00% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 636421 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 155347 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 287044907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 291873782 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 195893 8.77% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1841396 82.43% 91.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 196729 8.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202428 8.97% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1851752 82.02% 90.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 203495 9.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 302784 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830728417 95.90% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 306567 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 831752185 95.91% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued @@ -417,253 +418,253 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.94% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25630184 2.96% 98.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9545122 1.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25621043 2.95% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9547580 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 866206507 # Type of FU issued -system.cpu.iq.rate 1.929097 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2234018 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002579 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2022023513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 901959019 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 855369267 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 868137651 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1362479 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 867227375 # Type of FU issued +system.cpu.iq.rate 1.927692 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2257675 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002603 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2028918942 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 903653765 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 856397776 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 869178395 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 88 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1343949 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4321864 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17926 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2286443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4393917 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17180 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11337 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2321478 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817280 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 160300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817249 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160526 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4709906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33528904 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6021560 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 871350791 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 302780 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19666821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10717077 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 894230 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5567968 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 900317 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 526461 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1426778 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 864071451 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25139822 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2135055 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4756677 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34884624 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6122535 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 872649947 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 301193 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19727758 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10753386 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 894363 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5389997 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11337 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 906001 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524480 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1430481 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 865094857 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25131798 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2132517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34444060 # number of memory reference insts executed -system.cpu.iew.exec_branches 86704764 # Number of branches executed -system.cpu.iew.exec_stores 9304238 # Number of stores executed -system.cpu.iew.exec_rate 1.924343 # Inst execution rate -system.cpu.iew.wb_sent 863434483 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 855369319 # cumulative count of insts written-back -system.cpu.iew.wb_producers 671433691 # num instructions producing a value -system.cpu.iew.wb_consumers 1171953644 # num instructions consuming a value +system.cpu.iew.exec_refs 34436194 # number of memory reference insts executed +system.cpu.iew.exec_branches 86723634 # Number of branches executed +system.cpu.iew.exec_stores 9304396 # Number of stores executed +system.cpu.iew.exec_rate 1.922952 # Inst execution rate +system.cpu.iew.wb_sent 864455877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 856397826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671292665 # num instructions producing a value +system.cpu.iew.wb_consumers 1171999804 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.904962 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572918 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903620 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572775 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839904894 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 31338704 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 756085 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1254700 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 282350978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.974684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863709 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 840808469 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31735206 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1520183 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1254406 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 287133088 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.928288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.869814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102836465 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12523164 4.44% 40.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4697520 1.66% 42.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76975529 27.26% 69.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4042949 1.43% 71.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1857352 0.66% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1067382 0.38% 72.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71607681 25.36% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6742936 2.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 107529680 37.45% 37.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13316862 4.64% 42.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3946452 1.37% 43.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76651474 26.70% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4051645 1.41% 71.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1852261 0.65% 72.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1054561 0.37% 72.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71992194 25.07% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6737959 2.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 282350978 # Number of insts commited each cycle -system.cpu.commit.count 839904894 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 287133088 # Number of insts commited each cycle +system.cpu.commit.count 840808469 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23775588 # Number of memory references committed -system.cpu.commit.loads 15344954 # Number of loads committed -system.cpu.commit.membars 3541 # Number of memory barriers committed -system.cpu.commit.branches 85526796 # Number of branches committed +system.cpu.commit.refs 23765746 # Number of memory references committed +system.cpu.commit.loads 15333838 # Number of loads committed +system.cpu.commit.membars 781579 # Number of memory barriers committed +system.cpu.commit.branches 85539454 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768518485 # Number of committed integer instructions. +system.cpu.commit.int_insts 768627958 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6742936 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6737959 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1146769000 # The number of ROB reads -system.cpu.rob.rob_writes 1747209492 # The number of ROB writes -system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9841548887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 839904894 # Number of Instructions Simulated -system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated -system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.534610 # CPI: Total CPI of All Threads -system.cpu.ipc 1.870522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.870522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1407118516 # number of integer regfile reads -system.cpu.int_regfile_writes 857404874 # number of integer regfile writes -system.cpu.fp_regfile_reads 52 # number of floating regfile reads -system.cpu.misc_regfile_reads 282285829 # number of misc regfile reads -system.cpu.misc_regfile_writes 410057 # number of misc regfile writes -system.cpu.icache.replacements 1028866 # number of replacements -system.cpu.icache.tagsinuse 510.467349 # Cycle average of tags in use -system.cpu.icache.total_refs 8724446 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1029378 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.475454 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553290000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.467349 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8724446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8724446 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8724446 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1152856114 # The number of ROB reads +system.cpu.rob.rob_writes 1749856645 # The number of ROB writes +system.cpu.timesIdled 3066243 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 158004780 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9872474852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 840808469 # Number of Instructions Simulated +system.cpu.committedInsts_total 840808469 # Number of Instructions Simulated +system.cpu.cpi 0.535055 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.535055 # CPI: Total CPI of All Threads +system.cpu.ipc 1.868968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.868968 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407444841 # number of integer regfile reads +system.cpu.int_regfile_writes 857665866 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 282350765 # number of misc regfile reads +system.cpu.misc_regfile_writes 410137 # number of misc regfile writes +system.cpu.icache.replacements 1031767 # number of replacements +system.cpu.icache.tagsinuse 510.488308 # Cycle average of tags in use +system.cpu.icache.total_refs 8766017 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1032279 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.491907 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54591118000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.488308 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997047 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8766017 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8766017 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8766017 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8724446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8724446 # number of overall hits +system.cpu.icache.demand_hits::total 8766017 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8766017 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8724446 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1097711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1097711 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1097711 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8766017 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1100959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1100959 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1100959 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1097711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1097711 # number of overall misses +system.cpu.icache.demand_misses::total 1100959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1100959 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1097711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16447038991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16447038991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16447038991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9822157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9822157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9822157 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1100959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16475831488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16475831488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16475831488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9866976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9866976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9866976 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9822157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9822157 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9866976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9866976 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9822157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.111759 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.111759 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9866976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111580 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111580 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111759 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111580 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14983.031956 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14964.981882 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14983.031956 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14964.981882 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14983.031956 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14964.981882 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2545992 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2787490 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 258 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 276 # 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number of overall MSHR misses +system.cpu.icache.writebacks 1565 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 66134 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 66134 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 66134 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1034825 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1034825 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1034825 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12476028992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12476028992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12476028992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12496503490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12496503490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12496503490 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105061 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104878 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.105061 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.104878 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.105061 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.104878 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12090.065734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12075.958244 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12075.958244 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12075.958244 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # 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number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 9699 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9699 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 15025 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15025 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 9699 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9699 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 15025 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15025 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 189764500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 189764500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 189764500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 41598 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41598 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 9699 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9699 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 124296000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 124296000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 124296000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 36333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 36333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 41601 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41601 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 36336 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 36336 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 41601 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41601 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.361195 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 36336 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 36336 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.266947 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.361169 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.266925 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.361169 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.266925 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12629.916805 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12815.341788 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12629.916805 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12815.341788 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12629.916805 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12815.341788 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -673,83 +674,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2705 # number of writebacks +system.cpu.itb_walker_cache.writebacks 1368 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 15025 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 15025 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 15025 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 9699 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 9699 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 9699 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 144320000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 144320000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 144320000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 94849000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 94849000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 94849000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.361195 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.266947 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.361169 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.266925 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.361169 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.266925 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9605.324459 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9779.255593 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9779.255593 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9779.255593 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 144708 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.855241 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 146935 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 144723 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.015284 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934458000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.855241 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.865953 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 147187 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 147187 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 145081 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.868389 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 150553 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 145096 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.037610 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5102657828000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.868389 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.866774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 150554 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 150554 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 147187 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 147187 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 150554 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 150554 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 147187 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 147187 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 145638 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 145638 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 150554 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 150554 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 146024 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 146024 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 145638 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 145638 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 146024 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 146024 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 145638 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 145638 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 2011660500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 2011660500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 2011660500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 292825 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 292825 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 146024 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 146024 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 2047200500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 2047200500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 2047200500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 296578 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 296578 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 292825 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 292825 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 296578 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 296578 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 292825 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 292825 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.497355 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 296578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 296578 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.492363 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.497355 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.492363 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.497355 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.492363 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13812.744613 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14019.616638 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13812.744613 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14019.616638 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13812.744613 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14019.616638 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -759,136 +760,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 46772 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 42577 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 145638 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 145638 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 145638 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 146024 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 146024 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 146024 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1570780000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1570780000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1570780000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1605163000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1605163000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1605163000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.497355 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.492363 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.497355 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.492363 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.497355 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.492363 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10785.509276 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10992.460144 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10992.460144 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10992.460144 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1661747 # number of replacements -system.cpu.dcache.tagsinuse 511.998367 # Cycle average of tags in use -system.cpu.dcache.total_refs 17960054 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1662259 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.804606 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1663087 # number of replacements +system.cpu.dcache.tagsinuse 511.997625 # Cycle average of tags in use +system.cpu.dcache.total_refs 17982371 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1663599 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.809318 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998367 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11390626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11390626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6547450 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6547450 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17938076 # number of demand (read+write) hits +system.cpu.dcache.occ_blocks::0 511.997625 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11413167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11413167 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6547162 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6547162 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17960329 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17938076 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17938076 # number of overall hits +system.cpu.dcache.demand_hits::total 17960329 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17960329 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17938076 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2490346 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2490346 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1873884 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1873884 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4364230 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17960329 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2492340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2492340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1875398 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1875398 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4367738 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4364230 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4364230 # number of overall misses +system.cpu.dcache.demand_misses::total 4367738 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4367738 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4364230 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 37598789500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63471421475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 101070210975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 101070210975 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13880972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13880972 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8421334 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8421334 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22302306 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4367738 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37542071500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63453033216 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 100995104716 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 100995104716 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13905507 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13905507 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8422560 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8422560 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22328067 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22302306 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22302306 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22328067 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22328067 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22302306 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.179407 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222516 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.195685 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22328067 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.179234 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222664 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.195616 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.195685 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.195616 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15062.981576 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33834.435792 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23158.772790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23122.976863 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23158.772790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23122.976863 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1083244649 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6672500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73213 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1083233153 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6672000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73547 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14728.447836 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17063.938619 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1547981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1120147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1577106 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2697253 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2697253 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1370199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 296778 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1666977 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1666977 # number of overall MSHR misses +system.cpu.dcache.writebacks 1548983 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1121085 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1578340 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2699425 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2699425 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1371255 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 297058 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1668313 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1668313 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18186929000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9757421649 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27944350649 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27944350649 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947016500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1386048000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88333064500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098711 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18154950000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9754920653 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27909870653 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27909870653 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85210888500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1394917000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 86605805500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098612 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035241 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.074745 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074718 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.074745 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074718 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13239.660019 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32838.437790 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16729.397093 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 85136ebe7..6570dc326 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -23,7 +23,7 @@ Built 1 zonelists. Total pages: 30458 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.004 MHz processor.
+time.c: Detected 2000.000 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812511
+result 7812497
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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