diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/long/10.linux-boot | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/long/10.linux-boot')
7 files changed, 1483 insertions, 1483 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 803aca1ba..035a139c8 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -660,7 +660,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -680,7 +680,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -806,7 +806,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index f51a48835..cde3a8c1f 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,6 +2,6 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: 125740500: Trying to launch CPU number 1! +warn: 125751000: Trying to launch CPU number 1! For more information see: http://www.m5sim.org/warn/8f7d2563 hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index dc5374eea..fa47c5c0e 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:36:15 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:36:17 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1907705384500 because m5_exit instruction encountered +Exiting @ tick 1907689250500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5561f4961..3e4d779fa 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,447 +1,447 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 126888 # Simulator instruction rate (inst/s) -host_mem_usage 280000 # Number of bytes of host memory used -host_seconds 442.84 # Real time elapsed on the host -host_tick_rate 4307932213 # Simulator tick rate (ticks/s) +host_inst_rate 123563 # Simulator instruction rate (inst/s) +host_mem_usage 293920 # Number of bytes of host memory used +host_seconds 454.60 # Real time elapsed on the host +host_tick_rate 4196424819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56190549 # Number of instructions simulated -sim_seconds 1.907705 # Number of seconds simulated -sim_ticks 1907705384500 # Number of ticks simulated +sim_insts 56171530 # Number of instructions simulated +sim_seconds 1.907689 # Number of seconds simulated +sim_ticks 1907689250500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 4976194 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 9270305 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 8475185 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 10093433 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 5979895 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670392 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5124021 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 9548324 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 25931 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 576265 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 8953132 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 10665388 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 730260 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 6306789 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 727470 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 69432713 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.574171 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.330726 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 73665183 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.571097 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 52133999 75.09% 75.09% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 7662367 11.04% 86.12% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 4443977 6.40% 92.52% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 2023862 2.91% 95.44% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 1473823 2.12% 97.56% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 453845 0.65% 98.21% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 276436 0.40% 98.61% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 294012 0.42% 99.03% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 670392 0.97% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 55454240 75.28% 75.28% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 8064036 10.95% 86.23% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 4660922 6.33% 92.55% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 2129949 2.89% 95.44% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 1559149 2.12% 97.56% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 477103 0.65% 98.21% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 293859 0.40% 98.61% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 298455 0.41% 99.01% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 69432713 # Number of insts commited each cycle -system.cpu0.commit.COM:count 39866260 # Number of instructions committed -system.cpu0.commit.COM:loads 6404474 # Number of loads committed -system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed -system.cpu0.commit.COM:refs 10831640 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 73665183 # Number of insts commited each cycle +system.cpu0.commit.COM:count 42069937 # Number of instructions committed +system.cpu0.commit.COM:loads 6784715 # Number of loads committed +system.cpu0.commit.COM:membars 161083 # Number of memory barriers committed +system.cpu0.commit.COM:refs 11506692 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6218733 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 37660679 # Number of Instructions Simulated -system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated -system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 147686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15414.654688 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 548150 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 42069937 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 486094 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6570892 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 39732534 # Number of Instructions Simulated +system.cpu0.committedInsts_total 39732534 # Number of Instructions Simulated +system.cpu0.cpi 2.659989 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.659989 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 157022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15337.494650 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 135219 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135219 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.084416 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 12467 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12467 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.062680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11734.631539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 143004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 215001000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.089274 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 14018 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 14018 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3542 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 122932000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.066717 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 6414671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6414671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 28975.322669 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 10476 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 6796922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6796922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 28045.834026 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.577320 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27628.067292 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 5468114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5468114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27426794500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.147561 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 946557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 946557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250848 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19979077000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.108456 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 5780701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5780701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 28500765500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.149512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1016221 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1016221 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 272772 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 20540059000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109380 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54668.039693 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 743449 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639143000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 165236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 165236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54890.406800 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51668.039693 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875946000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.102350 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827877000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.102350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51890.406800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 147119 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147119 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 994449500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.109643 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 18117 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18117 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 940098500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.109643 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 48857.609099 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 18117 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 4544003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4544003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 48917.848661 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.542507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54316.339615 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80387818274 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.386408 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1645349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1645349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269947736 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066495 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 2781940 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2781940 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 86196331165 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.387778 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1762063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1762063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1458631 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 16481315562 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066776 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050789497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9307.081114 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224233 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 116343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 1082813738 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 303432 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1049908497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9537.404034 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.143990 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 120871 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 1152795563 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 10672732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 11340925 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10672732 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 41596.652338 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 11340925 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 41283.431307 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 8080826 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 8562641 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8080826 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107814612774 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.242853 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 8562641 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 114697096665 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.244979 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2591906 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2778284 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2591906 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613056 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35249024736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091715 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2778284 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1731403 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 37021374562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.092310 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1046881 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.863629 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 442.178159 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 10672732 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.870622 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 445.758667 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 11340925 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10672732 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 41596.652338 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 11340925 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 41283.431307 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 8080826 # number of overall hits +system.cpu0.dcache.overall_hits::0 8562641 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 8080826 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107814612774 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.242853 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 8562641 # number of overall hits +system.cpu0.dcache.overall_miss_latency 114697096665 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.244979 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2591906 # number of overall misses +system.cpu0.dcache.overall_misses::0 2778284 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2591906 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613056 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35249024736 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091715 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2778284 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1731403 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 37021374562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.092310 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690651997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1046881 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1689051497 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 922726 # number of replacements -system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 987239 # number of replacements +system.cpu0.dcache.sampled_refs 987751 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8515102 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 297339 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33638519 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401378 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50930123 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25726073 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9143955 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1094070 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 812672 # DTB accesses -system.cpu0.dtb.data_acv 801 # DTB access violations -system.cpu0.dtb.data_hits 11625422 # DTB hits -system.cpu0.dtb.data_misses 28525 # DTB misses +system.cpu0.dcache.tagsinuse 445.758667 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9031985 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 319854 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 35782513 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 28650 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 428056 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 53705173 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 27333196 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9585932 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1147003 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 91050 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 963541 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 873282 # DTB accesses +system.cpu0.dtb.data_acv 817 # DTB access violations +system.cpu0.dtb.data_hits 12339819 # DTB hits +system.cpu0.dtb.data_misses 31654 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 605265 # DTB read accesses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7063658 # DTB read hits -system.cpu0.dtb.read_misses 24056 # DTB read misses -system.cpu0.dtb.write_accesses 207407 # DTB write accesses -system.cpu0.dtb.write_acv 205 # DTB write access violations -system.cpu0.dtb.write_hits 4561764 # DTB write hits -system.cpu0.dtb.write_misses 4469 # DTB write misses -system.cpu0.fetch.Branches 10093433 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456937 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16710986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292610 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 52006541 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660337 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456937 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5666568 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 70526783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.737401 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.023896 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 648811 # DTB read accesses +system.cpu0.dtb.read_acv 602 # DTB read access violations +system.cpu0.dtb.read_hits 7477600 # DTB read hits +system.cpu0.dtb.read_misses 25745 # DTB read misses +system.cpu0.dtb.write_accesses 224471 # DTB write accesses +system.cpu0.dtb.write_acv 215 # DTB write access violations +system.cpu0.dtb.write_hits 4862219 # DTB write hits +system.cpu0.dtb.write_misses 5909 # DTB write misses +system.cpu0.fetch.Branches 10665388 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6760263 # Number of cache lines fetched +system.cpu0.fetch.Cycles 17500096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 314893 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 54825819 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 690026 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100914 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6760263 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5854281 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.518751 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 74812186 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.732846 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.023907 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 60303519 85.50% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 761816 1.08% 86.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 1433855 2.03% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 636077 0.90% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2329701 3.30% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 474692 0.67% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 552515 0.78% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 815434 1.16% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3219174 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3444071 4.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 70526783 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 6456937 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6456937 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15194.125887 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 74812186 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 6760263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6760263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15111.361670 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 5806694 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5806694 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9879873999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.100705 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 650243 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 650243 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526063499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.096077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12055.592401 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6055842 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6055842 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 10644760499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.104200 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 704421 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 704421 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 31973 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 8106758999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.099471 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11808.794118 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 672448 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11292.658537 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.361634 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.icache.avg_refs 9.007622 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 401499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 462999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 6456937 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 6760263 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6456937 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15194.125887 # average overall miss latency +system.cpu0.icache.demand_accesses::total 6760263 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15111.361670 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 5806694 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6055842 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5806694 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9879873999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.100705 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6055842 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 10644760499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.104200 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 650243 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 704421 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 650243 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526063499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.096077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 704421 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 31973 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 8106758999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.099471 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 672448 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995760 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.829037 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 6456937 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995774 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.836147 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 6760263 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6456937 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15194.125887 # average overall miss latency +system.cpu0.icache.overall_accesses::total 6760263 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15111.361670 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 5806694 # number of overall hits +system.cpu0.icache.overall_hits::0 6055842 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5806694 # number of overall hits -system.cpu0.icache.overall_miss_latency 9879873999 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.100705 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6055842 # number of overall hits +system.cpu0.icache.overall_miss_latency 10644760499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.104200 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 650243 # number of overall misses +system.cpu0.icache.overall_misses::0 704421 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 650243 # number of overall misses -system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526063499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.096077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 704421 # number of overall misses +system.cpu0.icache.overall_mshr_hits 31973 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 8106758999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.099471 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 672448 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 619753 # number of replacements -system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 671790 # number of replacements +system.cpu0.icache.sampled_refs 672302 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806694 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 509.836147 # Cycle average of tags in use +system.cpu0.icache.total_refs 6055842 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25289603000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30375240 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436261 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512857 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402648 # Inst execution rate -system.cpu0.iew.EXEC:refs 11740586 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575950 # Number of stores executed +system.cpu0.idleCycles 30875932 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6794464 # Number of branches executed +system.cpu0.iew.EXEC:nop 2650714 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.405657 # Inst execution rate +system.cpu0.iew.EXEC:refs 12475412 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4878585 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24161341 # num instructions consuming a value -system.cpu0.iew.WB:count 40226053 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back +system.cpu0.iew.WB:consumers 25547065 # num instructions consuming a value +system.cpu0.iew.WB:count 42445288 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.775506 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18823082 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398664 # insts written-back per cycle -system.cpu0.iew.WB:sent 40293911 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7178019 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7553743 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4836003 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46191057 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7164636 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359402 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40627967 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33758 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 19811901 # num instructions producing a value +system.cpu0.iew.WB:rate 0.401609 # insts written-back per cycle +system.cpu0.iew.WB:sent 42518285 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 591859 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7490199 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 8008916 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1306307 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 773924 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5151785 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 48752960 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7596827 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 385648 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 42873082 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 34285 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1094070 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 4894 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1147003 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 462624 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 256589 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 371728 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8138 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 34087 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12236 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1149269 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408837 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 34087 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3326 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 28267868 68.97% 68.98% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 42211 0.10% 69.08% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 12076 0.03% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1657 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 7398159 18.05% 87.16% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4612021 11.25% 98.41% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 650051 1.59% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 36722 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12836 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1224201 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 429808 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 36722 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 290524 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 301335 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.375941 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.375941 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 29744442 68.76% 68.77% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 44172 0.10% 68.87% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 13702 0.03% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1883 0.00% 68.91% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.91% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 7844859 18.13% 87.04% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4914921 11.36% 98.40% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 690973 1.60% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 40987369 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 290458 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 43258732 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 310534 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007179 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 33502 11.53% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 185621 63.91% 75.44% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 71335 24.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 34104 10.98% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 200961 64.71% 75.70% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 75469 24.30% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526783 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581160 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133092 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 74812186 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.578231 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.135171 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764700 70.56% 70.56% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507721 14.90% 85.46% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625277 6.56% 92.02% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839073 4.03% 96.04% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729944 2.45% 98.50% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663617 0.94% 99.44% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315224 0.45% 99.88% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67146 0.10% 99.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 14081 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 52955077 70.78% 70.78% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 11074556 14.80% 85.59% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4848896 6.48% 92.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2948908 3.94% 96.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1827398 2.44% 98.45% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 727506 0.97% 99.43% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 332197 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 81828 0.11% 99.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 15820 0.02% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 70526783 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42280479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40987369 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5737875 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23380 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3058582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 74812186 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.409306 # Inst issue rate +system.cpu0.iq.iqInstsAdded 44617182 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 43258732 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1485064 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6087251 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24441 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 998970 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3229124 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 875811 # ITB accesses -system.cpu0.itb.fetch_acv 900 # ITB acv -system.cpu0.itb.fetch_hits 845925 # ITB hits -system.cpu0.itb.fetch_misses 29886 # ITB misses +system.cpu0.itb.fetch_accesses 930014 # ITB accesses +system.cpu0.itb.fetch_acv 893 # ITB acv +system.cpu0.itb.fetch_hits 898869 # ITB hits +system.cpu0.itb.fetch_misses 31145 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -452,551 +452,549 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wripir 96 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2410 1.86% 1.94% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116005 89.53% 91.51% # number of callpals executed -system.cpu0.kern.callpal::rdps 6357 4.91% 96.41% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.41% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal::rti 4116 3.18% 99.60% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.29% 99.90% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 129578 # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2652 1.92% 1.99% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 2.03% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 2.04% # number of callpals executed +system.cpu0.kern.callpal::swpipl 124030 89.84% 91.88% # number of callpals executed +system.cpu0.kern.callpal::rdps 6358 4.61% 96.48% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.48% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.49% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.49% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.50% # number of callpals executed +system.cpu0.kern.callpal::rti 4305 3.12% 99.61% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.29% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 138052 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 47763 39.05% 39.05% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1931 1.58% 40.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72358 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122308 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96397 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1871606920000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 101495000 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398001000 0.02% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35173046500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907288793500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986391 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 153418 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4853 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 51417 39.39% 39.39% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.18% 39.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1931 1.48% 41.06% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.07% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 76919 58.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 130520 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 50665 48.95% 48.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.23% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1931 1.87% 51.05% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 50649 48.94% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 103498 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1871325988500 98.09% 98.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 101211000 0.01% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398014500 0.02% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8513500 0.00% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35854604500 1.88% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907688332000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985374 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.650889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.ipl_used::31 0.658472 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6220 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.217679 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.220257 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2121516000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1905422249500 99.88% 99.88% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2266074500 0.12% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2411 # number of times the context was actually changed -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2050556 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1832562 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 7553743 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4836003 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 100902023 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10627685 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742850 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930386 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58880297 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48158408 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32535845 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9104791 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1094070 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612728 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5197934 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19157121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536823 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.kern.swap_context 2653 # number of times the context was actually changed +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2188476 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1997712 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 8008916 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5151785 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 105688118 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 11112209 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 28779848 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 792454 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 28590888 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1753238 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16675 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 62049686 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 50763826 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 34216131 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9514762 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1147003 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3857610 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5436281 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 20589712 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1236784 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 9152277 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 192000 # count of temporary serializing insts renamed +system.cpu0.timesIdled 961954 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 2271371 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 5052294 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 5538388 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 417428 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 2947825 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1953599 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 4355656 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 14923 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 286606 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 4049478 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 4938226 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 376891 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 2617539 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 356362 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 37477420 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.524684 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.336555 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 33118489 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.526612 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.338198 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 29419430 78.50% 78.50% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 3577485 9.55% 88.04% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 1728132 4.61% 92.66% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 1049887 2.80% 95.46% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 708572 1.89% 97.35% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 265966 0.71% 98.06% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 180885 0.48% 98.54% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 145537 0.39% 98.93% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 401526 1.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 25969028 78.41% 78.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 3179753 9.60% 88.01% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 1522948 4.60% 92.61% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 936064 2.83% 95.44% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 628296 1.90% 97.34% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 237537 0.72% 98.05% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 164527 0.50% 98.55% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 123974 0.37% 98.92% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 356362 1.08% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 37477420 # Number of insts commited each cycle -system.cpu1.commit.COM:count 19663805 # Number of instructions committed -system.cpu1.commit.COM:loads 3551077 # Number of loads committed -system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5861573 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 33118489 # Number of insts commited each cycle +system.cpu1.commit.COM:count 17440586 # Number of instructions committed +system.cpu1.commit.COM:loads 3166581 # Number of loads committed +system.cpu1.commit.COM:membars 77258 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5179825 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3737019 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 18529870 # Number of Instructions Simulated -system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated -system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 72126 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72126 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14445.783133 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 272102 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 17440586 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 227930 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3329840 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 16438996 # Number of Instructions Simulated +system.cpu1.committedInsts_total 16438996 # Number of Instructions Simulated +system.cpu1.cpi 2.304097 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.304097 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 63271 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 63271 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14821.069300 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 59842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 177452000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.170313 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 12284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.142362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11124.971610 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 52535 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 52535 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 159119000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.169683 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 10736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 1930 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97966500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.139179 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 3589394 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3589394 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15546.336868 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 8806 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 3203716 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3203716 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15842.853412 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12022.349090 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12100.517465 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 2947184 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2947184 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9984013000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.178919 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 642210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 642210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5182462000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120095 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 2644617 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2644617 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 8857723500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.174516 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 559099 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 559099 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 185547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 4520172500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.116600 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298578500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 68169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 68169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54676.100066 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 373552 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298583500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 59498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54415.622389 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 51420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 51420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 915770000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.245698 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 16749 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 16749 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.245698 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51415.622389 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 45134 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45134 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 781626000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.241420 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 14364 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 14364 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 738534000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.241420 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 49366.459666 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 14364 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1946502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1946502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 49498.272766 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.809571 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54160.909528 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34266839381 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.310589 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 694132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 694132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7735954636 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.063808 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1381655 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1381655 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 27958950877 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.290186 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 564847 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 564847 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 446490 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 6410322769 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.060805 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526038500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13994.026145 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.879077 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 31364 # number of cycles access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 118357 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526362000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13351.888091 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 9.264017 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 24797 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 438908636 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 331086769 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18500 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 5824280 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 5150218 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5824280 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 33113.418856 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 5150218 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 32756.622095 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 4487938 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 4026272 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4487938 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44250852381 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.229443 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 4026272 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 36816674377 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.218233 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 1336342 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 1123946 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1336342 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12918416636 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.098497 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 1123946 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 632037 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 10930495269 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.095512 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 491909 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.953247 # Average percentage of cache occupancy -system.cpu1.dcache.occ_%::1 -0.003823 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 488.062339 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -1.957577 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 5824280 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.951616 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 487.227171 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 5150218 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5824280 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 33113.418856 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 5150218 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 32756.622095 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 4487938 # number of overall hits +system.cpu1.dcache.overall_hits::0 4026272 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 4487938 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44250852381 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.229443 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 4026272 # number of overall hits +system.cpu1.dcache.overall_miss_latency 36816674377 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.218233 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 1336342 # number of overall misses +system.cpu1.dcache.overall_misses::0 1123946 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1336342 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12918416636 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.098497 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 1123946 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 632037 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 10930495269 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.095512 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 824617000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 491909 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 824945500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 531784 # number of replacements -system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 455363 # number of replacements +system.cpu1.dcache.sampled_refs 455691 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4726297 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39405720000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 158239 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17789619 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 246499 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26253455 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14731428 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4724231 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641523 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 433929 # DTB accesses -system.cpu1.dtb.data_acv 77 # DTB access violations -system.cpu1.dtb.data_hits 6280304 # DTB hits -system.cpu1.dtb.data_misses 17153 # DTB misses +system.cpu1.dcache.tagsinuse 487.227171 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4221529 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 41371153000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 131807 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 15690044 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 15658 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 221514 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 23293804 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 13052984 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4174567 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 566096 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 47077 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 200893 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 379955 # DTB accesses +system.cpu1.dtb.data_acv 65 # DTB access violations +system.cpu1.dtb.data_hits 5542909 # DTB hits +system.cpu1.dtb.data_misses 13981 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 314117 # DTB read accesses -system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3872751 # DTB read hits -system.cpu1.dtb.read_misses 13436 # DTB read misses -system.cpu1.dtb.write_accesses 119812 # DTB write accesses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_hits 2407553 # DTB write hits -system.cpu1.dtb.write_misses 3717 # DTB write misses -system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8137045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192731 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26826558 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373512 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626137 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 38118943 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.703759 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.021088 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 276518 # DTB read accesses +system.cpu1.dtb.read_acv 12 # DTB read access violations +system.cpu1.dtb.read_hits 3445692 # DTB read hits +system.cpu1.dtb.read_misses 11718 # DTB read misses +system.cpu1.dtb.write_accesses 103437 # DTB write accesses +system.cpu1.dtb.write_acv 53 # DTB write access violations +system.cpu1.dtb.write_hits 2097217 # DTB write hits +system.cpu1.dtb.write_misses 2263 # DTB write misses +system.cpu1.fetch.Branches 4938226 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 2741713 # Number of cache lines fetched +system.cpu1.fetch.Cycles 7194016 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 172775 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 23780795 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 326197 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.130375 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 2741713 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2330490 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.627842 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 33684585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.705985 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.028331 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 33077920 86.78% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 338218 0.89% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 684572 1.80% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 401329 1.05% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 792382 2.08% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 254420 0.67% 93.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 341251 0.90% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 404733 1.06% 95.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1824118 4.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1644698 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 38118943 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14554.957905 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 33684585 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 2741713 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2741713 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14618.155893 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.745633 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6813626999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 468131 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 468131 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5189282500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.144757 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11660.018500 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 2328949 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2328949 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6033848499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.150550 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 412764 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 412764 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 18169 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 4600985000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143923 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 394595 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11340.909091 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.902933 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 249500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 3089103 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 2741713 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 3089103 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14554.957905 # average overall miss latency +system.cpu1.icache.demand_accesses::total 2741713 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14618.155893 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 2620972 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 2328949 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2620972 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6813626999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 2328949 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6033848499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.150550 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 468131 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 412764 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 468131 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5189282500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.144757 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 412764 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 18169 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 4600985000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.143923 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 394595 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.985305 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 504.476148 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 3089103 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.984930 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 504.284109 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 2741713 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 3089103 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14554.957905 # average overall miss latency +system.cpu1.icache.overall_accesses::total 2741713 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14618.155893 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 2620972 # number of overall hits +system.cpu1.icache.overall_hits::0 2328949 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 2620972 # number of overall hits -system.cpu1.icache.overall_miss_latency 6813626999 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 2328949 # number of overall hits +system.cpu1.icache.overall_miss_latency 6033848499 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.150550 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 468131 # number of overall misses +system.cpu1.icache.overall_misses::0 412764 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 468131 # number of overall misses -system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5189282500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.144757 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 412764 # number of overall misses +system.cpu1.icache.overall_mshr_hits 18169 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 4600985000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.143923 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 394595 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 446606 # number of replacements -system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 394030 # number of replacements +system.cpu1.icache.sampled_refs 394541 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.476148 # Cycle average of tags in use -system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 504.284109 # Cycle average of tags in use +system.cpu1.icache.total_refs 2328949 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 54145022000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4725629 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3215720 # Number of branches executed -system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474690 # Inst execution rate -system.cpu1.iew.EXEC:refs 6453151 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2418978 # Number of stores executed +system.cpu1.idleCycles 4192462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 2856676 # Number of branches executed +system.cpu1.iew.EXEC:nop 1154303 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.475940 # Inst execution rate +system.cpu1.iew.EXEC:refs 5695199 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2106410 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12377931 # num instructions consuming a value -system.cpu1.iew.WB:count 20081292 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731656 # average fanout of values written-back +system.cpu1.iew.WB:consumers 11059026 # num instructions consuming a value +system.cpu1.iew.WB:count 17811363 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.729393 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9056386 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468701 # insts written-back per cycle -system.cpu1.iew.WB:sent 20123893 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2501197 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4247431 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2557372 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23476845 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4034173 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 224909 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20337896 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 8066373 # num instructions producing a value +system.cpu1.iew.WB:rate 0.470242 # insts written-back per cycle +system.cpu1.iew.WB:sent 17846809 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 295481 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2247167 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 3784809 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 705322 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 304722 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2229881 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 20840957 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 3588789 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 201614 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 18027204 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 12484 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641523 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 2361 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 566096 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 83136 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 73212 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 122514 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7643 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 696354 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246876 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18287 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3984 0.02% 0.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 13476075 65.54% 65.56% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 28965 0.14% 65.70% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.70% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 13702 0.07% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.01% 65.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 4173782 20.30% 86.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2443072 11.88% 97.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 421241 2.05% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 16678 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 6458 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 618228 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 216637 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 16678 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 152685 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 142796 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.434009 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.434009 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3528 0.02% 0.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 11967153 65.65% 65.67% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 27009 0.15% 65.82% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.82% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 12064 0.07% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.01% 65.89% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.89% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 3711124 20.36% 86.25% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2127008 11.67% 97.92% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 379173 2.08% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 20562807 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 221150 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010755 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 18228818 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 196946 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010804 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 16139 7.30% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 131899 59.64% 66.94% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 73112 33.06% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 13962 7.09% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 116519 59.16% 66.25% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 66465 33.75% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118943 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539438 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158785 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 33684585 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.541162 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.162170 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405834 74.52% 74.52% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664798 12.24% 86.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989487 5.22% 91.98% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362185 3.57% 95.55% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979454 2.57% 98.12% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465472 1.22% 99.34% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186874 0.49% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52652 0.14% 99.97% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 12187 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 25088136 74.48% 74.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4124812 12.25% 86.72% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1756786 5.22% 91.94% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1209447 3.59% 95.53% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 865609 2.57% 98.10% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 413218 1.23% 99.33% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 164057 0.49% 99.81% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 50935 0.15% 99.97% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 11585 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 38118943 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.479940 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21283926 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20562807 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3483517 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16728 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1775091 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 33684585 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.481263 # Inst issue rate +system.cpu1.iq.iqInstsAdded 18897687 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 18228818 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 788967 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3125649 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 15583 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 561037 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1602623 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 525294 # ITB accesses -system.cpu1.itb.fetch_acv 109 # ITB acv -system.cpu1.itb.fetch_hits 518481 # ITB hits -system.cpu1.itb.fetch_misses 6813 # ITB misses +system.cpu1.itb.fetch_accesses 472041 # ITB accesses +system.cpu1.itb.fetch_acv 106 # ITB acv +system.cpu1.itb.fetch_hits 466299 # ITB hits +system.cpu1.itb.fetch_misses 5742 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1006,95 +1004,95 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1838 2.10% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 79684 91.22% 93.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2408 2.76% 96.11% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.11% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal::rti 3206 3.67% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.16% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1586 2.01% 2.04% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.04% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.05% # number of callpals executed +system.cpu1.kern.callpal::swpipl 71639 90.87% 92.92% # number of callpals executed +system.cpu1.kern.callpal::rdps 2407 3.05% 95.97% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.97% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 95.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.98% # number of callpals executed +system.cpu1.kern.callpal::rti 3007 3.81% 99.79% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.15% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 87355 # number of callpals executed +system.cpu1.kern.callpal::total 78839 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 34143 40.21% 40.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 2.27% 42.48% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48748 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 84915 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 68760 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871986905500 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 352078000 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 40004500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 35325543000 1.85% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907704531000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978707 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 84815 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3812 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 30474 39.75% 39.75% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 2.51% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 96 0.13% 42.39% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 44173 57.61% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 76671 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 29849 48.44% 48.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 3.13% 51.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 96 0.16% 51.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 29753 48.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 61626 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872267971000 98.16% 98.16% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 351911000 0.02% 98.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 40319500 0.00% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 34610873000 1.81% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907271074500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979491 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683515 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 521 -system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.ipl_used::31 0.673556 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 424 +system.cpu1.kern.mode_good::user 366 system.cpu1.kern.mode_good::idle 58 -system.cpu1.kern.mode_switch::kernel 2305 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.226030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::kernel 1953 # number of protection mode switches +system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.217102 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.254532 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1015923000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1839 # number of times the context was actually changed -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 906343 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 817120 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 4247431 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2557372 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 42844572 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3655833 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15199726 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29419521 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24525143 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16182603 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4333690 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641523 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2990949 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12476159 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.kern.mode_switch_good::idle 0.028473 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.245575 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 44394454000 2.33% 2.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 886105500 0.05% 2.37% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1861549295500 97.63% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1587 # number of times the context was actually changed +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 820507 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 719564 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 3784809 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2229881 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 37877047 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3238650 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 11736980 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 293624 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 13473240 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 554151 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 942 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 26045586 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 21738411 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 14384581 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 3820320 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 566096 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1590671 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2647601 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 10995606 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 652471 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4381532 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 75403 # count of temporary serializing insts renamed +system.cpu1.timesIdled 422616 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1107,262 +1105,262 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115331.417143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115252.862069 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20182998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63252.862069 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20053998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11082998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11005998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137844.166490 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137849.677657 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5727700806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85846.237437 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727929806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3567082858 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6165.982406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6166.374068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64483844 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64487940 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137749.749658 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137755.447539 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5747883804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747983804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3577930772 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3578088856 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.024239 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.387817 # Average occupied blocks per context +system.iocache.occ_%::1 0.028124 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.449991 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137749.749658 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137755.447539 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747983804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3577930772 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3578088856 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41697 # number of replacements -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.replacements 41696 # number of replacements +system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.387817 # Cycle average of tags in use +system.iocache.tagsinuse 0.449991 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1717168496000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses::0 221647 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 95855 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 317502 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 75026.275109 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 173484.417078 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 236243 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 78291 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 314534 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 69731.847293 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 210415.766819 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.037770 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629348799 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.604332 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16473660800 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 221647 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 95855 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 317502 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770894938 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.432467 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 3.312315 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 236243 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 78291 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 314534 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12649803961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.331400 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 4.017499 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1321671 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 883108 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2204779 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 53351.845432 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2020931.340670 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 314534 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1423603 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 771316 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2194919 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 53400.832785 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1985457.471546 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39977.821348 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39990.811057 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1018788 # number of ReadReq hits -system.l2c.ReadReq_hits::1 875112 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1893900 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159367000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.229167 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.009054 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 302883 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7996 # number of ReadReq misses -system.l2c.ReadReq_misses::total 310879 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12427585500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.235204 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.352009 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1119803 # number of ReadReq hits +system.l2c.ReadReq_hits::1 763145 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882948 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16223173000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.213402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.010594 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 303800 # number of ReadReq misses +system.l2c.ReadReq_misses::1 8171 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311971 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12475173500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.219128 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.404440 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310862 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 78396 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 63553 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 141949 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 92463.818205 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 114059.029346 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 86460 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 54412 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 140872 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 83177.133796 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 132167.444461 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.290548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40094.049918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7191494988 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 78396 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 63553 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 141949 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691202500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.810666 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.233553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 86460 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 54412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 140872 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5648129000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.629331 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.588988 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 140872 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1423763998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 455578 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 455578 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 455578 # number of Writeback hits -system.l2c.Writeback_hits::total 455578 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 451661 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 451661 # number of Writeback hits +system.l2c.Writeback_hits::total 451661 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. +system.l2c.avg_refs 4.797703 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 1543318 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 978963 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 1659846 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 849607 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2522281 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 62510.658683 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 315728.455181 # average overall miss latency +system.l2c.demand_accesses::total 2509453 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 60544.871057 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 378164.208554 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency -system.l2c.demand_hits::0 1018788 # number of demand (read+write) hits -system.l2c.demand_hits::1 875112 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency +system.l2c.demand_hits::0 1119803 # number of demand (read+write) hits +system.l2c.demand_hits::1 763145 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1893900 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788715799 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.339872 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.106083 # miss rate for demand accesses +system.l2c.demand_hits::total 1882948 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32696833800 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.325357 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.101767 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 524530 # number of demand (read+write) misses -system.l2c.demand_misses::1 103851 # number of demand (read+write) misses +system.l2c.demand_misses::0 540043 # number of demand (read+write) misses +system.l2c.demand_misses::1 86462 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 628381 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25198480438 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.407151 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.641867 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 626505 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 25124977461 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.377436 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.737382 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 628364 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 626485 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.065210 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.029545 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.380758 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4273.595958 # Average occupied blocks per context -system.l2c.occ_blocks::1 1936.249784 # Average occupied blocks per context -system.l2c.occ_blocks::2 24953.333071 # Average occupied blocks per context -system.l2c.overall_accesses::0 1543318 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 978963 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.066802 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.029576 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.372873 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 4377.904620 # Average occupied blocks per context +system.l2c.occ_blocks::1 1938.298251 # Average occupied blocks per context +system.l2c.occ_blocks::2 24436.623036 # Average occupied blocks per context +system.l2c.overall_accesses::0 1659846 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 849607 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2522281 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 62510.658683 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 315728.455181 # average overall miss latency +system.l2c.overall_accesses::total 2509453 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 60544.871057 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 378164.208554 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1018788 # number of overall hits -system.l2c.overall_hits::1 875112 # number of overall hits +system.l2c.overall_hits::0 1119803 # number of overall hits +system.l2c.overall_hits::1 763145 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1893900 # number of overall hits -system.l2c.overall_miss_latency 32788715799 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.339872 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.106083 # miss rate for overall accesses +system.l2c.overall_hits::total 1882948 # number of overall hits +system.l2c.overall_miss_latency 32696833800 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.325357 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.101767 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 524530 # number of overall misses -system.l2c.overall_misses::1 103851 # number of overall misses +system.l2c.overall_misses::0 540043 # number of overall misses +system.l2c.overall_misses::1 86462 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 628381 # number of overall misses -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25198480438 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.407151 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.641867 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 626505 # number of overall misses +system.l2c.overall_mshr_hits 20 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 25124977461 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.377436 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.737382 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 628364 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2264235998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 626485 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2263111998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 402142 # number of replacements -system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. +system.l2c.replacements 402176 # number of replacements +system.l2c.sampled_refs 435074 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31163.178813 # Cycle average of tags in use -system.l2c.total_refs 2096699 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124293 # number of writebacks +system.l2c.tagsinuse 30752.825907 # Cycle average of tags in use +system.l2c.total_refs 2087356 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278644000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 124146 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 6eea1f6ec..8128ce648 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -355,7 +355,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -375,7 +375,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -501,7 +501,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 00e25aeac..f6482ad23 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:35:15 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:36:15 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:37:22 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867362977500 because m5_exit instruction encountered +Exiting @ tick 1867360295500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 75071ea91..6ec7aca0a 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,447 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86499 # Simulator instruction rate (inst/s) -host_mem_usage 277924 # Number of bytes of host memory used -host_seconds 613.76 # Real time elapsed on the host -host_tick_rate 3042478511 # Simulator tick rate (ticks/s) +host_inst_rate 154746 # Simulator instruction rate (inst/s) +host_mem_usage 291744 # Number of bytes of host memory used +host_seconds 343.04 # Real time elapsed on the host +host_tick_rate 5443609822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53090223 # Number of instructions simulated -sim_seconds 1.867363 # Number of seconds simulated -sim_ticks 1867362977500 # Number of ticks simulated +sim_insts 53083414 # Number of instructions simulated +sim_seconds 1.867360 # Number of seconds simulated +sim_ticks 1867360295500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461925 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6774596 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12988394 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41867 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 814870 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12133144 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14563531 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1033178 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461193 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 999873 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.559325 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.322901 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 76387036 75.91% 75.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 10760374 10.69% 86.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5981089 5.94% 92.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 2990150 2.97% 95.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2079430 2.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 662647 0.66% 98.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 398739 0.40% 98.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 391912 0.39% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 978098 0.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 76371825 75.99% 75.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 10652369 10.60% 86.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5995069 5.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 2948172 2.93% 95.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2094039 2.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 649751 0.65% 98.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 415244 0.41% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 382142 0.38% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:count 56284559 # Number of instructions committed -system.cpu.commit.COM:loads 9308572 # Number of loads committed -system.cpu.commit.COM:membars 228000 # Number of memory barriers committed -system.cpu.commit.COM:refs 15700770 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:count 56277376 # Number of instructions committed +system.cpu.commit.COM:loads 9307406 # Number of loads committed +system.cpu.commit.COM:membars 227986 # Number of memory barriers committed +system.cpu.commit.COM:refs 15698987 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53090223 # Number of Instructions Simulated -system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated -system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 773341 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56277376 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667767 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9507253 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53083414 # Number of Instructions Simulated +system.cpu.committedInsts_total 53083414 # Number of Instructions Simulated +system.cpu.cpi 2.579204 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.579204 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.595548 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.625753 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 345718500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103721 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4847 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205988000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081158 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17435 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23910.895806 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22793.768876 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36690361000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.164206 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 450067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24717449000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116043 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084395 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904961500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.344016 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.344016 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689238000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.136420 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599277000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136420 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 29987 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 49095.565499 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54537.318055 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109486695038 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.362224 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21611393951 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064365 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 137083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 396268 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235673497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9968.474051 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.834980 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 138443 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1380065453 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15501348 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15501348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11736813 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11736813 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 146177056038 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.242852 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3764535 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3764535 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2283872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46328842951 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095518 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1480663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995450 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15499631 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::1 -0.019112 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995421 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -9.785268 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15501348 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15499631 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15501348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11736725 # number of overall hits +system.cpu.dcache.overall_hits::0 11736813 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11736725 # number of overall hits -system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.242774 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11736813 # number of overall hits +system.cpu.dcache.overall_miss_latency 146177056038 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.242852 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3762906 # number of overall misses +system.cpu.dcache.overall_misses::0 3764535 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3762906 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3764535 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2283872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46328842951 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095518 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1480663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140634997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1402110 # number of replacements -system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401152 # number of replacements +system.cpu.dcache.sampled_refs 1401664 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use -system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430447 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236133 # DTB accesses +system.cpu.dcache.tagsinuse 507.102797 # Cycle average of tags in use +system.cpu.dcache.total_refs 12383673 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430200 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48440098 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42540 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 615090 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72709786 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37935584 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12980555 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1639247 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 136073 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1152246 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1232975 # DTB accesses system.cpu.dtb.data_acv 823 # DTB access violations -system.cpu.dtb.data_hits 16770289 # DTB hits -system.cpu.dtb.data_misses 44393 # DTB misses +system.cpu.dtb.data_hits 16785642 # DTB hits +system.cpu.dtb.data_misses 44486 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 909859 # DTB read accesses -system.cpu.dtb.read_acv 588 # DTB read access violations -system.cpu.dtb.read_hits 10173052 # DTB read hits -system.cpu.dtb.read_misses 36219 # DTB read misses -system.cpu.dtb.write_accesses 326274 # DTB write accesses -system.cpu.dtb.write_acv 235 # DTB write access violations -system.cpu.dtb.write_hits 6597237 # DTB write hits -system.cpu.dtb.write_misses 8174 # DTB write misses -system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched -system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.726149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.019798 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 911401 # DTB read accesses +system.cpu.dtb.read_acv 582 # DTB read access violations +system.cpu.dtb.read_hits 10188595 # DTB read hits +system.cpu.dtb.read_misses 36193 # DTB read misses +system.cpu.dtb.write_accesses 321574 # DTB write accesses +system.cpu.dtb.write_acv 241 # DTB write access violations +system.cpu.dtb.write_hits 6597047 # DTB write hits +system.cpu.dtb.write_misses 8293 # DTB write misses +system.cpu.fetch.Branches 14563531 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8983923 # Number of cache lines fetched +system.cpu.fetch.Cycles 23375540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455206 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74277236 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 956999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106371 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8983923 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7807774 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542514 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 87829962 85.88% 85.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1051726 1.03% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2021481 1.98% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 968950 0.95% 89.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 2998384 2.93% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 688876 0.67% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 831559 0.81% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1217734 1.19% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4664036 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14917.128866 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116430 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.331981 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15609939999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.116480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 50514 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11860861000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110857 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 995930 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 10883.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.971412 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 653000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8983923 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8997144 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.demand_accesses::total 8983923 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7937479 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7949609 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116430 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7937479 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15609939999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.116480 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1046444 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1047535 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1046444 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 50514 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11860861000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.110857 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 995930 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995649 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.772438 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8997144 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995671 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.783438 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8983923 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8997144 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.overall_accesses::total 8983923 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7949609 # number of overall hits +system.cpu.icache.overall_hits::0 7937479 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7949609 # number of overall hits -system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116430 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7937479 # number of overall hits +system.cpu.icache.overall_miss_latency 15609939999 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.116480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1047535 # number of overall misses +system.cpu.icache.overall_misses::0 1046444 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1047535 # number of overall misses -system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1046444 # number of overall misses +system.cpu.icache.overall_mshr_hits 50514 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11860861000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.110857 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 995930 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 994957 # number of replacements -system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks. +system.cpu.icache.replacements 995232 # number of replacements +system.cpu.icache.sampled_refs 995743 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use -system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 509.783438 # Cycle average of tags in use +system.cpu.icache.total_refs 7937478 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25287643000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9164165 # Number of branches executed -system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate -system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6620337 # Number of stores executed +system.cpu.idleCycles 34765240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9170733 # Number of branches executed +system.cpu.iew.EXEC:nop 3662671 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420879 # Inst execution rate +system.cpu.iew.EXEC:refs 17068903 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6620272 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value -system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back +system.cpu.iew.WB:consumers 34614422 # num instructions consuming a value +system.cpu.iew.WB:count 57031603 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763117 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26380221 # num instructions producing a value -system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle -system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26414846 # num instructions producing a value +system.cpu.iew.WB:rate 0.416554 # insts written-back per cycle +system.cpu.iew.WB:sent 57130351 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 839771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9768928 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11058875 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1801420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1004974 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7015626 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65914650 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10448631 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 528111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57623776 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 52093 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6603 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1639247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554420 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 311339 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 434411 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10284 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7284 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39611417 68.15% 68.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62110 0.11% 68.27% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 46318 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 18429 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1751469 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 624045 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46318 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 408059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431712 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39633385 68.15% 68.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62109 0.11% 68.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10788116 18.56% 86.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6673339 11.48% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953263 1.64% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10799740 18.57% 86.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6666948 11.46% 98.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953172 1.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58124772 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 58151889 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 434913 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007479 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 50716 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 279321 64.50% 76.21% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 103014 23.79% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 52889 12.16% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 280249 64.44% 76.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 101775 23.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% 71.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% 85.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% 92.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% 95.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% 98.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% 99.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73060847 71.52% 71.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14641510 14.33% 85.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6377407 6.24% 92.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3918998 3.84% 95.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2506307 2.45% 98.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1046173 1.02% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 456673 0.45% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 116088 0.11% 99.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate -system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.424736 # Inst issue rate +system.cpu.iq.iqInstsAdded 60199205 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58151889 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2052774 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8775393 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1385007 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4703772 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1303750 # ITB accesses -system.cpu.itb.fetch_acv 951 # ITB acv -system.cpu.itb.fetch_hits 1264322 # ITB hits -system.cpu.itb.fetch_misses 39428 # ITB misses +system.cpu.itb.fetch_accesses 1302209 # ITB accesses +system.cpu.itb.fetch_acv 948 # ITB acv +system.cpu.itb.fetch_hits 1264828 # ITB hits +system.cpu.itb.fetch_misses 37381 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -457,51 +459,51 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175681 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175662 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192652 # number of callpals executed +system.cpu.kern.callpal::total 192631 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211789 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74950 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105947 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183030 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105933 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183009 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73583 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149305 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 102621000 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392338000 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867362103000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73583 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149292 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824774879500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 102464000 0.01% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392165500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42089912000 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867359421000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981761 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694583 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.ipl_used::31 0.694618 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5972 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5971 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319826 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320047 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3191204500 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 1.401192 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31307096500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3189085000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832863231500 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -534,29 +536,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136997789 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed -system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3116609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2798105 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11058875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7015626 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136912971 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14296513 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38253474 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1101619 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39527204 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2223744 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15702 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83467187 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68675679 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46041377 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12627654 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1639247 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5214289 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7787901 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28842822 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704528 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12805525 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256634 # count of temporary serializing insts renamed +system.cpu.timesIdled 1324969 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -572,14 +574,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -587,37 +589,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137793.747738 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85790.377840 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725605806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3564761780 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6164.456543 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10470 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64541860 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745548804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -625,7 +627,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3575708778 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -633,20 +635,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.079213 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.267415 # Average occupied blocks per context +system.iocache.occ_%::1 0.079211 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.267376 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745548804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -654,7 +656,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3575708778 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -664,137 +666,137 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267415 # Cycle average of tags in use +system.iocache.tagsinuse 1.267376 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716180121000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52374.719501 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.943752 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739179332 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 300582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 300582 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses::0 300511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 300511 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12085934495 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.745492 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 300511 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52047.601080 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.046370 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1785718 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785718 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16208195500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.148494 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 311411 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311411 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12461397000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.148493 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52274.462658 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.358873 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6800698494 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5216506000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130096 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430447 # number of Writeback hits -system.l2c.Writeback_hits::total 430447 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430200 # number of Writeback hits +system.l2c.Writeback_hits::total 430200 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. +system.l2c.avg_refs 4.595902 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2397640 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.demand_accesses::total 2397640 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency -system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency +system.l2c.demand_hits::0 1785718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses +system.l2c.demand_hits::total 1785718 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31947374832 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.255218 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 611735 # number of demand (read+write) misses +system.l2c.demand_misses::0 611922 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 611735 # number of demand (read+write) misses +system.l2c.demand_misses::total 611922 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24547331495 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.255218 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 611921 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context -system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context -system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.090196 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.378860 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5911.076462 # Average occupied blocks per context +system.l2c.occ_blocks::1 24828.993432 # Average occupied blocks per context +system.l2c.overall_accesses::0 2397640 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.overall_accesses::total 2397640 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1786590 # number of overall hits +system.l2c.overall_hits::0 1785718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1786590 # number of overall hits -system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses +system.l2c.overall_hits::total 1785718 # number of overall hits +system.l2c.overall_miss_latency 31947374832 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.255218 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 611735 # number of overall misses +system.l2c.overall_misses::0 611922 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 611735 # number of overall misses +system.l2c.overall_misses::total 611922 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24547331495 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.255218 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 611921 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926647998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396039 # number of replacements -system.l2c.sampled_refs 427720 # Sample count of references to valid blocks. +system.l2c.replacements 396067 # number of replacements +system.l2c.sampled_refs 427735 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use -system.l2c.total_refs 1966597 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119094 # number of writebacks +system.l2c.tagsinuse 30740.069893 # Cycle average of tags in use +system.l2c.total_refs 1965828 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645113000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119080 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post |