diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-01-25 17:19:50 +0000 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-01-25 17:19:50 +0000 |
commit | a17dbdf8834b84f05a8f5154a74ac819fe8adc7c (patch) | |
tree | 8761136c790b84e20d6df2e84207eca3c553984b /tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini | |
parent | bd55c9e2af7fd6c06af48a020c29cb33ba1ca3fc (diff) | |
download | gem5-a17dbdf8834b84f05a8f5154a74ac819fe8adc7c.tar.xz |
stats: Update stats for final tick and memory bandwidth patches
Diffstat (limited to 'tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini')
-rw-r--r-- | tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 665888efd..bec9490f3 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ type=System children=cpu membus physmem mem_mode=atomic memories=system.physmem +num_work_ids=16 physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -18,6 +19,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 +system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU @@ -477,7 +479,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[1] +mem_side=system.membus.port[2] [system.cpu.toL2Bus] type=Bus @@ -500,9 +502,9 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf +executable=/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -519,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory @@ -529,5 +531,5 @@ latency_var=0 null=false range=0:268435455 zero=false -port=system.membus.port[0] +port=system.membus.port[1] |