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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:25 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:25 -0600 |
commit | fe300c6de2bb5c78f34e14787908d0d0640849eb (patch) | |
tree | a57cf969c18cb7a64b3b825af7fcef3323ad48e9 /tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt | |
parent | 057b451773eb2f6042cf5a1f6d86b39a8a48eff5 (diff) | |
download | gem5-fe300c6de2bb5c78f34e14787908d0d0640849eb.tar.xz |
ARM: Add full-system regressions
Diffstat (limited to 'tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt index 7d95e3dd8..175ae2408 100644 --- a/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1157512 # Simulator instruction rate (inst/s) -host_mem_usage 330420 # Number of bytes of host memory used -host_seconds 78.77 # Real time elapsed on the host -host_tick_rate 1880000368 # Simulator tick rate (ticks/s) +host_inst_rate 795252 # Simulator instruction rate (inst/s) +host_mem_usage 393312 # Number of bytes of host memory used +host_seconds 114.65 # Real time elapsed on the host +host_tick_rate 1291628028 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91176087 # Number of instructions simulated sim_seconds 0.148086 # Number of seconds simulated @@ -74,8 +74,20 @@ system.cpu.dcache.total_refs 26356881 # To system.cpu.dcache.warmup_cycle 54482100000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 942313 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -139,8 +151,20 @@ system.cpu.icache.warmup_cycle 0 # Cy system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses |